J. Semicond. > 2014, Volume 35 > Issue 8 > 083004
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SEMICONDUCTOR MATERIALS

Investigation of charge loss characteristics of HfO2 annealed in N2 or O2 ambient

Yuqiong Chu, Zongliang Huo, Yulong Han, Guoxing Chen, Dong Zhang, Xinkai Li and Ming Liu

+ Author Affiliations

 Corresponding author: Huo Zongliang, Email:huozongliang@ime.ac.cn; Liu Ming, Email:liuming@ime.ac.cn

DOI: 10.1088/1674-4926/35/8/083004

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Abstract: The retention characteristics of electrons and holes in hafnium oxide with post-deposition annealing in a N2 or O2 ambient were investigated by Kelvin probe force microscopy. The KFM results show that compared with the N2 PDA process, the O2 PDA process can lead to a significant retention improvement. Vertical charge leakage and lateral charge spreading both played an important role in the charge loss mechanisms. The retention improvement is attributed to the deeper trap energy. For electrons, the trap energy of the HOS structure annealed in a N2 or O2 ambient were determined to be about 0.44 and 0.49 eV, respectively. For holes, these are about 0.34 and 0.36 eV, respectively. Finally, the electrical characteristics of the memory devices are demonstrated from the experiment, which agreed with our characterization results. The qualitative and quantitative determination of the charge retention properties, the possible charge decay mechanism and trap energy reported in this work can be very useful for the characterization of hafnium charge storage devices.

Key words: KFM, HfO2, retention

With the semiconductor devices scaling,the critical charge of memory cell and the distance between cells decrease strongly. Single event multiple-cell upsets (MCU) have become a main source of single event soft errors in space[1, 2, 3]. MCUs are topological multiple upsets induced by a single impinging particle,including the neighboring cells of the struck cell. MBUs (multiple-bit upsets within a word) are logical multiple upsets where more than one bit flip occurs within a word. MCUs pose a large challenge on the common circuit hardening technology which combines bit-interleaving with EDAC (error detection and correction) as MCUs sharply increase the occurrence probability of MBUs. Moreover,some classical layout hardending technologies such as DICE (dual interlocked storage cell) lose effectiveness due to the mechanism of the multiple-node charge collection. Regarding the related study,there are still some unsolved problems,like the acquisition of a single event MCU topology pattern~and the assessment of MCUs from the quantitative point of view. Meanwhile,MCUs are related to various factors which have different impacts on MCUs due to different design technologies and test conditions. Thus,it is essential that a more reasonable single event test method is developed and the effectiveness of anti-MCU strategies under different factors is assessed for space application of nanometer-scale devices.

The paper aims at carrying out heavy ion investigation on 65 nm SRAM,especially on the impacts of several test factors~on single event MCU based on the foundation of MCUs data acquiring and processing method,including the heavy ion LET,ion tilt angle,test pattern and supply voltage. The effects due to different factors are summarized,compared and analyzed. The feasibility of the current test method is also discussed.

2.1 Heavy ion facility

The heavy ion single event effect testing is carried out on the HI-13 Tandem accelerator in China's Institute of Atomic Energy. The HI-13 facility is capable of providing beams of $^{1}$H through $^{197}$Au with a range of LET from 0.0176-80.9 MeV$\cdot$cm$^{2}$/mg at normal incidence. Table1 summarizes the ions used in the testing,including the effective LET values at the device surface for different tilt angles.

Table  1.  Ions used in heavy ion accelerator experiment.
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2.2 Devices under test

The test chip is M328C fabricated in a bulk CMOS 65 nm technology. It is a synchronous single-port SRAM combined with the standard 6 transistors SRAM cells designed with one access transistor on each internal node,immune to single event latchup. The capacity is 256 kbits organized as 32 k × 8 bits. The supply voltages are 1.2 V for core circuits and 3.3 V for input/output (IO) circuits.

To measure the MCU dependency on the test pattern,the SRAM was measured at HI-13 with several test patterns of all “0”,all “1”,and a logical checkerboard using a dynamic testing mode during the irradiation period.

Irradiations are carried out at several incident angles with the operation voltage of 1.2 V and the test pattern of a logical checkerboard. The board is tilted along both the $x$-axis and $y$-axis,making two distinct device orientations to the beam. The orientation of the device is described with respect to the SRAM layout. SRAM array is laid out with alternating columns of n-wells and p-wells. Tilting with the $y$-axis corresponds to tilting “along the wells” because incidence ions at the orientation move along the long length of the wells. Tilting with the $x$-axis is pointed as tilting “against the wells” because incidence ions at the orientation are perpendicular to the well length. Irradiations are performed at three tilt angles: 0°,30°,and 60° under room temperature.

Experiments are also performed at different supply voltages ranging from 1.1 to 1.3 V with the test pattern of a logical checkerboard at the normal incidence.

2.3 Testing

Since a large proportion of upsets per read cycle would make it hard to distinguish true MCU events from false ones (two single event upsets in neighboring cells created by two different ions i.e. not simultaneously generated),the beam flux is adjusted to make sure that only a few upsets are observed in each sample cycle compared to the entire capacity. The number of cell upsets is controlled within less than 0.01% of the capacity for each cycle to avoid the influence of the false MUCs on the accuracy of MCUs statistics,resulting in a worse case probability of less than 1 × 10$^{-3}$ for creating a false two-cell MCU. 4 ms was needed for the system to finish one testing cycle. The logical addresses and data of the upsets are recorded at the end of each cycle. Upset is defined as the value of a bit being different from that from the previous read cycle.

2.4 Data processing

The relationship between the logical bitmap and the physical bitmap is built. The logical addresses need to be decoded to the physical addresses so the physical location on the memory modules could be determined. The position of the single event upset (SEU) is located to perform analysis and statistics about SCU (single-cell upset) event and MCU event,both of them belonging to SEU events.

The multiplicity of MCU can be expressed as the MCU mean value.

Mean=∞∑i=1i×Eventi−cell∞∑i=1Eventi−cell,
 (1)
where $i$ is the number of affected cells in the SEU events,${{\text{Even}}{{\text{t}}_{i - {\text{cell}}}}}$ is the number of SEU events with $i$-cell upsets. MCU mean value equals to the count of total SEUs divided by the count of total SEU events. It represents the average number of single event upsets caused by an SEU event.

The percentage of MCU is an important characteristic which reflects the sensitivity of a technology to MCU events. The percentage of all MCU events can be written as[4]

PMCU=∞∑i=2Eventi−cell∞∑i=1Eventi−cell.
 (2)

It equals to the count of all MCU events divided by the count of all SEU events. Each event is counted only once and is not weighted. Likewise,the percentage of MCU with $i$-cell upsets can be written as

PMCUi - cell=Eventi−cell∞∑i=1Eventi−cell.
 (3)

3.1 Heavy ion single event upset cross section of 65 nm SRAM

Figure1 shows the M328C heavy ion SEU cross section as a function of the effective LET. Four kinds of basic heavy ions with several tilt angles were adopted in the test. A range of effective LET values are obtained based on 1/cos law in order to get the complete SEU cross section curves.

Figure  1.  M328C heavy ion single event bit upset cross section as a function of the effective LET.
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The Weibull function only fits through data points taken at normal incidence,as shown in Figure1. The SEU cross section curve has approached saturation with LET greater than 42 MeV$\cdot$cm$^{2}$/mg at normal incidence. However,the SEU cross section still increases at tilted angle,especially for ion incident along the $y$-axis. The area of the SRAM memory cell is about 0.625 $\mu $m$^{2}$ for the 65 nm technology. The highest cross section at tilt 60° along the $y$-axis with an effective LET of 84 MeV$\cdot$cm$^{2}$ is 2.67 × 10$^{-8}$ cm$^{2}$,that is,2.67 $\mu $m$^{2}$. The cross section value is almost four times more than one cell size,indicating very serious MCU effects. Tilt angle induces more upsets simultaneously due to the charge diffusion and the bipolar amplification. The orientations of the device also have an impact on the SEU cross section. The cross section with tilting along the $y$-axis is larger than that along the $x$-axis. The underlying mechanism will be analyzed later.

Meanwhile,the cross section data at tilt angles with a low effective LET less than 20 MeV$\cdot $cm$^{2}$/mg are in good agreement with the testing results at normal incidence for the same effective LET. But it is evident that the cross section data at tilt angles with a higher effective LET more than 20 MeV$\cdot $cm$^{2}$/mg is above data at the same LET obtained at normal incidence. The 1/cos tilt test method is usually suitable for the case in which the thickness of the SEU sensitive volume is far smaller than the lateral two dimensional sizes,however the aspect ratio of the sensitive volume is high for a nanometer device. MCUs also become more predominant at a tilt angle with a high LET value,so angular dependence of an effective LET does not simply follow the 1/cos law as a result of the geometrical effect and MCU effect. Applicability of the heavy ion single event 1/cos tilt test method is correlative to device types and ion LET values.

3.2 The dependency of MCU on LET

Figure2 shows the MCU event percentage and mean value as a function of the heavy ion LET at normal incidence. MCU multiplicity and percentage evidently increase with increasing LET. For 4.2 MeV$\cdot $cm$^{2}$/mg,single event upsets are dominated by SCU. An SCU event has a proportion of up to 82% of the total event. MCU only manifests double cells upset. For LET greater than 4.2 MeV$\cdot $cm$^{2}$/mg,a main contribution of SEU events is from the MCU event. The amount and the order of the MCU events increase while the proportion of SCU decreases. For 64.7 MeV$\cdot $cm$^{2}$/mg,SCU events are only 6% of the total upset events. Higher order of MCU (greater than five-order MCU) has been up to 15%. MCU mean varies from 1.18 to 4.41 when LET increases to 64.7 MeV$\cdot $cm$^{2}$/mg. It means that an incident heavy ion can induce four cells upset simultaneously.

Figure  2.  SCU and MCU event percentage as a function of heavy ion LET.
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Secondly,the MCU topological patterns are analyzed further. Table2 shows the MCU percentage of different topological patterns versus LET. While the heavy ion is incident at normal angle,vertical double MCU is predominant in the double MCU,there only exists a handful of horizontal double MCU. Triple MCU is mainly in the vertical pattern; the L-shape pattern takes a small part. Quartette MCU basically manifests square shaped patterns and a few vertical patterns. The topological pattern of Quintuplet MCU and higher order MCU mainly shows two adjacent vertical patterns. In general,vertical MCU have a higher sensitivity than horizontal MCU.

Table  2.  MCU percentage of different topological patterns versus LET.
DownLoad: CSV  | Show Table

The electron-hole pairs are initially generated within the ion's track region after a heavy ion strikes the device sensitive node. A part of the deposited charge is directly collected by drift for neighboring cells. The rest charge spreads in all directions and is collected further by more adjacent cells during the diffusion process. With the increase of LET,the amount of the diffusion charge is more,the diffusion length is longer,and parasitic bipolar transistors are easier to turn on,so this will cause more cells upset.

3.3 The dependency of MCU on tilt angle

The percentage of SCU and MCU events versus the tilt angle along the $y$-axis for a fluorine ion is shown in Figure3. Variations of the tilt angle from 0° to 60° increase the MCU proportion,multiplicity and order. The MCU percentage is 18% with tilting of 0°,30% with tilting of 30° and 73% with tilting of 60°. The MCU mean value increases from 1.18 to 2.08 in turn. A larger tilt angle will induce a higher order MCU. The MCU only shows a double MCU for tilting of 0°. Triple MCUs and a small quantity of quartette MCUs occur with tilting of 60°. Double MCUs are all vertical patterns. Vertical double MCUs have a large advantage over horizontal double MCUs with tilting angle along the $y$-axis.

Figure  3.  MCU and SCU event percentage versus tilt angle along $y$-axis for fluorine ion.
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Therefore,MCU response evidently depends on the tilt angle. The MCU proportion increases as the tilt angle increases. When heavy ion is incident with the tilt angle,the trajectories of the incident ions cross underneath multiple reversed-bias drain. The ions will interact with more cells and increase the probability of MCU. Besides that the charge is collected through drift and diffusion,the majority carriers are deposited into the well and cause the well potential collapse. This in turn leads to multiple parasitic bipolar transistors turning on. More cells will upset all together due to additional carriers injected from the source. A vertical seven-order MCU is even observed with a tilt angle of 60° at Br incidence. According to the calculation based on the size of memory cell layout,the well collapse can extend to about 4.5 $\mu $m from the strike location with a large tilt angle along the $y$-axis for high LET.

3.4 The dependency of MCU on device orientation

Figure4 shows the percentage of SCU and MCU events with tilting incidence along different device orientations for a fluorine ion. The MCU percentage of different topological patterns versus device orientation for the fluorine ion is given in Table3. Even if the tilt angle is kept the same,the MCU proportion has an obvious difference with different device orientation. While the ion is incident along the $x$-axis,the percentage of MCU is only 21% and only a double MCU occurs,this only shows a slight angular effect of MCU compared with normal incidence. It is noted that the horizontal double MCU events take up half of the total double MCU events along the $x$-axis. However,the ratio of MCU can be up to 73% with the incidence along the $y$-axis. The ratio of triple and quartette MCU has been up to 33%. All the MCU patterns are the vertical pattern along the $y$-axis,whether a double MCU,triple MCU or quartette MCU. The MCU pattern presents a track-orientation characteristic along the trajectories of the incident ions. With the increase of LET,such as the Br ion,the incident ion will also cause a horizontal MCU even if the ion is incident along the $y$-axis. But the maximum number of horizontal MCUs is only two-order,whether incidence along the $y$-axis or along the $x$-axis. That is,only two column cells can be affected simultaneously. This can make the probability of accumulating MBU stay low. At present,the maximum size of MCU pattern can be up to 6 row × 2 column along the $y$-axis and 4 row × 2 column along the $x$-axis with tilting of 60° for Br incidence.

Figure  4.  Percentage of SCU and MCU event with tilting incidence along different device orientation.
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Table  3.  MCU percentage of different topological pattern versus device orientation for fluorine ion.
DownLoad: CSV  | Show Table

Three factors can cause the dependence of MCU on device orientation. Firstly,the layout of the SRAM cell (shown in Figure5) results in alternating columns of n-wells containing PMOS and p-wells containing NMOS. The ion incidence along the $x$-axis corresponds to against the wells. The ion's trajectory is separated by the alternating wells and multiple reverse biased n-well/p-well junctions need to be crossed,so less charge sharing takes place. Ion incidence along the $y$-axis is referred as along the well. This can lead to greater charge sharing and modulation of the well potential[5, 6, 7]. Secondly,the region between two vertical adjacent off-NMOS sensitive nodes shares a silicon diffusion region while the region between the horizontal adjacent off-NMOS sensitive nodes is an oxide region. An ion striking between the two sensitive nodes will cause more charge to be shared in the silicon diffusion region than in the oxide region[5]. Thirdly,cell length in the against-the-wells direction is about twice the cell width in the along-the-wells direction. Ions incident along this orientation must travel a longer distance if multiple horizontal cells of more than two occur. The resulting MCU events are characterized by many affected rows and few affected columns.

Figure  5.  Nine adjacent SRAM cells: dashed rectangles are bitcells. Striped and white squares are respectively drains of NMOS and PMOS. Black squares are sensitive drains of off-NMOS and off-PMOS.
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3.5 The dependency of MCU on test pattern

To understand the dependence of SEU and MCU on the test pattern,it is necessary to identify the relative locations of the sensitive nodes within the SRAM array with the different patterns in conjunction with the information of device layout,thus acquiring the worst test pattern affecting SEU and MCU.

Due to the use of bit-interleaving technology,the successive bits are separated,all memory was thus divided into large regions with “1” and “0” when the memory is filled with the test pattern of a logical checkerboard. The width of these regions is 16 cells according to the SRAM design. All the cells are the state of “1” or “0” when filled with an all “1” or all “0” pattern. Figure5 shows the position of the adjacent sensitive nodes with the all “1” pattern. Actually,the situation with all “0” is the same as all “1”. So there was no physical difference of sensitive nodes among these patterns: a logical checkerboard,all “1” and all “0”. Therefore,MCU event percentage with the three test patterns is the same as shown in Figure6. As the sensitive nodes in the off-NMOS are adjacent vertically as well as horizontally,this can cause the maximum MCU size,the three patterns are the worst MCU test pattern. If the memory is filled with a physical checkerboard,the sensitive nodes are only adjacent diagonally,this case is not the worst case for MCU.

Figure  6.  M328C SCU and MCU event percentage with different test patterns for Cl ion.
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3.6 The dependency of MCU on supply voltage

Generally,the critical charge which is the minimum charge causing a single event upset is decreased proportionally to the supply voltage,so accordingly the SEU cross section increases. However,when the feature size scales to the nanometer scale,the influence of supply voltage on the SEU cross section may have a different characteristic. Furthermore,the effect of the supply voltage on the MCU is not understood clearly yet.

The testing data shows the SEU cross section has no visible dependence on supply voltage for the 65 nm SRAM. With technology scaling,there are competing mechanisms that both increase and decrease the SEU cross section. The susceptibility to upset is increased due to the lower supply voltage and critical charge. On the other hand,charge collection efficiency of the sensitive node is reduced; the probability of upsets is decreased. These off-setting factors contribute to a relatively weak net difference in the SEU cross section per bit with the different voltage.

Figure7 shows the percentage of SCU and MCU events as a function of the supply voltage with the incidence of Chlorine ion. MCU percentage and mean increase slightly with the reduction of supply voltage. As charge collection efficiency of the sensitive nodes and well taps decreases,more charges diffuse and are collected by adjacent cells,so the parasitic bipolar effect is triggered more easily due to the higher susceptibility of well potential collapse.

Figure  7.  Percentage of SCU and MCU event versus supply voltage with incidence of Chlorine ion.
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Based on the buildup of the MCU data acquiring and the processing method,a further investigation about the impacts of several factors on~single event MCU is carried out on 65 nm SRAM,including the heavy ion LET value,the tilt angle,the device orientation,the test pattern and the supply voltage,the MCU physical bitmaps are extracted correspondingly.

The MCU multiplicity and percentage evidently increase with LET. The impact of the tilt angle on MCU response augments is due to the stronger charge sharing. The test results show that the MCU also depends on the orientation of the device. The sensitivity of the influence of device orientation on MCU is closely related to the direction of the incident ion with respect to the layout of the cell. Due to the use of bit-interleaving technology,the three patterns of a logical checkerboard,all “1” and all “0” are all the worst MCU test patterns and can cause the maximum MCU size. The SEU cross section has no visible dependency on the supply voltage for the 65 nm SRAM as a result of competing mechanisms. The MCU percentage increases slightly with the reduction of supply voltage. It is worth noting that the angular dependency of the effective LET does not simply follow the 1/cos law for a higher LET value in virtue of the increase of MCU percentage. All these works lay a foundation for developing a scientific heavy ion ground modeling test method on nanometer-scale devices.



[1]
Kim K. From the future Si technology perspective:challenges and opportunities. Electron Devices Meeting, 2010, 1(1):1 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5703274
[2]
Wang Y Q, Hwang W S, Zhang G, et al. Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3N4 tunneling layer. IEEE Trans Electron Devices, 2007, 54(10):2700 http://ieeexplore.ieee.org/document/4317755/
[3]
You H W, Cho W J. Charge trapping properties of the HfO2 layer with various thicknesses for charge trap flash memory applications. Appl Phys Lett, 2010, 96(9):093506 doi: 10.1063/1.3337103
[4]
Yuan C L, Chan M Y, Lee P S, et al. Al2O3 nanocrystals embedded in amorphous Lu2O3 high-k gate dielectric for floating gate memory application. J Phys:Conference Series, 2007, 61(1):1312 http://adsabs.harvard.edu/abs/2007JPhCS..61.1312Y
[5]
Ding S J, Zhang D W, Wang L K. Atomic-layer-deposited Al2O3-HfO2 laminated and sandwiched dielectrics for metal-insulator-metal capacitors. J Phys D:Appl Phys, 2007, 40(4):1072 doi: 10.1088/0022-3727/40/4/023
[6]
Maikap S, Rahaman S Z, Tien T C, et al. Nanoscale (EOT = 5.6 nm) nonvolatile memory characteristics using n-Si/SiO2/HfAlO nanocrystal/Al2O3/Pt capacitors. Nanotechnology, 2008, 19(43):435202 doi: 10.1088/0957-4484/19/43/435202
[7]
Sugizaki T, Kohayashi M, Ishidao M, et al. Novel multi-bit SONOS type flash memory using a high-k charge trapping layer. Symposium on VLSI Technology, 2003:27 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=1221069
[8]
Spiga S, Driussi F, Lamperti A. Experimental and simulation study of the program efficiency of HfO2 based charge trapping memories. Solid-State Device Research Conference (ESSDERC), 2010:408 http://ieeexplore.ieee.org/abstract/document/5618194/
[9]
Zhu Chenxin, Yang Rong, Huo Zongliang, et al. Investigation of charge trap and loss characteristics for charge trap memory by electrostatic force microscopy. Non-Volatile Memory Technology Symposium (NVMTS), 2011:1 http://ieeexplore.ieee.org/document/6137099/
[10]
Chowdhury N A, Garg R, Misra D, et al. Charge trapping and interface characteristics of thermally evaporated HfO2. Appl Phys Lett, 2004, 85(15):3290 doi: 10.1063/1.1805708
[11]
Ryan J T, Yu L C, Han J H, et al. A new interface defect spectroscopy method. IRPS, 2011:203 http://ieeexplore.ieee.org/document/5872242/
[12]
Uren M J. The properties of individual Si/SiO2 defects and their link to 1/f noise. Mater Sci Forum, 1992, 83-87:1519 doi: 10.4028/www.scientific.net/MSF.83-87
[13]
Girard P. Electrostatic force microscopy:principles and some applications to semiconductors. Nanotechnology, 2001, 12(4):485 doi: 10.1088/0957-4484/12/4/321
[14]
Tzeng S D, Gwo S. Charge trapping properties at silicon nitride/silicon oxide interface studied by variable-temperature electrostatic force microscopy. J Appl Phys, 2006, 100(2):023711 doi: 10.1063/1.2218025
[15]
Baik S J, Lim K S. Lateral redistribution of trapped charges in nitride/oxide/Si (NOS) investigated by electrostatic force microscopy. Nanoscale, 2011, 3:2560 doi: 10.1039/c1nr10104h
[16]
Chen Yong, Zhao Jianming, Han Dedong, et al. Extraction of equivalent oxide thickness for HfO2 high k gate dielectrics. Chinese Journal of Semiconductors, 2006, 27(5):852
Fig. 1.  Schematic sample structure and KFM analysis method (a) charge injection with contact mode and (b) contact potential differences (CPDs) measurement.

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Fig. 2.  The measured CPDs profiles after injection of electrons and holes of samples annealed in (a) N$_{2}$ and (b) O$_{2}$ ambient (c) injected electron and hole density in 0 s and after 7560 s.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  Normalized electron and hole densities ($\sigma _{\rm T}$ /$\sigma _{\rm T 0})$ evolution versus the elapsed time corresponding to samples annealed in a N$_{2}$ and O$_{2}$ ambient, which present the overall performance of retention. }

DownLoad: Full-Size Img PowerPoint
Fig. 4.  Charge density line profiles (dot lines) and their fitted curve using Eq. (1) (thin lines) of devices annealed in N$_{2}$ ambient.

DownLoad: Full-Size Img PowerPoint
Fig. 5.  (a) CPD decay profiles of the sample with HfO$_{2}$ trapping layer at 90 ℃ and 25 ℃. (b) ln($\sigma _{\rm I})$-$t$ plots, which are converted from CPD peak values by assuming charges are distributed at the interface, where $E_{\rm T}$ is the effective trap energy. (c) Relationship between $\tau T^{2}$ (unit: sK$^{2})$ and $1/T$ (unit: K$^{-1})$, where $\alpha $ is the combination of temperature independent constants, and $e_{\rm bb}$ is the direct tunneling of electrons through the oxide from HfO$_{2}$ conduction band into the silicon conduction band.

DownLoad: Full-Size Img PowerPoint
Fig. 6.  The high-frequency (100 kHz) $C$-$V$ hysteresis of the two samples under $\pm $15 V sweep voltage.

DownLoad: Full-Size Img PowerPoint
Fig. 7.  Data retention properties at 25 ℃ and 85 ℃ with an identical initial $V_{\rm fb}$ of samples annealed in N$_{2}$ and O$_{2}$ ambients.

DownLoad: Full-Size Img PowerPoint
Fig. 8.  Gate leakage current properties at data retention properties at 25 ℃ and 85 ℃ of samples annealed in N2 and O2 ambients.

DownLoad: Full-Size Img PowerPoint

Table 1.   Extracted diffusion coefficients for different samples.

Table 2.   Extracted trap energy levels for different samples. Unit: eV
[1]
Kim K. From the future Si technology perspective:challenges and opportunities. Electron Devices Meeting, 2010, 1(1):1 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5703274
[2]
Wang Y Q, Hwang W S, Zhang G, et al. Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3N4 tunneling layer. IEEE Trans Electron Devices, 2007, 54(10):2700 http://ieeexplore.ieee.org/document/4317755/
[3]
You H W, Cho W J. Charge trapping properties of the HfO2 layer with various thicknesses for charge trap flash memory applications. Appl Phys Lett, 2010, 96(9):093506 doi: 10.1063/1.3337103
[4]
Yuan C L, Chan M Y, Lee P S, et al. Al2O3 nanocrystals embedded in amorphous Lu2O3 high-k gate dielectric for floating gate memory application. J Phys:Conference Series, 2007, 61(1):1312 http://adsabs.harvard.edu/abs/2007JPhCS..61.1312Y
[5]
Ding S J, Zhang D W, Wang L K. Atomic-layer-deposited Al2O3-HfO2 laminated and sandwiched dielectrics for metal-insulator-metal capacitors. J Phys D:Appl Phys, 2007, 40(4):1072 doi: 10.1088/0022-3727/40/4/023
[6]
Maikap S, Rahaman S Z, Tien T C, et al. Nanoscale (EOT = 5.6 nm) nonvolatile memory characteristics using n-Si/SiO2/HfAlO nanocrystal/Al2O3/Pt capacitors. Nanotechnology, 2008, 19(43):435202 doi: 10.1088/0957-4484/19/43/435202
[7]
Sugizaki T, Kohayashi M, Ishidao M, et al. Novel multi-bit SONOS type flash memory using a high-k charge trapping layer. Symposium on VLSI Technology, 2003:27 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=1221069
[8]
Spiga S, Driussi F, Lamperti A. Experimental and simulation study of the program efficiency of HfO2 based charge trapping memories. Solid-State Device Research Conference (ESSDERC), 2010:408 http://ieeexplore.ieee.org/abstract/document/5618194/
[9]
Zhu Chenxin, Yang Rong, Huo Zongliang, et al. Investigation of charge trap and loss characteristics for charge trap memory by electrostatic force microscopy. Non-Volatile Memory Technology Symposium (NVMTS), 2011:1 http://ieeexplore.ieee.org/document/6137099/
[10]
Chowdhury N A, Garg R, Misra D, et al. Charge trapping and interface characteristics of thermally evaporated HfO2. Appl Phys Lett, 2004, 85(15):3290 doi: 10.1063/1.1805708
[11]
Ryan J T, Yu L C, Han J H, et al. A new interface defect spectroscopy method. IRPS, 2011:203 http://ieeexplore.ieee.org/document/5872242/
[12]
Uren M J. The properties of individual Si/SiO2 defects and their link to 1/f noise. Mater Sci Forum, 1992, 83-87:1519 doi: 10.4028/www.scientific.net/MSF.83-87
[13]
Girard P. Electrostatic force microscopy:principles and some applications to semiconductors. Nanotechnology, 2001, 12(4):485 doi: 10.1088/0957-4484/12/4/321
[14]
Tzeng S D, Gwo S. Charge trapping properties at silicon nitride/silicon oxide interface studied by variable-temperature electrostatic force microscopy. J Appl Phys, 2006, 100(2):023711 doi: 10.1063/1.2218025
[15]
Baik S J, Lim K S. Lateral redistribution of trapped charges in nitride/oxide/Si (NOS) investigated by electrostatic force microscopy. Nanoscale, 2011, 3:2560 doi: 10.1039/c1nr10104h
[16]
Chen Yong, Zhao Jianming, Han Dedong, et al. Extraction of equivalent oxide thickness for HfO2 high k gate dielectrics. Chinese Journal of Semiconductors, 2006, 27(5):852

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    Yinhong Luo, Fengqi Zhang, Hongxia Guo, Yao Xiao, Wen Zhao, Lili Ding, Yuanming Wang. Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM[J]. Journal of Semiconductors, 2015, 36(11): 114009. doi: 10.1088/1674-4926/36/11/114009
    Y H Luo, F Q Zhang, H X Guo, Y Xiao, W Zhao, L L Ding, Y M Wang. Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM[J]. J. Semicond., 2015, 36(11): 114009. doi: 10.1088/1674-4926/36/11/114009.
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    Received: 10 January 2014 Revised: 10 March 2014 Online: Published: 01 August 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(8): 083004
      Yinhong Luo, Fengqi Zhang, Hongxia Guo, Yao Xiao, Wen Zhao, Lili Ding, Yuanming Wang. Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM[J]. Journal of Semiconductors, 2015, 36(11): 114009. doi: 10.1088/1674-4926/36/11/114009 ****Y H Luo, F Q Zhang, H X Guo, Y Xiao, W Zhao, L L Ding, Y M Wang. Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM[J]. J. Semicond., 2015, 36(11): 114009. doi: 10.1088/1674-4926/36/11/114009.
      Citation:
      Yuqiong Chu, Zongliang Huo, Yulong Han, Guoxing Chen, Dong Zhang, Xinkai Li, Ming Liu. Investigation of charge loss characteristics of HfO2 annealed in N2 or O2 ambient[J]. Journal of Semiconductors, 2014, 35(8): 083004. doi: 10.1088/1674-4926/35/8/083004 ****
      Y Q Chu, Z L Huo, Y L Han, G X Chen, D Zhang, X K Li, M Liu. Investigation of charge loss characteristics of HfO2 annealed in N2 or O2 ambient[J]. J. Semicond., 2014, 35(8): 083004. doi: 10.1088/1674-4926/35/8/083004.
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      Investigation of charge loss characteristics of HfO2 annealed in N2 or O2 ambient

      DOI: 10.1088/1674-4926/35/8/083004

      • Laboratory of Nano-Fabrication and Novel Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

      Funds:

      the National Natural Science Foundation of China 61176073

      the MOST 2011CBA00600

      the MOST 2010CB934200

      Project supported by the MOST (Nos. 2010CB934200, 2011CBA00600) and the National Natural Science Foundation of China (No.61176073)

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