J. Semicond. > 2014, Volume 35 > Issue 8 > 085001

SEMICONDUCTOR INTEGRATED CIRCUITS

Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method

Jia Zhang1, 2, Haigang Yang1, , Jiabin Sun1, Le Yu1 and Yuanfeng Wei1

+ Author Affiliations

 Corresponding author: Yang Haigang, Email:yanghg@mail.ie.ac.cn

DOI: 10.1088/1674-4926/35/8/085001

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Abstract: This paper proposes a novel technique for modeling the electrostatic discharge (ESD) characteristic of the enclosed-gate layout transistors (ELTs). The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELT is decomposed into edge and corner transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM (Berkeley Short-channel IGFET Model). Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification.

Key words: Electrostatic dischargeEnclosed-gate layout transistormodelingconformal mapping

Electrostatic discharge (ESD) protection has become an important task on the reliability of CMOS ICs. MOS field effect transistor (MOSFET) is currently the most widely used as an ESD protection structure because of its active discharge mechanism and compatibility to CMOS technologies. But in radiation harsh environments, such as space and nuclear applications, ionizing radiation could induce an inversion layer at the bird's beak or shallow trench corner, giving rise to leakage current paths from the drain to the source, and lead to permanent damage to the MOSFETs serving ESD protection. In this situation, layout techniques for the reliable operation of MOS devices are needed, and enclosed-gate layout transistors (ELTs) are widely used as ESD protection devices[1-3].

It is quite laborious and time-consuming to do the ESD design with ELTs in the traditional "trial and error-fixing" approach, which can be greatly enhanced by the ability to perform circuit level simulations of the protection circuits. However, most available simulators do not cover the high current region of the ESD protection devices, nor take the special characteristics of ELT into account. As a result, an accurate model of ELT is very important for the design and simulation of the ESD protection circuits.

Some previous research on ELT modeling has been reported. In Ref. [4], ELT is proved to have better ESD performance than standard MOSFETs in area and reliability, but this design is performed in the traditional approach based on ESD measurements, and no available model is extracted. In Refs. [5, 6], SPICE models for ELT are developed, but these models only focused on the static, small signal, and noise performance of the ELT, and could not reflect the special characteristic of ELT under ESD events.

To help the design and optimization of ESD protection circuits, circuit level simulations are needed and several reported models of standard MOS devices have been considered. In Refs. [7, 8], the ESD model of MOSFET is constituted with a bipolar transistor (BJT), a current source, and a substrate resistor. These models always have discontinuity problems and need excess improvement to be implemented into SPICE, leading to limited availability. In Ref. [9], the MOS device is modeled in the Verilog-A language, but it possesses low simulation speed and may cause convergence problems. In Refs. [10, 11], standard SPICE models, such as the Gunnel-Poon and VBIC models, are used to describe the ESD characteristics of MOSFETs. However, the parameters required to define the bipolar transistor in these models are not suitable for ELTs, and the extraction methodology needs to be improved.

In this paper, a novel circuit model of ELT as an ESD protection device is explained. Our model is constructed with the main ELT, the parasitic bipolar transistor, and a parasitic substrate resistor[17]. Using the conformal mapping technique, the ELT is approximated to a linear combination of several standard MOSFETs, each modeled by BSIM3[13]; the parasitic BJT is modeled with Philips Mextram model[14]. The external current sources that existed in the previous models have been modeled internal to BSIM3 and Mextram, making the model easily to be implemented in SPICE, and improving the simulation speed. The equivalent circuit parameters are extracted from measurement, and good agreement of the generated models to measured data is achieved for ESD characteristics.

N-channel MOSFETs were fabricated using an enclosed-gate layout and p+ guard rings, and the layout diagram of the ELT is shown in Fig. 1, where L is the minimum distance between the drain and the source, c is the length of the corner, and d is the side length of the drain after cutting down. The drain diffusion is in the middle, encircled by the channel and the source diffusion. Placing the drain in the middle makes the substrate contact closer to the source and reduces the drain resistance. Different shapes of the layout, such as circular, square, rectangular with stressed edges, octagonal and square with the corner cut at 45 (broken corners), have been considered[4, 12]; the square with the corner cut at 45 (broken corners) was chosen for convenience of manufacture and area. Compared with the octagonal device, the current in the broken corner geometry mainly flows in two orthogonal directions, assuring better homogeneity as well as device matching.

Figure  1.  Layout diagram of the ELT

The electric field in the channel of ELTs is of an anomalous formation, as Figure 2 shows. To solve this electrostatic problem, the conformal mapping technique is adopted, in which the basic idea is to turn a problem, difficult to study analytically, into a simpler geometrical one according to the Riemann mapping theorem[12]. The mapping preserves local angles, and the real and imaginary parts of the mapping function satisfy Laplace's equation. To help find a solution, Schwartz-Christoffel transformation is introduced, in which polygonal regions are mapped onto a half-plane preserving the orthogonality of electric field vectors and the equipotential curves. By studying the electric field in the channel, the ELT can be decomposed into edge and corner transistors, shown as T1, T2 and T3 in Fig. 1. The border between T1 and T2 is the electric field line running from point A to point D, and point D is placed at a distance of αL from the corner point C, as Figure 2 shows. It is very difficult to know the priori value of α, but in our case α = 0.05 is considered to be a reasonable estimate[6].

Figure  2.  Electric field in the channel of ELT

In the analysis, all the electrical parameters are assumed to be the same in the ELT[12]. T1 and T2 are approximated by the two trapezia with bases and heights as shown in Fig. 3, and T3 is approximated by a standard MOS transistor with channel width = c and channel length = 2L. More details of the ELT model are discussed in Section 3.

Figure  3.  Approximation of T1 and T2

One of the simplest MOS ESD protection devices is the so-called grounded-gate NMOS (ggNMOS) structure, where the drain (D) goes to an I/O pad and the gate (G), source (S) and body (B) are shortened together to ground. The cross-sectional view of grounded-gate ELT and its equivalent circuit is shown in Fig. 4. The principle of the ggNMOS structure in ESD protection operation is explained as follows. As a positive ESD transient appears at an I/O pad, i.e., D, with respect to the ground, the DB junction is reverse-biased all the way until its breakdown. Then avalanche multiplication takes place and electron-hole pairs are generated. Hole current Isub flows into the ground through the lateral parasitic resistance Rsub, and builds up a potential VB. Since the B and S regions are shortened together, VB actually appears across the BS PN junction positively. As VB increases, the BS junction turns on, eventually triggers the parasitic lateral NPN transistor[8]. As a result, the ELT is turned on at a triggering point, Vt1, under ESD pulse and moves into a snapback region to form a low-impedance discharge channel with low holding voltage, Vh.

Figure  4.  A schematic cross-sectional view of ELT

The circuit model for ESD simulation of the ELT is shown in Fig. 5. BSIM3 is used to model the ELT itself, and the Philips Mextram model is used to characterize the parasitic lateral NPN transistor. These two elements model the ggNMOS protection device, with the drain of the NMOS connected directly to the I/O pin. The substrate current Isub is modeled using the substrate current modeling in BSIM3 (Isub_MOS) and avalanche current modeling in Mextram (Iav_BJT).

Figure  5.  The circuit model for ESD simulation of the ELT

In the BSIM3 model, the general current equation at any point x along the channel is given by[13]

Ids=WCox[VgstAbulkVds(x)]μeffE(x)1+E(x)/Esat,
(1)

where Vgst = Vgs -Vth, μeff is the effective mobility of the carriers, W is the device channel width, Cox is the gate capacitance per unit area, Abulk is used to take into account the bulk charge effect, E(x) is the electric field at the x point, and the drift velocity saturates at E(x)=Esat. From Eq. (1) we can get

E(x)=IdsμeffWCox[VgstAbulkVds(x)]Ids/Esat=dV(x)dx.
(2)

For a standard MOS device, the channel width is constant and independent with x; but for the ELT, the channel width is a function of x. To calculate Ids, the ELT is divided into three parts as Figure 2 shows. T1 and T2 are approximated by MOS transistors with a trapeziform gate, and T3 is an approximate by standard MOS transistors, as Figure 3 shows. The trapeziform gate width is

WT1(x)=d2αx,
(3)
WT2(x)=L2(1α)Δαx.
(4)

Take T1 as an example, the expression of IT1ds is calculated by integrating x from 0 to L, and V(x) from 0 to Vds. Then we can get

IT1ds=μeffCOX1M111+Vds/EsatL(VgstAbulkVds/2)Vds,
(5)

where M1 is

M1=L01WT1(x)dx.
(6)

Considering the velocity saturate effect, then Equation (5) becomes

IT1ds=LM1CoxV2gstVgst+AbulkEsatLυsat,
(7)

where υsat is the saturated carrier drift velocity, which is

υsat=μeffEsat/2.
(8)

From the analysis above, the effective channel width and length of T1 is calculated, and T1 can be approximated by standard BSIM transistors. In the same way, we can get the effective geometric parameters of T2 and T3, listed in Table 1.

Table  1.  The effective channel width and length of T1, T2 and T3
DownLoad: CSV  | Show Table

The BSIM model of T1, T2, T3 is established with the effective parameters in Table 2, and the whole ELT can be modeled as a combination of these BSIM transistors. The drain current of ELT is

Table  2.  Critical parameters of the snapback curve
DownLoad: CSV  | Show Table
Ids0=4(IT1ds+2IT2ds+IT3ds).
(9)

BSIM3 model takes the influence of impact ionization of carriers in the high field region into account. If electrons in the channel of an n-MOSFET acquire more than about 1.5 eV of energy, impact ionization could occur. During the process of impact ionization, electron-hole pairs are generated, and these electrons are either attracted to the drain (contributing to the additional drain current) or, if possessing sufficient energy, injected into the oxide. The generated holes, on the other hand, enter into the substrate and constitute a parasitic substrate current Isub.

The substrate current in the BSIM3 model is given by[13]

Isub_MOS=(α1+α0Leff)(VdsVdseff)×exp(β0VdsVdseff)Ids0,
(10)

where Ids0 is the drain current without considering impact ionization, Leff is the effective channel length of the MOS, Vdseff is the effective drain-source voltage, α0 and β0 are impact ionization coefficients, and α1 is a fitting parameter which improves the Isub scalability. The gate voltage dependence of the multiplication factor resulting from the gate coupling between the MOS and the parasitic BJT is included in this equation.

The Philips Mextram model is used to express the characteristic of the parasitic bipolar. The main current of the Mextram model is[14]

IC=IS(expVBEVTexpVBCVT)1qB,
(11)

where IS is the transistor main saturation current, qB is the normalized base charge, and VT=Kt/q is the thermal voltage. When the transistor works as an amplifier, which means the base-emitter junction is forward-biasing and VBC < 0, Equation (11) can be expressed as

ICISexpVBEVT1qB.
(12)

As Figure 4 shows, the voltage drop in the substrate is given by VBE=IsubRsub. As VBE approaches about 0.8 V, the source-substrate junction will become forward-biasing and make the parasitic bipolar begin to turn on. IE, IC, IB are used to represent the emitter current, collector current and base-emitter current, respectively. At node B', the total substrate current Isub in Fig. 4 is given by

Isub+IB=Isub_MOS+Iav1,
(13)

where Isub_MOS is the MOS drain-substrate avalanche current and Iav1 is the Mextram collector-base weak-avalanche current. Iav1 is a function of the avalanche multiplication factor M, and can be expressed as

Iav1=(M1)IC.
(14)

In the Mextram model, the variable GEM =M1 is used to model the weak-avalanche current, which is[14]

GEM=AnBnλDEM{exp(BnEM)exp[BnEM(1+WeffλD)]},
(15)

where An and Bn are material constants given by

An=7.03×107,Bn=1.23×108.
(16)

EM is the maximum electric field, λD is the point in the space-charge region where the extrapolation of the electric field is zero, and Weff is the effective epilayer width. EM and λD can be computed using

EM=Vdc+VCB+2VAVLWAVLVdc+VCBVdc+VCB+WAVL,
(17)
λD=W2AVLEM2VAVL,
(18)

where Vdc is the collector-base diffusion voltage, VCB is the collector-base reverse voltage, and Wavl and Vavl are the avalanche fitting parameters. The most important contribution to the avalanche current is the first exponential term, which is determined by EM. For large collector-base biases, EM is almost equal to VCB/Wavl. Therefore, the effective thickness Wavl over which the electric field is appreciable is the most important parameter. The second parameter Vavl only determines the curvature of the avalanche current as a function of bias.

For an ESD model of ELT, the accuracy of simulation not only depends on a correct description of physical phenomena, but also on a reliable parameter extraction method. The use of a very sophisticated model with poorly determined parameters will result in a bad prediction of circuit performance, so the strategy for the extraction of the model parameters is an important task.

The transmission-line pulse generator (TLPG) with a pulse width of 100 ns is used to get the I-V characteristics of the ELT. Just like the standard MOS device, ELT also shows a snapback phenomenon when used as an ESD protection device. During the process of model extraction, several key points of the snapback curve should be taken seriously. The critical parameters of the snapback curve are the "turn-ON point" (Vt1 and It1), "hold-on"point (Vh and Ih), and the second breakdown voltage and current (Vt2 and It2). These parameters are listed in Table 2.

First, the effective aspect ratio of the ELT should be extracted from measurements. The strategy of the extraction of (W/L)eff is illustrated in Ref. [12]. The estimated aspect ratio, evaluated for several α, has been compared with that extracted from numerical simulations and experimental measurements. Then we can get the appropriate value of α, Weff and Leff of the ELT.

Second, the impact ionization coefficients: α0, α1 and β0 are extracted. In order to reflect the drain-induced breakdown mechanisms properly, these parameters are extracted mainly from the portion of the snapback curve closed to the "turn-ON point". The Isub model may not be consistent with the measurement result accurately when Vds is far off below Vt1, but this is not the critical issue we are concerned with. The ELT parameters are shown in Table 3.

Table  3.  Parameters extracted from measurements
DownLoad: CSV  | Show Table

The avalanche multiplication factor M (or GEM) is the most important parameter to be extracted. This is determined before bipolar "turn-on" takes place. After the parasitic bipolar turns on, some of the generation current will flow into the emitter, and the impact ionization coefficients cannot be extracted from measurements. For the computed GEM, the Mextram avalanche parameters, Wavl and Vavl, are extracted. Wavl is the effective epilayer thickness and decided EM directly, while Vavl decides only the curvature of the avalanche current and is chosen to be small.

Then the avalanche and main current of the parasitic bipolar is determined in the linear region of the measurement curve, after the "hold-on" point. In this region there is:

ID=IC+Iav_BJT+IdsIC(GEM+1).
(19)

Then from Eqs. (13) and (16) we can get:

Isub=Isub_MOS+Iav_BJTIBIav_BJTIB=IC(GEM1βf).
(20)

Then the important variables, like IS and βf, are extracted from the measurement results of ID and Isub. IS determines the range of the bipolar current, and βf determines the "hold-on" voltage of the ELT. The parasitic bipolar parameters are also shown in Table 3.

The variable Rsub has an important role in biasing the bipolar transistor. As VBE=IsubRsub, and IC is a function of exp(VBE/VT), so small changes in VBE will have a big influence on IC. With Isub extracted from measurements, Rsub can be calculated since VBE is usually in the range 0.7 < VBE < 0.9 and is taken to be 0.8 V at the "turn-ON" point[8].

The proposed ESD protection ELT is placed between the I/O pad and the internal circuit, and fabricated in a 0.13-μm CMOS process. The chip microphotograph and the layout of the ELT are shown in Fig. 6. The PLT has an effective channel width of about 320 μm and an effective channel length of 0.355 μm, and occupies an active area of 1600 μm2. Using a TLPG system, the I-V characteristics of ELT are measured and a comparison between the experimental and simulation results is shown in Fig. 7. From the figures, we can see that the device turns "ON" at Vt1 = 6.2 V and It1 = 4.35 mA. For the next higher input voltage, the device snaps back to its "hold-on" voltage Vh = 5.6 V and the current through the drain increases to Ih = 108.2 mA. After this point, the voltage and current share a linear relation. Good correlation is found between the simulated and measured data, especially for the critical point at Vt1 and Vh. Due to certain approximations in the simulation parameter values, there are slight variations before the turn "ON" point and in the linear relation of the curve, which are within a tolerable range.

Figure  6.  (a) Microphotograph of the chip. (b) layout of the ELT with 16 cells. (c) single ELT cell
Figure  7.  Simulated and measured snapback curves of the ELT

Moreover, to confirm the validity of our model, the ELT chip is tested in HBM ESD measurement, and the ELT model is used to simulate the ESD characteristic. A transient simulation program is developed in the Cadence SPICE simulator, as shown in Fig. 8. For the HBM ESD test, the parasitic elements of the circuit impedance need to be considered. The impedance between the test pin and the ground is measured using an LCR tester, and an equivalent model is built using the standard R, L, and C elements. In this model Rr = 9.6 Ω, Rp = 105 Ω, L = 2.0 nH, and C = 32 pF, as shown in Fig. 8. VESD represents the HBM charging voltage, and CESD, RESD represents the human body capacitance and resistance, respectively.

Figure  8.  Equivalent circuit for HBM ESD test

Figure 9 shows the simulated and measured transient responses of currents passing through the drain terminal of the ELT subjected to three different HBM charging voltages ranging from 500 to 2000 V. Good agreement is found between the model and measured data. It is noted that the peak value of the drain current of the ELT is proportional to the HBM charging voltage, so that the maximum HBM ESD-pass voltage of the chip can be extrapolated from the ELT's second breakdown current (It2). For the ELT with an effective channel width of about 320 μm, It2 is about 2.40 A, which gives a maximum HBM ESD-pass voltage of about 3600 V. This is coincident with the test results.

Figure  9.  Simulated and measured transient responses of ID in HBM test

Figure 10 shows the simulated and measured transient responses of the drain voltages of the ELT. While the oscillatory movement of the drain voltage observed experimentally could not be described by the model, the simulation results reflect the main ESD response of the chip, and the oscillatory behavior seen in Fig. 10 is mainly due to the parasitic effects of the probe of the oscilloscope[10].

Figure  10.  Simulated and measured transient responses of VDS in HBM test

A novel and comprehensive model for an ELT as an ESD protection device has been presented. The model is composed of standard device components: the BSIM3 model for the ELT and the Mextram model for the parasitic BJT. The ELT is decomposed into edge and corner transistors by solving the electrostatic problem through the conformal mapping method, and these transistors are modeled with BSIM3 separately. High simulation speeds were obtained due to the sophisticated and fine-tuned algorithms in the BSIM and Mextram models, and simple procedure of parameter extraction makes the model easily to be implemented. To confirm the validity of the model, HBM ESD test is performed, and good agreement is found between simulations and measurements. Therefore, the ESD simulation of ELTs is effectively enhanced with the presented model.

Acknowledgement: The authors would like to thank Fei Liu for his valuable comments and discussion on the ELT model. The authors are also grateful to Xianli Zeng, Kai Hu and Deli Wang for their helpful support with the ESD measurements of this work.


[1]
Lee M S, Lee H C. Dummy gate-assisted n-MOSFET layout for a radiation-tolerant integrated circuit. IEEE Trans Nucl Sci, 2013, 60(4):3084 doi: 10.1109/TNS.2013.2268390
[2]
Nowlin R, McEndree S, Wilson A, et al. A new total-dose-induced parasitic effect in enclosed-geometry transistors. IEEE Trans Nucl Sci, 2005, 52(6):2495 doi: 10.1109/TNS.2005.860713
[3]
VSilvestri M, Gerardin S, Paccagnella A, et al. Degradation induced by X-ray irradiation and channel hot carrier stresses in 130-nm NMOSFETs with enclosed layout. IEEE Trans Nucl Sci, 2008, 55(6):3216 doi: 10.1109/TNS.2008.2006747
[4]
Ker M D, Wu C Y, Wu T S. Area-efficient layout design for CMOS output transistors. IEEE Trans Electron Devices, 1997, 44(4):635 doi: 10.1109/16.563369
[5]
Champion C L, Rue G S L. Accurate SPICE models for CMOS analog radiation-hardness-by-design. IEEE Trans Nucl Sci, 2005, 52(6):2542 doi: 10.1109/TNS.2005.860717
[6]
Chen L, Gingrich D M. Study of n-channel MOSFETs with an enclosed-gate layout in a 0.18μm CMOS technology. IEEE Trans Nucl Sci, 2005, 52(4):861 doi: 10.1109/TNS.2005.852652
[7]
Jiao C, Yu Z. A robust novel technique for SPICE simulation of ESD snapback characteristic. Proceedings of the 8th International Conference on Solid-State Integrated Circuit Technology, 2006:1367 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4098411&openedRefinements%3D*%26filter%3DAND%28AND%28NOT%284283010803%29%29%2CAND%28NOT%284283010803%29%29%29%26pageNumber%3D7%26rowsPerPage%3D100%26queryText%3D%28esd%29
[8]
Vassilev V, Lorenzini M, Groeseneken G. MOSFET ESD breakdown modeling and parameter extraction in advanced CMOS technologies. IEEE Trans Electron Devices, 2006, 53(9):2108 doi: 10.1109/TED.2006.880367
[9]
Li J, Joshi S, Rosenbaum E. A verilog-a compact model for ESD protection NMOSTs. Proceedings of Custom Integrated Circuits Conference, 2003:253
[10]
Gao X, Liou J, Bernier J, et al. Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2002, 21(12):1497 doi: 10.1109/TCAD.2002.804379
[11]
Zhou Y Z, Connerney D, Carroll R, et al. Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models. Proceedings of the 6th International Symposium on Quality Electronic Design, San Jose, 2005:476 doi: 10.1109/ISQED.2005.81
[12]
Giraldo A, Paccagnella A, Minzoni A. Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout. Solid-State Electron, 2000, 44:981 doi: 10.1016/S0038-1101(00)00010-1
[13]
Liu W D, Jin X D, Chen J, et al. BSIM3v3. 2. 2 MOSFET model users' manual. Department of Electrical Engineering and Computer Sciences University of California, Berkeley, 1999
[14]
Van der Toorn R, Paasschens J C J, Kloosterman W J. The Mextram bipolar transistor model, level 504. 10. 1. Users' Manual, Koninklijke Philips Electronics N. V. , Amsterdam, Netherlands, 2000/2004
[15]
Chen S H, Ker M D, Hung H P. Active ESD protection design for interface circuits between separated power domains against cross-power-domain ESD stresses. IEEE Trans Device Mater Reliab, 2008, 8(3):549 doi: 10.1109/TDMR.2008.2002492
[16]
Meng K H, Rosenbaum E. Verification of snapback model by transient I-V measurement for circuit simulation of ESD response. IEEE Trans Device Mater Reliab, 2013, 13(2):371 doi: 10.1109/TDMR.2013.2258672
[17]
Amerasekera A, Ramaswamy S, Chang M, et al. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations. Proceedings of the 34th Annual IEEE International Reliability Physics Symposium, Dallas, 1996:318
Fig. 1.  Layout diagram of the ELT

Fig. 2.  Electric field in the channel of ELT

Fig. 3.  Approximation of T1 and T2

Fig. 4.  A schematic cross-sectional view of ELT

Fig. 5.  The circuit model for ESD simulation of the ELT

Fig. 6.  (a) Microphotograph of the chip. (b) layout of the ELT with 16 cells. (c) single ELT cell

Fig. 7.  Simulated and measured snapback curves of the ELT

Fig. 8.  Equivalent circuit for HBM ESD test

Fig. 9.  Simulated and measured transient responses of ID in HBM test

Fig. 10.  Simulated and measured transient responses of VDS in HBM test

Table 1.   The effective channel width and length of T1, T2 and T3

Table 2.   Critical parameters of the snapback curve

Table 3.   Parameters extracted from measurements

[1]
Lee M S, Lee H C. Dummy gate-assisted n-MOSFET layout for a radiation-tolerant integrated circuit. IEEE Trans Nucl Sci, 2013, 60(4):3084 doi: 10.1109/TNS.2013.2268390
[2]
Nowlin R, McEndree S, Wilson A, et al. A new total-dose-induced parasitic effect in enclosed-geometry transistors. IEEE Trans Nucl Sci, 2005, 52(6):2495 doi: 10.1109/TNS.2005.860713
[3]
VSilvestri M, Gerardin S, Paccagnella A, et al. Degradation induced by X-ray irradiation and channel hot carrier stresses in 130-nm NMOSFETs with enclosed layout. IEEE Trans Nucl Sci, 2008, 55(6):3216 doi: 10.1109/TNS.2008.2006747
[4]
Ker M D, Wu C Y, Wu T S. Area-efficient layout design for CMOS output transistors. IEEE Trans Electron Devices, 1997, 44(4):635 doi: 10.1109/16.563369
[5]
Champion C L, Rue G S L. Accurate SPICE models for CMOS analog radiation-hardness-by-design. IEEE Trans Nucl Sci, 2005, 52(6):2542 doi: 10.1109/TNS.2005.860717
[6]
Chen L, Gingrich D M. Study of n-channel MOSFETs with an enclosed-gate layout in a 0.18μm CMOS technology. IEEE Trans Nucl Sci, 2005, 52(4):861 doi: 10.1109/TNS.2005.852652
[7]
Jiao C, Yu Z. A robust novel technique for SPICE simulation of ESD snapback characteristic. Proceedings of the 8th International Conference on Solid-State Integrated Circuit Technology, 2006:1367 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4098411&openedRefinements%3D*%26filter%3DAND%28AND%28NOT%284283010803%29%29%2CAND%28NOT%284283010803%29%29%29%26pageNumber%3D7%26rowsPerPage%3D100%26queryText%3D%28esd%29
[8]
Vassilev V, Lorenzini M, Groeseneken G. MOSFET ESD breakdown modeling and parameter extraction in advanced CMOS technologies. IEEE Trans Electron Devices, 2006, 53(9):2108 doi: 10.1109/TED.2006.880367
[9]
Li J, Joshi S, Rosenbaum E. A verilog-a compact model for ESD protection NMOSTs. Proceedings of Custom Integrated Circuits Conference, 2003:253
[10]
Gao X, Liou J, Bernier J, et al. Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2002, 21(12):1497 doi: 10.1109/TCAD.2002.804379
[11]
Zhou Y Z, Connerney D, Carroll R, et al. Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models. Proceedings of the 6th International Symposium on Quality Electronic Design, San Jose, 2005:476 doi: 10.1109/ISQED.2005.81
[12]
Giraldo A, Paccagnella A, Minzoni A. Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout. Solid-State Electron, 2000, 44:981 doi: 10.1016/S0038-1101(00)00010-1
[13]
Liu W D, Jin X D, Chen J, et al. BSIM3v3. 2. 2 MOSFET model users' manual. Department of Electrical Engineering and Computer Sciences University of California, Berkeley, 1999
[14]
Van der Toorn R, Paasschens J C J, Kloosterman W J. The Mextram bipolar transistor model, level 504. 10. 1. Users' Manual, Koninklijke Philips Electronics N. V. , Amsterdam, Netherlands, 2000/2004
[15]
Chen S H, Ker M D, Hung H P. Active ESD protection design for interface circuits between separated power domains against cross-power-domain ESD stresses. IEEE Trans Device Mater Reliab, 2008, 8(3):549 doi: 10.1109/TDMR.2008.2002492
[16]
Meng K H, Rosenbaum E. Verification of snapback model by transient I-V measurement for circuit simulation of ESD response. IEEE Trans Device Mater Reliab, 2013, 13(2):371 doi: 10.1109/TDMR.2013.2258672
[17]
Amerasekera A, Ramaswamy S, Chang M, et al. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations. Proceedings of the 34th Annual IEEE International Reliability Physics Symposium, Dallas, 1996:318
1

Analytical modeling and simulation of germanium single gate silicon on insulator TFET

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    Jia Zhang, Haigang Yang, Jiabin Sun, Le Yu, Yuanfeng Wei. Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method[J]. Journal of Semiconductors, 2014, 35(8): 085001. doi: 10.1088/1674-4926/35/8/085001
    J Zhang, H G Yang, J B Sun, L Yu, Y F Wei. Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method[J]. J. Semicond., 2014, 35(8): 085001. doi: 10.1088/1674-4926/35/8/085001.
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    History

    Received: 14 January 2014 Revised: 27 January 2014 Online: Published: 01 August 2014

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      Jia Zhang, Haigang Yang, Jiabin Sun, Le Yu, Yuanfeng Wei. Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method[J]. Journal of Semiconductors, 2014, 35(8): 085001. doi: 10.1088/1674-4926/35/8/085001 ****J Zhang, H G Yang, J B Sun, L Yu, Y F Wei. Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method[J]. J. Semicond., 2014, 35(8): 085001. doi: 10.1088/1674-4926/35/8/085001.
      Citation:
      Jia Zhang, Haigang Yang, Jiabin Sun, Le Yu, Yuanfeng Wei. Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method[J]. Journal of Semiconductors, 2014, 35(8): 085001. doi: 10.1088/1674-4926/35/8/085001 ****
      J Zhang, H G Yang, J B Sun, L Yu, Y F Wei. Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method[J]. J. Semicond., 2014, 35(8): 085001. doi: 10.1088/1674-4926/35/8/085001.

      Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method

      DOI: 10.1088/1674-4926/35/8/085001
      Funds:

      the National Natural Science Foundation of China 61271149

      Project supported by the National Natural Science Foundation of China (No. 61271149) and the CAS/SAFEA International Partnership Program for Creative Research Teams

      the CAS/SAFEA International Partnership Program for Creative Research Teams 

      More Information
      • Corresponding author: Yang Haigang, Email:yanghg@mail.ie.ac.cn
      • Received Date: 2014-01-14
      • Revised Date: 2014-01-27
      • Published Date: 2014-08-01

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