Fig. 1.
(a) Structure schematic diagram and (b) optical microscope graph of graphene field effect transistor, ${W}{\text{/}}{L}{\text{ = 10 }}\mu {\text{m/10 }}\mu {\text{m}}$ .
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| Citation: |
Jie Yang, Kunpeng Jia, Yajuan Su, Yang Chen, Chao Zhao. Hysteresis analysis of graphene transistor under repeated test and gate voltage stress[J]. Journal of Semiconductors, 2014, 35(9): 094003. doi: 10.1088/1674-4926/35/9/094003
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J Yang, K P Jia, Y J Su, Y Chen, C Zhao. Hysteresis analysis of graphene transistor under repeated test and gate voltage stress[J]. J. Semicond., 2014, 35(9): 094003. doi: 10.1088/1674-4926/35/9/094003.
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Hysteresis analysis of graphene transistor under repeated test and gate voltage stress
DOI: 10.1088/1674-4926/35/9/094003
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Abstract
The current transport characteristic is studied systematically based on a back-gate graphene field effect transistor, under repeated test and gate voltage stress. The interface trapped charges caused by the gate voltage sweep process screens the gate electric field, and results in the neutral point voltage shift between the forth and back sweep direction. In the repeated test process, the neutral point voltage keeps increasing with test times in both forth and back sweeps, which indicates the existence of interface trapped electrons residual and accumulation. In gate voltage stress experiment, the relative neutral point voltage significantly decreases with the reducing of stress voltage, especially in -40 V, which illustrates the driven-out phenomenon of trapped electrons under negative voltage stress.-
Keywords:
- graphene FET,
- interface trap,
- electrical measurement,
- repeated test,
- stress
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References
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