1. Introduction

SiC material has potential applications in high power microwave devices and RF circuitry because of its large bandgap, high saturated electron velocity, high breakdown field and large thermal conductivity^{[1, 2, 3]}. The development of a microwave device such as MESFET, fabricated from 4H polytype of SiC, is of great interest because of its simple construction and wide use in circuit applications namely power amplifiers, mixers and oscillators^[4]. The intrinsic material properties of 4H-SiC can be taken as an advantage to construct microwave devices (MESFETs) if the 4H-SiC substrate formed is semi-insulating (SI)^[5]. SI substrates are needed to minimize parasitic device capacitances, which in turn reduce the RF losses so that the devices can have enhanced performance at high frequencies. One traditional way of achieving this SI property in 4H-SiC is by introducing transition metals such as vanadium (V). The resulting material is found to be SI at room temperature and retains its nature even at elevated temperatures^[6]. However, later reports^{[5, 7]} suggest that V may not be the favorable deep-level trap for SI 4H-SiC. An unacceptably high concentration of V ($\sim$10$^{17}$ cm$^{-3})$ in the substrate is used to compensate for the residual shallow acceptors ($\sim$10$^{16}$ cm$^{-3})$, which degrade the crystalline and electronic quality of the material by introducing growth defects^{[8, 9]}. Alternatively, compensation of SiC substrates without intentional V doping is explored^{[10, 11]}. Unlike the earlier compensation technique, the intrinsic defects that have energy levels deep in the bandgap (with concentration in the mid 10$^{15}$ cm$^{-3})$ are used to compensate for the shallow levels, making the substrate semi-insulating^[8]. Impressive DC and RF performances of 4H-SiC MESFET formed on 4H-SiC HPSI substrate are demonstrated^{[12, 13]}. Other ways of forming a SI SiC layer in n-type 4H-SiC wafers such as by controlled electron irradiation^[14] and by defect competition epitaxy^[15] }$ are also reported. The recent developments in the formation of HPSI substrates make SiC MESFET even more attractive for monolithic microwave integrated circuit (MMIC) technology but the device performance is still affected by the trapping centers in the substrate and at the surface of the device^[16]. On the other hand, suppression of trapping effects in SiC MESFETs is investigated by separating the conducting channel from the SI substrate by sandwiching a low-doped buffer layer^[16]. However, it has been reported that the substrate trapping effects still persist even with buffer layers^[16]. Hence it is worthwhile investigating the trapping effects in 4H-SiC MESFETs fabricated directly on HPSI substrates. In addition to the trapping near to the substrate, trapping at the channel-passivation layer interface also affects the microwave performance of the device^[17]. The trapping of charge carriers by the surface states present between source/drain, and the gate modulates the channel current and degrades the DC and RF performance of the device. In 4H-SiC MESFETs, trapping effects introduce current collapse in the $I$-$V$ characteristics, frequency dispersion of transconductance and output resistance, drain and gate lag that severely limits the microwave power output^{[16, 18, 19]}. A physics-based analytical model of 4H-SiC MESFETs including the major trapping effects is crucial for an exact evaluation of device performance at low frequency and microwave applications. Furthermore, it is useful for subsequent optimization once the model is validated.

Tsap^[20] presented an analytical $I$-$V$ model of SiC MESFET including the field-dependent mobility and computed the cut-off frequency of the MESFET. Murray and Roenkar^[21] reported a physics-based analytical model of SiC MESFETs based on the two-dimensional analysis of the charge distribution under the gate including the field dependent mobility and velocity saturation effects. In Reference ^[22], Mukherjee \textit{et al. }presented an analytical model of SiC MESFET with trapping and thermal effects but the exact nature and origin of the traps are not discussed. Zhu et al.^[23] reported a three-region model for short channel SiC MESFETs. Chattopadhyay et al.^[24] proposed an analytical model of an ion-implanted 4H-SiC MESFET by considering different ion-implantation parameters. A comprehensive frequency dispersion model of 4H-SiC MESFET was proposed by Lu et al.^[25]. The small-signal parameters of the MESFET are computed from the modeled DC $I$-$V$ characteristics. It is observed that the aforementioned models do not consider the effects of both substrate and surface trapping and the actual nature of the HPSI substrate in modeling the DC characteristics of the 4H-SiC MESFET.

The main objective of this paper is to provide an improved analytical model with the recently reported nature and origin of the deep-level traps^{[10, 11]} in the substrate bulk of 4H-SiC MESFET along with the surface trapping effect so that the modeled $I$-$V$ characteristics can show a closer resemblance to the real devices. The contribution of each trap is validated through two-dimensional simulations (SILVACO$^{\circledR }$-TCAD)^[26]. The surface trapping effect is included through the modulation of parasitic series resistance obtained at the gate-source spacing, as well as the gate-drain spacing of MESFET. For the completeness, self-heating effects are also considered. At present, our model is simulated for DC characteristics. In addition, the transconductance and the drain conductance are determined for the same device. Some of the assumptions considered in the model are also validated by performing two-dimensional device simulations^[26] (SILVACO$^{\circledR }$-TCAD) on the same device.

2. Theoretical model

The schematic structure of 4H-SiC MESFET is shown in Figure 1. A uniform doping concentration $(N_{\rm d})$ is assumed throughout the channel of the device approximating the ion-implantation profile considered in experimental results^[12]. Here $W$, $L$, $L_{\rm sg}$, $L_{\rm gd}$ and $a$ are the gate width, gate length, source-gate spacing, gate-drain spacing and active layer thickness respectively. The device is assumed to be passivated on the ungated regions between source-gate and gate-drain of the device with an insulator, typically silicon dioxide (SiO$_{2})$. The substrate considered here is an HPSI substrate where the compensation is by deep levels created by intrinsic defects formed during the growth^[10]. In Figure 1, the depletion region under the gate is due to the conventional metal-semiconductor junction. Whereas, the depletion region at the channel-substrate interface is due to the capture of energetic channel electrons by the uncompensated deep levels in the substrate, increasing the effective negative charge leading to a positive depletion region in the channel side of the channel-substrate interface (as shown in Figure 1). Similarly, interface states present at the ungated portions between the source and gate as well as between the gate and drain of the 4H-SiC MESFET create a surface depletion region, which is also modulated by the gate and drain voltages leading to voltage dependent series resistance. The inset of Figure 1 demonstrates the surface trapping effects at the channel-dielectric interface. The result of both these effects is the reduction in the drain current under static conditions. The other effects include frequency dispersion of transconductance and output resistance, drain and gate lag that severely limits the microwave power output; however, these effects will be visible when a transient signal is applied to the terminals of the device. In the following sub-sections, modeling of the substrate and surface trapping effects are discussed and later a complete DC $I$-$V$ model of 4H-SiC MESFET is presented.

2.1 Modeling of substrate trapping effects

For analytical modeling of the substrate trapping effects in 4H-SiC MESFETs, it is essential to identify the dominant defects (traps) that are responsible for substrate compensation and trapping. A multitude of defects in 4H-SiC covering the whole range of energies in the bandgap are reported^[27]. However, the intrinsic traps with energy levels ranging from 0.5 to 1.5 eV from the conduction band are found to be responsible for the substrate compensation in 4H-SiC^[10]. Out of many intrinsic levels, three major deep-level traps (Z$_{1/2}$, RD$_{1/2}$, EH$_{6/7})$ found in the 4H-SiC substrate are believed to compensate shallow donors and acceptors from residual shallow impurities^[10]. The origin of these traps is mainly due to the carbon vacancy, which was revealed by recent electron paramagnetic resonance studies (EPR)^[28]. The observation in Reference ^[10] indicates that these traps are found in the upper half of the bandgap and are acceptor-like. The recent report by Son et al.^[29] indicates that Z$_{1/2}$ is a double acceptor and EH$_{6/7}$ is a single donor trap.

Table 1 summarizes the typical concentrations and captured cross sections of these three dominant traps in the HPSI substrate used in our analysis. The trap parameters for Z$_{1/2}$ and RD$_{1/2}$ are taken from Reference ^[10], whereas the trap parameters of EH$_{6/7}$ in the HPSI 4H-SiC substrate are not yet reported. It is observed that the Z$_{1/2}$ center is always present along with the EH$_{6/7}$ trap, suggesting that both may be due to C-vacancy related defects in 4H-SiC^[29]. Moreover, the concentrations of both traps were found to be very close to each other (with a slightly higher Z$_{1/2}$ concentration, but of the same order) irrespective of the growth and annealing conditions^{[29, 30]}. Hence, it is reasonable to consider the EH$_{6/7}$ concentration of the order of 10$^{15}$ cm$^{-3}$ in HPSI 4H-SiC substrates. We have found that the Fermi level position in the substrate is relatively insensitive to the variation in EH$_{6/7}$ concentration (changes only by few meV for a decade of change).

In the subsequent analysis, we have considered the above mentioned three dominant deep-level traps with energies and concentrations specified in Table 1. Many experimental results revealed that nitrogen ($E_{\rm C}$ - 0.090 eV) and Boron ($E_{\rm V}$ $+$ 0.22 eV) are the dominant shallow donors and acceptors with concentrations in the mid 10$^{15}$ cm$^{-3}$ in HPSI substrates and that nitrogen concentration exceeds the boron concentration^{[5, 10, 15]}. In the analysis, we have assumed the net donor concentration as 2 $\times$ 10$^{15}$ cm$^{-3}$ similar to Mitchel's report^[10].

2.1.1   At thermal equilibrium

To verify the compensation mechanism in the 4H-SiC HPSI substrate, we have determined the position of the Fermi level in the substrate at thermal equilibrium by applying a charge neutrality condition to the multiple-trap model. Considering the charge states of acceptor and donor-like deep-level traps, incomplete ionization of shallow dopants, the charge neutrality condition can be written as:

$n_0 + N_{\rm T1}^{-} +N_{\rm SA}^{-} +N_{\rm T2}^{-} =p_0 + N_{\rm SD}^{+} + N_{\rm T3}^{+},$

(1)

where $n_0$ is the free electron concentration, $p_0$ is the free hole concentration, $N_{\rm SD}^+$ is the ionized shallow donor concentration, $N_{\rm SA}^-$ is the ionized shallow acceptor concentration, and $N_{\rm T1}^{-}$, $N_{\rm T2}^{-}$, and $N_{\rm T3}^{+}$ are the densities of ionized Z$_{1/2}$ (acceptor), RD$_{1/2}$ (acceptor) and EH$_{6/7}$ (donor) trap concentrations respectively.

In HPSI 4H-SiC, the Fermi level is in the forbidden bandgap and is several $kT$ away from the band edges and hence Maxwellian statistics are applicable.

The free electron/hole concentrations are given by $n_0 =gN_{\rm c} {\rm e}^{\frac{-\left( {E_{\rm c} -E_{\rm f} } \right)}{kT}}$ and $p_0 =\left( {\frac{N_{\rm v} }{g}} \right){\rm e}^{\frac{-\left( {E_{\rm f} -E_{\rm v} } \right)}{kT}}$ respectively, where $N_{\rm c}$ and $N_{\rm v}$ are the effective density of states in the conduction and valence bands of 4H-SiC^[10] and the degeneracy factor ($g$) of donors and donor-like traps is taken as being two, whereas for acceptor and acceptor-like traps, it is considered as being four^[31]. The ionized trap densities $N_{\rm T1}^{-}$, $N_{\rm T2}^{-}$ and $N_{\rm T3}^{+}$ are given by

$N_{\rm T1(eql)}^- =N_{Z_{1/2} } f_{\rm T(eql)} =N_{Z_{1/2}} \left( {1+\frac{1}{g}{\rm e}^{\frac{ {E_{Z_{1/2} } -E_{\rm f} } }{kT}}} \right)^{-1},$

(2)

$N_{\rm T2(eql)}^- =N_{\rm RD_{1/2} } f_{\rm T(eql)} =N_{\rm RD_{1/2} } \left( {1+\frac{1}{g}{\rm e}^{\frac{{E_{\rm RD_{1/2} } -E_{\rm f} }}{kT}}} \right)^{-1},$

(3)

$$\begin{split} \label{eq4} N_{\rm T3({eql})}^+ {}& =N_{\rm EH_{6/7} } \left( {1-f_{\rm T(eql)} } \right) \\[2mm]& =N_{\rm EH_{6/7} } \left( {1+g{\rm e}^{\frac{{E_{\rm f} -E_{\rm EH_{6/7} } }}{kT}}} \right)^{-1}, \end{split}$$

(4)

where $f_{\rm T(eql)}$ is the probability of a trap level being occupied by an electron in the substrate under thermal equilibrium. $N_{\rm Z_{1/2} }$, $N_{\rm RD_{1/2}}$ and $N_{\rm EH_{6/7} }$ are the densities of Z$_{1/2}$, RD$_{1/2}$ and EH$_{6/7}$ traps with the energy levels represented by $E_{\rm Z_{1/2} }$, $E_{\rm RD_{1/2} }$ and $E_{\rm EH_{6/7}}$ respectively. $E_{\rm f}$ is the Fermi energy level in the substrate bulk at thermal equilibrium.

The position of Fermi level can now be determined graphically by plotting each term in Equation (1) as a function of energy ($E_{\rm f})$. The above mentioned graphical method is demonstrated in Figure 2 with the reported SIMS results for shallow dopant concentrations^{[5, 10, 15]} and the deep level trap parameters in Table 1. The Fermi level is found to be located at 0.845 eV from the conduction band in the HPSI substrate at thermal equilibrium. The electrons from the shallow donor level can compensate for the lowest acceptor level (near to the valence band), the boron level in this case, first and then the next higher levels (EH$_{6/7}$, RD$_{1/2}$ and Z$_{1/2})$ will be compensated for. Finally, the Fermi level is pinned close to the highest partially compensated deep level, Z$_{1/2}$ in this case. The resultant material is found to be slightly n-type with a carrier concentration of about 10$^6$ cm$^{-3}$. Using the reported electron mobility values of 1-100 cm$^2$/(V$\cdot$s) for HPSI 4H-SiC^[32], the room temperature resistivity is found to be $>$ 10$^{11}$ $\Omega \cdot$cm. The resistivity obtained from the above calculations is comparable to the resistivity of commercially available HPSI 4H-SiC wafers^{[5, 14, 15]}, which further confirms that multiple deep-level traps with concentrations of more than 10$^{15}$ cm$^{-3}$ compensate for the HPSI 4H-SiC substrate.

2.1.2   At non-thermal equilibrium

It is evident from the above calculations and the reported experimental results that Z$_{1/2}$, RD$_{1/2}$ and EH$_{6/7}$ traps may be the dominant traps responsible for substrate compensation in 4H-SiC. For modeling and analyzing the substrate trapping effects, it may be helpful in identifying the roles of individual traps towards the overall trapping. To understand this, we have performed two-dimensional device simulations, with commercial simulators^[26], of 4H-SiC MESFET having a gate length of 0.5 $\mu$m formed directly on the HPSI substrate as in Figure 1. The substrate is modeled initially as trap-free with only the background dopant concentrations and later deep-level traps are introduced with the trap parameters in Table 1. The simulated electron concentration profiles in different regions of the MESFET operating at 300 K are shown in Figure 3. The bias voltages used are $V_{\rm ds}$ $=$ 20 V and $V_{\rm gs}$ $=$ $-6$ V. Figures 3(a) and 3(b) present the simulated electron concentration in the MESFET on a substrate defined to be trap-free with only the background doping concentration and with a substrate that contains the three dominant traps. As evident from the figures, the presence of all the traps in the substrate inhibits the electron movement from the channel to the bulk of the substrate. Rather, they get trapped by these traps and hence show a reduction in the electron concentration in the substrate. At high gate and drain voltages, the conducting electrons are pushed away from the channel by the high vertical electric field in the channel and enter into the substrate. Since the substrate in Figure 3(a) is defined as trap-free, the injected electrons stay close to the channel-substrate interface without being trapped, whereas in Figure 3(b), the substrate includes the dominant deep level traps and hence a reduction in the injected electron concentration is observed. These simulations clearly show that trapping effects are present in 4H-SiC MESFETs fabricated on HPSI substrates.

To further clarify the same, Figure 4 shows the simulated vertical electric field in the substrate along the cutline $AA^{1}$ of the MESFET structure shown in Figures 3(a) and 3(b). It is noted that the vertical component of the electric field increases for the substrate with traps due to the possible substrate trapping.

Figures 5(a) and 5(b) show the simulated electron density profiles of the MESFET without considering EH$_{6/7}$ and Z$_{1/2}$ traps in the SiC substrate. By comparing those profiles with Figure 3(b), it can be observed that when the EH$_{6/7}$ trap is absent, there is an almost negligible change in the electron concentration profile as compared to the profile when all the traps are present in the substrate. On the other hand, major changes in the electron concentration profiles were noticed when Z$_{1/2}$ was not considered in the simulations. Similar behavior was observed for the RD$_{1/2}$ trap (not shown). Hence it may be reasonable to neglect the trapping effects of EH$_{6/7}$ to the overall substrate trapping, even though it takes part in the substrate compensation. The same can be concluded by looking into Figure 2. The calculated Fermi level at thermal equilibrium in the HPSI 4H-SiC substrate was earlier found to lie at 0.845 eV below the conduction band and hence this level is many $kT$ above the EH$_{6/7}$ level (1.65 eV below the conduction band), as shown in Figure 2. Under normal conditions, this level is almost filled with electrons and trapping by this level may be negligible. Hence the trapping model is developed considering the substrate trapping by Z$_{1/2}$ and RD$_{1/2}$ traps in the HPSI substrate.

Under non-equilibrium conditions, the Fermi function in the substrate is given by^[33]

$f_{\rm T(non-eql)} ={\frac{e_{\rm p} +nC_{\rm n} }{e_{\rm p} +e_{\rm n} +nC_{\rm n} +pC_{\rm p} }} ,$

(5)

where $C_{\rm p} =\sigma _{\rm p} v_{\rm pth}$ and $C_{\rm n} =\sigma _{\rm n} v_{\rm nth}$ are the hole and electron capture coefficients; $\sigma _{\rm p}$ and $\sigma _{\rm n}$ are the capture cross sections of holes and electrons; $n$ and $p$ are the free electron and hole concentrations at non-equilibrium conditions; $v_{\rm pth}$ and $v_{\rm nth}$ are the thermal velocities of holes and electrons; and $e_{\rm p}$ and $e_{\rm n}$ are the emission rates of holes and electrons from the respective traps.

The concentration of negative charge due to electron trapping by a defect level in the substrate side can be given as follows:

$N_{\rm T(non-eql)}^- =N_{\rm T} \left( {f_{\rm T(non-eql)} } \right).$

(6)

$f_{\rm T(non-eql)}$ given in Equation (5) can be simplified by considering the non-equilibrium carrier statistics in the 4H-SiC substrate. In unipolar devices like MESFETs, the injected electron density from the channel is orders of magnitude higher than the equilibrium electron and hole concentrations in the HPSI substrate. Moreover, Z$_{1/2}$ and RD$_{1/2}$ traps are in the upper half of the bandgap and hence $e_{\rm p}$ $\ll$ $<$ $e_{\rm n}$. Under these conditions, $f_{\rm T(non-eql)}$ for traps Z$_{1/2}$ and RD$_{1/2}$ can be computed and is nearly equal to 1. This is expected because of the large number of electrons injected into the substrate and the lower concentration of vacant traps.

The net negative charge acquired by the substrate due to trapping by a single defect level is,

$N_{\rm sub} =N_{\rm T(non-eql)}^- -N_{\rm T\left( {eql} \right)}^-.$

(7)

Extending this equation to multiple deep-level traps (Z$_{1/2}$ and RD$_{1/2})$ by neglecting the inter-trap charge transfer, Equation (7) can be written as

$N_{\rm sub} =\sum\limits_{i=1}^2 {N_{T_i } f_{T_i{\rm (non-eql)}} } -\sum\limits_{i=1}^2 {N_{T_i }} f_{T_i{\rm (eql)}}.$

(8)

2.2 Modeling of surface trapping effects

It has been generally agreed that the surface potential of a free-SiC surface is comparable to that of an un-biased Schottky metal gate due to pinning the Fermi level at the surface by high density surface states^[34]. Surface passivation with native SiO$_{2}$ is proposed to reduce the interface state density, but a two orders of magnitude higher interface state density at the SiC/SiO$_{2}$ interface compared to the Si/SiO$_{2}$ interface is reported^[35]. The high density of electrically active surface/interface states at SiC/SiO$_{2}$ is responsible for the undesirable surface trapping effects in MESFETs^{[23, 36]}, mobility degradation in MOSFETs and the reduction of current gain in BJTs. Particularly in 4H-SiC MESFET, either with an unpassivated or passivated surface, the surface trapping induced depletion layer extends into the channel between the source-gate and gate-drain (inset of Figure 1) modulating the source and drain parasitic resistances ($R_{\rm S}$ and $R_{\rm D})$. The surface trapping effects may cause a substantial reduction in the channel current and the transconductance, which eventually degrade the DC and microwave performance of these devices. Various techniques for minimizing the surface trapping problems in 4H-SiC MESFETs have been reported in the literature such as surface treatment by dielectric passivation^{[17, 34]}, insertion of MOS gate controlled spacer layers between the surface and the channel, recessed gate structures^[37] }$ and by gate-connected field plates^[38]. Among those techniques, improved surface treatment by dielectric passivation may be promising for monolithic integration and the surface trapping effects are even more noticeable in planar devices^[39]. In order to design optimized circuits using SiC MESFETs, a complete analysis of dc characteristics that includes the surface trapping effects is extremely valuable.

Experimental results^[40] on the 4H-SiC/SiO$_{2}$ interface shows a mean interface trap density of the order of 10$^{12}$~eV$^{-1}$cm$^{-2}$. To include the effect of interface states, the energy and the temperature dependence of the trap density of interface states ($D_{\rm it}( {E_{\rm T} , T}))$ is considered that facilitates the incorporation of different surface passivation effects on the DC characteristics of the MESFET in the model. The typical extracted $D_{\rm it}$ profiles of the 4H-SiC/SiO$_{2}$ interface has shown a nearly flat profile near the middle of the bandgap and an exponential increase near the band edges^[41]. Thus the energy and temperature dependent $D_{\rm it}$ distribution can be modeled as^{[40, 41]}

$D_{\rm it} (E_{\rm T}, T)=D_{\rm it}^{\rm mid} +D_{\rm it}^{\rm CBedge} {\rm e}^{-\frac{(E_{\rm c} -E_{\rm T})} {\sigma _1}}+ D_{\rm it}^{\rm VBedge} {\rm e}^{{-\frac{\left( {E_{\rm T} -E_{\rm v} } \right)}{\sigma _2 }}},$

(9)

where $E_{\rm T}$ is the surface trap level in the energy bandgap, $E_{\rm C}$ is the conduction band minimum, $E_{\rm V}$ is the valence band maximum, $D_{\rm it}^{\rm mid}$ is the midgap density of states, $D_{\rm it}^{\rm CBedge}$$(D_{\rm it}^{\rm VBedge})$ and $\sigma _1$ $(\sigma _2 )$ are the interface state density and the characteristic band tail energy at the conduction (valence) band edges respectively.

In order to use the energy dependent $D_{\rm it}$ profile for further analysis, the unknown parameters in Equation (9) are extracted from the reported $D_{\rm it}$ distribution for the 4H-SiC/SiO$_{2}$ interface^[42]. The best fit is observed for the extracted values of unknown parameters with $D_{\rm it}^{\rm mid}$ $=$ 2 $\times$ 10$^{11}$ eV$^{-1}$cm$^{-2}$, $D_{\rm it}^{\rm CBedge}$ $=$ 6 $\times$ 10$^{13}$ eV$^{-1}$cm$^{-2}$, $D_{\rm it}^{\rm VBedge}$ $=$ 1 $\times$ 10$^{12}$ eV$^{-1}$cm$^{-2}$, $\sigma _1$ $=$ 0.25 eV and $\sigma _2$ $=$ 0.26 eV.

When the MESFET is unbiased, the acceptor interface states below $E_{\rm f}$ and above the charge neutral level (CNL), $E_{\rm CNL}$, are negatively charged. Recent quasi-particle calculations^[43] performed on SiC polytypes reveals that in 4H-SiC, the CNL lies 1.4 eV below the conduction band minimum. Assuming the CNL is at 1.4 eV below the conduction band and $E_{\rm f}$ above $E_{\rm CNL}$, the interface trapped negative charge density is evaluated as

$Q_{\rm it} =-q\int\nolimits_{E_{\rm CNL} }^{E_{\rm f} } {\left[{D_{\rm it}( {E_{\rm T} })f({E_{\rm T}})} \right]} {\rm d}E_{\rm T},$

(10)

where $f({E_{\rm T}})$ is the probability of occupying the acceptor trap at $E_{\rm T}$ by an electron.

By applying the charge balance equation at the interface of 4H-SiC/SiO$_{2}$ and converting the density of state energies into the surface potential, the width of the surface depletion region can be found using,

$qN_{\rm d} W_{\rm S} =\left| {-q\int\nolimits_{E_{\rm CNL} }^{E_{\rm f}} {\left[{D_{\rm it}({E_{\rm T}})f({E_{\rm T}})} \right]} {\rm d}E_{\rm T} } \right|,$

(11)

$W_{\rm S} =\sqrt {\frac{2\varepsilon _{\rm SiC} V_{\rm sbi} }{qN_{\rm d} }},$

(12)

$E_{\rm f}\, -E_{\rm CNL}=E_{\rm g}\, -\, \left[{\left( {E_{\rm CNL} -E_{\rm V}} \right)+qV_{\rm sbi} +\left( {E_{\rm C} -E_{\rm f, bulk} } \right)} \right],$

(13)

where $W_{\rm S}$ is the width of the surface depletion region at the source end of the unbiased MESFET, $V_{\rm sbi}$ is the surface built-in potential, $\varepsilon _{\rm SiC}$ is the permittivity of 4H-SiC, $q$ is the electron charge, $E_{\rm g}$ is the bandgap of 4H-SiC, and $E_{\rm C} -E_{\rm f, bulk}$ is the relative position of the Fermi level in the channel region of 4H-SiC MESFET that can be determined from the channel doping density.

2.2.1   Modeling of voltage-dependent source-gate & gate-drain series resistances

It has been mentioned earlier that surface trapping by the acceptor interface states at the SiC/SiO$_{2}$ interface leads to the formation of a surface depletion region between gate-source and gate-drain opening of the SiC MESFET. We assume that the surface effects beneath the Schottky gate are included in the determination of the Schottky barrier height ($\phi _{\rm b})$. When the MESFET is biased, the depletion layers between gate-source and gate-drain are modulated by the gate bias resulting in additional variable series resistances that are connected to the intrinsic FET. These series resistances are larger compared to GaAs MESFETs with similar geometry and doping concentration because of the low value of electron mobility and high interface state densities in 4H-SiC^{[3, 17]}. Moreover, the extracted source and drain series resistances from the measured $S$-parameters are strongly dependent on the surface passivation conditions^[17]. Hence, an analytical model for the voltage dependent series resistances of a 4H-SiC MESFET considering the different surface passivation effects is valuable for accurate device characterization at DC and microwave frequencies.

The source series resistance ($R_{\rm S})$ between source and gate opening of the MESFET may be given as

$R_{\rm S} \left( {V_{\rm G} } \right)=R_{\rm C} +R_{\rm sg}({V_{\rm G}}),$

(14)

where $R_{\rm C}$ is the contact resistance of the source metal contact and $R_{\rm sg} \left( {V_{\rm G}} \right)$ is the voltage-dependent series resistance between gate-source opening.

Considering the linear variation of the potential at the interface between the source and the gate (equivalent to gradual channel approximation as long as the source-gate separation, $L_{\rm sg}$, is much longer than the surface depletion layer depth), the depletion layer width from the surface at any point in the gate-source spacing is given by^[44],

$h_{\rm s} \left( x \right)=\left\{ {\frac{2\varepsilon _{\rm s} }{qN_{\rm d} }\left[{V_{\rm sbi} -\phi _{\rm s}(x)+V(x)} \right]} \right\}^{1/2},$

(15)

where $V_{\rm sbi}$ is the surface built-in potential calculated earlier, while $\phi _{\rm s}(x)=\frac{V_{\rm sg} }{L_{\rm sg} }x$ and $V(x)$ are the surface potential in the ungated portion of the channel and the potential in the channel at point $x$.

The depletion layer thickness at the source and gate edges is respectively,

$h_{\rm 0s} =h_{\rm s}(0)=\left\{ {\frac{2\varepsilon _{\rm s}}{qN_{\rm d} }\left[{V_{\rm sbi} +V(0)} \right]} \right\}^{1/2},$

(16)

$h_{\rm 1s} =h_{\rm s}({L_{\rm sg}})=\left\{ {\frac{2\varepsilon _{\rm s} }{qN_{\rm d} }\left[{V_{\rm sbi} -V_{\rm sg} +V({L_{\rm sg}})} \right]} \right\}^{1/2}.$

(17)

Following the similar analysis of the modeling of $R_{\rm S}$ proposed for GaAs MESFET^[44], the voltage dependent source-gate series resistance can be computed by,

$R_{\rm sg} \left( {V_{\rm G} } \right)=\frac{1}{qN_{\rm d} \mu _0 W}\int\nolimits_0^{L_{\rm sg} } {\frac{{\rm d}x}{a-h_{\rm s}(x)}} .$

(18)

The above equation assumes the linear velocity-field characteristics in the ungated region of the channel. The two-dimensional simulations of the electric field profile in the gate-source spacing of the 4H-SiC MESFET in Figure 1 reveals a typical lateral electric field that is much less than the critical field for velocity saturation (not shown here), which confirms the validity of the above assumption.

A similar analysis is performed to find $R_{\rm D}$ at the ungated portion of the 4H-SiC MESFET drain end by appropriately modifying Equations (16) and (18).

2.3 Modeling of self-heating effects

For a biased MESFET, self-heating occurs when electrical energy is converted into thermal energy, increasing the lattice temperature which in turn affects electron mobility, ionization and saturation velocity^{[45, 46]}. SiC MESFETs operating at higher drain voltage and current leads to the decrement of mobility and saturation velocity, which ultimately reduces the drain current. The effect is more prominent at larger gate and drain voltages due to the high level of heat dissipation.

The self-heating effect incorporates the influence of temperature through the low-field mobility, the saturation velocity and the free carrier concentration of the device. The reduction of drain current is observed as the drain voltage increases. Here an iterative method proposed in Reference ^[45] is followed to find the $I$-$V$ characteristics where the current variation is shown by varying the temperature associated with the power dissipation of the 4H-SiC MESFET and drain voltage.

2.4 Modeling of $\boldsymbol{I}$-$\boldsymbol{V}$ characteristics

The analytical model of $I$-$V$ characteristics incorporate the Caughey-Thomas model of field-dependent electron mobility^[21], the substrate trapping of electrons by multiple deep-level traps and the two-dimensional analysis of the charge distribution under the gate.

The current at any point `$x$' in the channel under the Schottky gate including field dependent mobility and the substrate trapping is expressed as^[33],

$I_{\rm D} =qWn(x)\mu(E)E(x)\left[{a-h(x)-h_{\rm b}(x)} \right],$

(19)

where $E(x)$ is the lateral field along the channel, $n(x)$ is the channel electron concentration, $\mu(x)$ is the field dependent mobility, while $h(x)$ and $h_{\rm b}(x)$ are the depletion layer thicknesses under the metal gate and in the channel side of channel-substrate (CS) interface at a distance $x$ from the source end of the gate. The analytical expressions for $h(x)$ and $h_{\rm b}(x)$ are given by^[47],

$h(x)=\left\{ {\frac{2\varepsilon _{\rm s} }{qN_{\rm d} }\left[{V_{\rm bi} -V_{\rm gs} +V(x)}\right]} \right\}^{1/2},$

(20)

$h_{\rm b}(x)=\left\{ {\frac{2\varepsilon _{\rm s} }{qN_{\rm d} }\left( {\frac{N_{\rm sub}}{N_{\rm d} +N_{\rm sub} }} \right)\left[{U_{\rm bi} +V(x)} \right]} \right\}^{1/2},$

(21)

where $V_{\rm bi}$ and $U_{\rm bi}$ $(U_{\rm bi} =\frac{kT}{q}\ln \frac{N_{\rm d} }{n_{\rm sub} })$ are the built-in potentials of conventional metal-semiconductor and channel-substrate junctions, respectively; $n_{\rm sub}$ is the electron concentration in the 4H-SiC HPSI substrate; and $V(x)$ is the potential along the channel starting from the source end of the gate ($x=0)$. The term $\left[{a-h(x)-h_{\rm b}(x)} \right]$ in Equation (19) is the effective channel opening.

Solving Equations (19)-(21) along the length of the gate and considering the effect of source and drain series resistances modeled earlier, the $I$-$V$ characteristics of a 4H-SiC MESFET in the linear region incorporating substrate and surface trapping can be expressed as^{[22, 47]},

$$\begin{split} \label{eq22} I_{\rm D} ={} & YaV_{\rm P} \left\{ \left[{\frac{V_{\rm ds} -I_{\rm D} \left( {R_{\rm S} +R_{\rm D} } \right)}{V_{\rm P} }} \right]^{1/2}- \frac{2}{3}\left( {U_{\rm D}^3 -U_{\rm S}^3 } \right)\right. \\[2mm]& \left. -\, \frac{2}{3}k_{11} \left( {U_{\rm 1D}^3 -U_{\rm 1S}^3 } \right) \right\}, \end{split}$$

(22)

where $V_{\rm D}$ is the drain bias, and $V_{\rm P}$ and $k_{11}$ are constants given by,

$V_{\rm P} =\frac{qN_{\rm d} a^2}{2\varepsilon _{\rm s} }, \quad k_{11} =\left( {\frac{N_{\rm sub}}{N_{\rm sub} +N_{\rm d} }} \right)^{1/2},$

$U_{\rm S} =\left( {\frac{V_{\rm bi} -V_{\rm gs} +I_{\rm D} R_{\rm S} }{V_{\rm P} }} \right)^{1/2},$

$Y=\frac{qWv_{\rm sat} \mu _0 \left( {N_{\rm d} -N_{\rm sub}} \right)}{v_{\rm sat} L +\mu _0 \left[{V_{\rm ds} -I_{\rm D} \left( {R_{\rm S} +R_{\rm D} } \right)} \right]},$

$U_{\rm D} =\left( {\frac{V_{\rm bi} -V_{\rm gs} +V_{\rm ds} -I_{\rm D} R_{\rm D} }{V_{\rm P} }} \right)^{1/2},$

$U_{\rm 1D} =\left( {\frac{U_{\rm bi} +V_{\rm ds} -I_{\rm D} R_{\rm D} }{V_{\rm P} }} \right)^{1/2}, U_{\rm 1S} =\left( {\frac{U_{\rm bi} +I_{\rm D} R_{\rm S} }{V_{\rm P} }} \right)^{1/2}.$

Here $U_{\rm D} \left( {U_{\rm S} } \right)$ is the normalized depletion width under the gate at drain (source) and $U_{\rm 1D} \left( {U_{\rm 1S} } \right)$ is the normalized depletion width in the channel at the CS interface, $v_{\rm sat}$ is the electron saturation velocity, and $\mu _0$ is the low-field electron mobility.

Considering the channel length modulation, the channel under the gate is divided into the linear region ($L_1)$ and the velocity saturation region ($L-L_1 )$, as shown in Figure 1. The current equation at $x=L_1$ can be given as^{[22, 47]},

$$\begin{split} I_{\rm D} ={}& Y_1 aV_{\rm P} \left[{\frac{V\left( {L_1 } \right)-I_{\rm D} R_{\rm S} }{V_{\rm P} }}-\frac{2}{3}\left( {U_{\rm L1}^3 -U_{\rm S}^3 } \right)\right. \\[2mm]& \left.-\, \frac{2}{3}k_{11} \left( {U_{\rm 1L1}^3 -U_{\rm 1S}^3 } \right) \right]. \end{split}$$

(23)

where $Y_1 =\frac{qWv_{\rm sat} \mu _0 \left( {N_{\rm d} -N_{\rm sub}} \right)}{v_{\rm sat} L_1 +\mu _0 \left( {V\left( {L_1 } \right)-I_{\rm D} R_{\rm S} } \right)}$, $U_{\rm L1} =\left[{\frac{V_{\rm bi} -V_{\rm gs} +V\left( {L_1 } \right)}{V_{\rm P} }} \right]^{1/2}$, $U_{\rm 1L1} =\left[{\frac{U_{\rm bi} +V\left( {L_1 } \right)}{V_{\rm P} }} \right]^{1/2}$, where $U_{\rm L1}$ is the normalized depletion width under the gate at a point where the electron reaches saturation velocity and $U_{\rm 1L1}$ is the normalized depletion width in the channel at the CS interface.

The current equation at $x=L_1$, which corresponds to velocity saturation, can also be given as^{[21, 47]},

$I_{\rm D} =qW\left( {N_{\rm d} - N_{\rm sub}} \right)v_{\rm sat } \gamma a\left( {1-U_{\rm L1} -U_{\rm 1L1} k_{11} } \right),$

(24)

where $\gamma$ is the velocity saturation factor close to unity.

A two-dimensional analysis of Poisson's equation to calculate the potential in the depletion region under the gate can be expressed as^[47],

$$\begin{split} V_{\rm ds} -I_{\rm D} R_{\rm D} {}& =V\left( {L_1 } \right)+\frac{2E_{\rm c} a\left[{\dfrac{V_{\rm bi} -V_{\rm gs} +V\left( {L_1 } \right)}{V_{\rm P} }} \right]^{1/2}}{\pi } \\[4mm]& \times \sinh {\frac{\pi \left( {L-L_1 } \right)}{2a\left[{\dfrac{V_{\rm bi} -V_{\rm gs} +V\left( {L_1 } \right)}{V_{\rm P} }} \right]^{1/2}}}, \\ \end{split}$$

(25)

where $E_{\rm c}$ is the channel electric field corresponding to velocity saturation condition and $V\left( {L_1 } \right)$ is the potential in the channel at $x=L_1$.

Solving Equations (23)-(25) simultaneously, the drain current can be determined.

The DC transconductance (output conductance) can be computed by differentiating the current equation with respect to the gate voltage (drain voltage).

3. Results and discussion

It is evident from the previously reported literature that substrate and surface traps are the main causes for current degradation of the 4H-SiC MESFET. Though the trapping effects show the major impact on transient characteristics and frequency dispersion of transconductance, at this point of time, we have only depicted the impact on the DC characteristics. It may be noticed from the analytical model that the presence of deep-level traps and interface traps modifies the $I$-$V$ characteristics of the device. To study the same, the $I$-$V$ characteristics of the 4H-SiC MESFET structure in Figure 1 are simulated using the model equations with and without trapping effects. Seen in Figure 6(a) are the $I_{\rm D}$-$V_{\rm D}$ characteristics at $V_{\rm G}$ $=$ 0~V. The nature of the characteristics without trapping effects shows the usual expected behavior of the 4H-SiC MESFET. A significant reduction in the channel current is noticed due to the trapping of channel electrons by the deep-level traps at the channel-substrate interface. A similar behavior is observed in the $I_{\rm D}$-$V_{\rm G}$ characteristics of the same device plotted in the saturation region for $V_{\rm D}$ $=$ 40 V, as shown in Figure 6(b). The surface trapping effects on the modeled $I_{\rm D}$-$V_{\rm D}$ and $I_{\rm D}$-$V_{\rm G}$ characteristics of the 4H-SiC MESFET are also shown in the same figure. The surface traps are included in the model through the modulation of bias-dependent $R_{\rm S}$ and $R_{\rm D}$ by the interface states present at the 4H-SiC/SiO$_{2}$ interface, as explained in Section 2.2. Figure 6 reveals that the channel current is substantially reduced by the surface trapping and the extent of reduction depends on the surface passivation conditions as well.

Figure 7 shows the modeled $R_{\rm S}$-$V_{\rm G}$ characteristics of a 4H-SiC MESFET for two different $D_{\rm it}$ profiles^[42] (stating different surface passivations SP1 and SP2).

SP1-D$_{\rm it}^{\rm mid}$ $=$ 2 $\times$ 10$^{11}$ eV$^{-1}$cm$^{-2}$, $D_{\rm it}^{\rm CBedge}$ $=$ 6 $\times$ 10$^{13}$~eV$^{-1}$cm$^{-2}$, $D_{\rm it}^{\rm VBedge}$ $=$ 1 $\times$ 10$^{12}$ eV$^{-1}$cm$^{-2}$, $\sigma _1$ $=$ 0.25~eV.

SP2-$D_{\rm it}^{\rm mid}$ $=$ 1 $\times$ 10$^{10}$ eV$^{-1}$cm$^{-2}$, $D_{\rm it}^{\rm CBedge}$ $=$ 1 $\times$ 10$^{13}$ eV$^{-1}$cm$^{-2}$, $D_{\rm it}^{\rm VBedge}$ $=$ 1 $\times$ 10$^{12}$ eV$^{-1}$cm$^{-2}$, $\sigma _1$ $=$ 0.1 eV.

The two surface passivation conditions SP1 and SP2 (passivated using the nitrogen-hydrogen mixed plasma method for SiO$_{2}$/4H-SiC) are taken for two different samples at different annealing times, one with as-oxidized and the other annealed for 15 min^[42], yielding different interface trap densities and hence varied interface passivation conditions. The energy dependent $D_{\rm it}$-profile parameters in Equation (7) are extracted from the reported experimental results^[42] for SP1 and SP2. The contact resistance value ($R_{\rm C})$ is calculated in accordance with the typical specific contact resistance values for Ni/4H-SiC ohmic contacts reported^[48] (of the order of 10$^{-5}$ $\Omega \cdot$cm$^2)$, which is found to be 10 $\Omega$. The modeled results clearly show that the series resistance ($R_{\rm S})$ strongly depends on applied bias, similar to GaAs MESFETs^[44] as well as on the surface conditions^[17]. The nature of series resistance is found to decrease with the increase of gate voltage and for low values of $D_{\rm it}$. A similar behavior is observed in case of drain series resistance ($R_{\rm D})$ (not shown here) but the values are found to be much lower than source series resistance. In addition to the native bulk and interface defects in 4H-SiC, selective doping of the channel region in MESFET by ion-implantation followed by high temperature annealing damages the surface of the active region. For MESFETs, this may lead to enhanced interface trapping and may increase the series resistance of the device, as is evident from the modeled equations.

In Figure 8(a), our analytical model with multiple deep-level traps is compared with the two-dimensional simulations performed using Silvaco$^{\circledR ^[26]. The substrate in two-dimensional simulations is modeled considering the dominant traps responsible for substrate trapping (Table 1). In addition to the basic Poisson and continuity equations used in the simulator, the key physical models are SRH for generation and recombination, incomplete ionization of impurities and field-dependent mobility models. The two-dimensional MESFET simulation model considers a uniform doping in the channel, which approximates the ion-implanted MESFET^[12]. It is found from the figure that our model closely tracks the two-dimensional simulation results with the same device dimensions. The modeled $I$-$V$ characteristics, including the surface trapping effects, are also shown in the same figure and are validated by comparing with the two-dimensional simulation results. In the two-dimensional simulations, the surface traps are defined following the procedure reported by Deng et al.^[36].

Figure 8(b) shows the comparison of calculated results with the reported experimental results^[13]. The $I_{\rm D}$-$V_{\rm G}$ characteristics are obtained for a 0.5 $\mu$m MESFET with a 200 $\mu$m width and a channel thickness of 0.23 $\mu$m. By observing the nature of the characteristics, it is noted that the calculated result shows good agreement with the experimental results.

In our model, we incorporated a very thin layer of SiO$_{2}$ for passivation and assume that the $D_{\rm it}$ distributions considered for thinner passivated layers are justified. It is reported^[49] that the interface charge density ($D_{\rm it}$ distribution) within the bandgap of 4H-SiC of a MOS structure varies with the oxide thickness, with higher $D_{\rm it}$ values for thicker oxides. Since passivation layers are relatively thick as compared to gate oxides, for real devices, the surface effects may be more prominent and severe than computed earlier.

The temperature dependence of the modeled $I_{\rm D}$-$V_{\rm D}$ characteristics of the SiC MESFET including the major trapping and thermal effects is presented in Figure 9 for $V_{\rm G}$ $=$ 0 V and for operating temperatures 300 K and 500 K. At each temperature, the shift in $I_{\rm D}$-$V_{\rm D}$ is calculated for two cases: one considering only self-heating effects and the other with trapping and self-heating effects. Self-heating effects are found to aid the current reduction and are more prominent for gate-source voltages near to 0 V and for high drain bias, as shown in Figure 9. This is due to the fact that at higher drain and gate voltages, the heat generation is more and hence have a higher influence on device performance.

Remembering that at higher operating temperatures, small changes in the $D_{\rm it}$-profile are reported for 4H-SiC/SiO$_{2}$ interface^[50], due to a lack of concrete experimental data for temperature dependent $D_{\rm it}$ variations available in the literature, we have assumed slightly lower values of the earlier extracted $D_{\rm it}$-values at high temperatures. The values used for simulating the $I_{\rm D}$-$V_{\rm D}$ at 500 K are $D_{\rm it}^{\rm mid}$ $=$ 2 $\times$ 10$^{11}$ eV$^{-1}$cm$^{-2}$, $D_{\rm it}^{\rm CBedge}$ $=$ 4.8 $\times$ 10$^{13}$ eV$^{-1}$cm$^{-2}$, $D_{\rm it}^{\rm VBedge}$ $=$ 1 $\times$ 10$^{12}$ eV$^{-1}$cm$^{-2}$, $\sigma _1$ $=$ 0.28 eV and $\sigma _2$ $=$ 0.28 eV. These values are in the same range as reported for the SiC/SiO$_{2}$ interface^[50] of 4H-SiC MOSFET at the operating temperature of 200 C. A closer observation of Figure 9 reveals that at higher operating temperatures, the trapping effects both at the interface and substrate bulk are found to be less severe. The reason for this type of behavior may be due to the high probability of detrapping of electrons from the traps in the substrate and at the surface at high temperatures.

One of the important consequences of modeling is that once validated against experimental or simulation results, the model can be used to predict the performance of 4H-SiC MESFETs, even before the device fabrication. This information is a valuable tool for device optimization. Russo et al.^[51] have studied the geometrical optimization of gate-source scaling ($L_{\rm sg} )$ effects in AlGaN/GaN HEMTs with the knowledge of peculiar transport characteristics of GaN compared to GaAs/InP through Monte Carlo simulations. Their results suggest that down scaling of source-gate distance ($L_{\rm sg} )$ can enhance the device performance considerably. Deng et al.^[52] have further extended the previous studies^[51] to 4H-SiC MESFETs. Through two-dimensional numerical simulations, they have noticed that the $L_{\rm sg}$ scaling is more effective than the $L_{\rm gd}$ scaling for the overall improvement of the device DC and microwave performance. Both researchers have attributed the improved characteristics due to $L_{\rm sg}$ scaling to the increase in the carrier velocity with the electric field in the source-gate spacing of the device. We have also studied the geometrical scaling effects of $L_{\rm sg}$ and $L_{\rm gd}$ on the overall DC performance of the device using the modeled equations. In Figure 10(a), the $I_{\rm D}$-$V_{\rm G}$ characteristics are plotted for the 4H-SiC MESFET of Figure 1 at $V_{\rm D}$ $=$ 40 V by only varying the gate-source spacing ($L_{\rm sg} )$ and keeping $L$ and $L_{\rm gd}$ constant. It is observed that the reduction in $L_{\rm sg}$ improved the DC performance of the device. The improvement of the channel current is due to the reduction in the source-gate series resistance ($R_{\rm sg} )$, as can be seen from Equation (13). The effect of $L_{\rm sg} (L_{\rm gd} )$-scaling on the saturated drain current $I_{\rm DSS}$ of the 4H-SiC MESFET with $L$ $=$ 0.5 $\mu$m biased at $V_{\rm D}$ $=$ 40 V and $V_{\rm G}$ $=$ 0 V is plotted and is shown in Figure 10(b). For plotting the $L_{\rm sg} (L_{\rm gd} )$-scaling effects, $L_{\rm gd} (L_{\rm sg} )$ was kept constant at 1.75 $\mu$m and the $L_{\rm sg} (L_{\rm gd} )$ was varied from 2.5-0.5 $\mu$m. It is observed that $L_{\rm sg}$ scaling greatly increases the drain current whereas $L_{\rm gd}$-scaling has nearly no effect on the saturated drain current. This might be because of the weak dependence of $R_{\rm gd}$ on $L_{\rm gd}$ in our model. The modeled results are consistent with the earlier reported simulation results^{[51, 52]}.

Finally, the effects of substrate and surface trapping on the transconductance ($G_{\rm m})$ and drain conductance ($G_{\rm D})$ of the SiC MESFET that are derived from the DC $I$-$V$ characteristics are evaluated from the proposed model and are plotted in Figure 11. The observed characteristics are typical of a SiC MESFET. The nature obtained in Figure 11(a) is in accordance with the reported models^{[21, 22]} where it is demonstrated that the transconductance increases with the gate voltage and is fairly independent of the drain voltage in the saturation region. Figure 11(b) shows the drain conductance versus the drain voltage. For the linear region, the drain conductance is high and slowly decreases with the increase in drain voltage and becomes nearly independent at very high drain bias. As seen in the $I$-$V$ characteristics, the transconductance and conductance also show a decremented behavior when the trapping effects are included. It can be concluded that substrate and surface trapping degrades the transconductance and drain conductance of the device.

4. Conclusion

In this paper, we have presented an improved analytical $I$-$V$ model of a 4H-SiC MESFET directly on an HPSI substrate, which includes the analysis with and without trapping and thermal effects. The substrate trapping effect is realized by the inclusion of deep-level traps. We show here that even with HPSI substrates, the trapping effect cannot be neglected. The involvement of the recent and exact nature of the traps in the substrate bulk of the 4H-SiC MESFET gives a clear picture of the realistic nature of the device, which is an important feature of our model. The effects of parasitic series resistances at the source and drain end of the device are also taken into consideration. The effect of interface states is highlighted through the energy and temperature dependent trap density of interface states, making the model valid for any surface conditions. The model is made complete with the inclusion of self-heating effects. The model projects DC $I$-$V$ characteristics, transconductance and drain conductance of the simulated device. By analyzing the DC characteristics of the device, it is found that there is a significant reduction in drain current due to the substrate and surface trapping effects. The calculated results are in good agreement with reported experimental^[13] and two-dimensional simulations (Silvaco$^{\circledR }$-TCAD). Finally, we conclude that a complete DC analytical model of 4H-SiC MESFET is projected with all major trapping effects and this may be useful for realizing SiC based MMICs on HPSI substrates.