1. Introduction

The tunnel FET, based on the interband tunneling effect, has recently been the subject of a variety of both theoretical and experimental studies^{[1, 2, 3, 4]}.

It has been shown that the device has several superior electrical properties, like the subthreshold swing and OFF current $I_{\rm OFF}$, as compared to the conventional MOSFET.

TFETs have been widely studied in recent years due to their characteristic of overcoming the 60-mV/dec subthreshold swing (SS) limit of conventional MOSFETs at room temperature^[5]; this is seen because the SS of a TFET is independent of the temperature. Therefore TFETs can be considered as very good candidates for delivering operation at higher temperature without compromising on output characteristics. TFETs work on band to band tunneling principles; therefore they can be scaled down without degrading their properties^[6], such as the OFF state current, threshold voltage and subthreshold swings. For example, the OFF current, $I_{\rm OFF}$, and threshold voltage for a conventional MOSFET depend on the gate length scaling, but in the case of a TFET these properties remain constant with changing gate length scaling^[7].

In this paper, channel region electrical properties of the DG TFET such as the electric potential, electron density and electron quasi-Fermi potential are studied, and changes in these properties are found on comparing with the case for the conventional DG MOSFET. The paper is organized as follows: Section 2 presents the device structure and simulation setup, Section 3 presents device simulation results relating to the channel potential and electron quasi-Fermi potential, and the last part, section (4), gives the conclusions drawn from the work done in the paper.

2. The device structure and simulation setup

The DG TFET device structure under study is shown in Figure 1.

Here a transverse cut AA$'$ is taken. Cut AA$'$ is used to explore the results at point A, which is termed the surface or Si oxide interface, and at the middle of the channel, i.e. at the middle of the cut AA$'$, which is termed the midchannel point. The device parameters are listed in Table 1.

Simulations are performed using the TCAD device simulator Sentaurus^[9]. he models included are as follows: the nonlocal tunneling model, the Wentzel-Kramers-Brillouin (WKB) model with Fermi statistics, the band-gap narrowing model OldSlotboom without Fermi statistics, high field saturation mobility models, and the carrier transport model; and the Shockley-Reed-Hall (SRH), Auger carrier recombination, eMLDA and hMLDA models are included for correction of the density due to energy quantization. The doping profiles used are abrupt. For the n-type impurity, phosphorus, as a pentavalent impurity, is used and the gate workfunction is set as 4.1 eV. The device under study is calibrated against data given in Reference ^[8]. The electron and hole effective masses are tuned to match the tunneling current, while for the recombination current calibrations the carrier lifetimes are tuned. The calibrated results are shown in Figure 2.

3. Simulation results and discussion

} Tunnel FETs $I$-$V$ characteristics are determined by the barrier height and barrier width at the source and drain junctions. The channel potential profiles need to be evaluated in order to derive exact conduction and valence band energy profiles. Thus we can find the barrier widths and barrier heights at the source/channel junction as well as at the drain/channel junction. Using these, we can calculate the drain current under drain/gate bias. Therefore in this section the simulation results and discussion for a DG TFET at the surface (below 1 nm from the interface) and in the middle of the body are presented-i.e., at point A or A$'$ and at the middle of the channel. Electrical properties at the silicon/HfO$_{2}$ interface of the AA$'$ cut, i.e. at point A$'$, are termed surface electrical properties, and those at the middle of AA$'$, i.e. at the center of the channel, are termed midchannel properties.

The energy barrier width ($\delta x$), as expressed by Equation (1), decreases with the applied gate voltages, as shown in Figure 3 ^{[10, 11]}. At the same time, since the gate control over the channel dominates for higher gate voltages ($V_{\rm gs}\geqslant V_{\rm ds}$), we observe constant potential (and conduction/valence band energies, as shown in Figure 3) in the channel and sharp changes in the potentials near the junctions^{[12, 13]}.

Hence if a vertical (or transverse) cut AA$'$ is taken in the middle of the channel, as shown in Figure 1, then this will carry information about the potential and therefore the barrier height ($\delta\phi$). The barrier height is expressed by Equation (2) below^{[10, 11, 14]}.

We have

$\delta x=\frac{L_{\rm g}}{2}+x_{1},$

(1)

where $\delta x$ is the energy barrier width at the source junction, $L_{\rm g}$ is the gate length, and $x_{1}$ is the position in the channel after which the potential becomes constant along the lateral cut BB$'$ in the device; see Figure 1(a) (i.e., where the potential level starts).

Also, we have

$\delta\phi=E_{\rm F_{p}, source}-E_{\rm C, channel}(x_{1}), \label{eq:Barrier_height}$

(2)

where $\delta\phi$ is the energy barrier height, $E_{\rm F_{p}, source}$ is the source valence band Fermi energy, and $E_{\rm C, channel}(x_{1})$ is the channel conduction band energy just outside of the depletion region near the source/channel junction.

Effectively, the energy states between $E_{\rm V, source}$ and $E_{\rm F_{p}, source}$ are empty states. So the effective width must always be from $E_{\rm F_{p}, source}$ to $E_{\rm C, channel}(x_{1})$. $E_{\rm F_{p}, source}$ is the hole quasi-Fermi level in the source region, which acts as the reference terminal.

From the above mentioned barrier height and width, the average electric field across the tunnel junction can be determined, as given in Equation (3) below. The average electric field can be further used in Kane's model^[15] to evaluate the drain current, $I_{\rm ds}$, of the TFET device as given in Equation (4).

We have

$E_{\rm avg}=-\frac{\delta\phi}{\delta x}$

(3)

and

$I_{\rm ds}=\iint A_{\rm KANE}E_{\rm avg}^{2}\exp{\left(-\frac{B_{\rm KANE}}{E_{\rm avg}}\right)}, d x, d y$

(4)

where $A_{\rm KANE}$ and $B_{\rm KANE}$ are Kane constants, and $I_{\rm ds}$ is the width-normalized drain current (A/$\mu$m)

3.1 The electric potential and the eQFP

Initially the midchannel and surface electric potentials keep on increasing with the applied gate voltage, as shown in Figure 4; this regime goes from accumulation to inversion. But as the gate voltage, $V_{\rm gs}$, is further increased there is a decrease in both the midchannel and the surface potentials at higher $V_{\rm ds}$; this regime is essentially a very strong inversion one. This change is negligible for lower $V_{\rm ds}$ ($\leqslant$ 0.2) values. But as the drain voltage is increased, decreases in the midchannel potential and the surface potential are seen for higher applied gate voltages. The electron quasi-potential remains constant for low gate voltage but reduces monotonically for higher voltages, as shown in Figure 4(c). To explain this pattern for the electric potential and eQFP, we draw the resistive equivalent of the tunnel FET structure, as shown in Figure 1(b). Here the source and drain extension regime resistances $R_{\rm S}$ and $R_{\rm D}$ will remain constant and will depend on the extension regime widths and lengths, but the channel regime resistance $R_{\rm C}$ and the tunnel junction resistance $R_{\rm T}$ are the highest of all and will depend on both the applied gate, $V_{\rm gs}$, and the drain, $V_{\rm ds}$, voltages. At very low $V_{\rm gs}$ the tunneling junction resistance, $R_{\rm T}$ (${\gg} R_{\rm C}, R_{\rm D}, R_{\rm S}$), is substantially higher; thus whatever drain voltage is applied, it will be seen at the tunneling junction as an eQFP ($\phi_{\rm F}=V_{\rm ds}$), as shown in Equation (5) and as is also clear from the simulations of Figure 4. Here the source is degenerately doped; thus it will have the lowest resistance. The voltage division rule can be applied to find the quasi-Fermi potential, as shown in Equation (5):

$\phi_{\rm F}(x)=\left[1+\frac{R_{\rm D}+R_{\rm C}(L_{\rm g}-x)}{R_{\rm C}(x)+R_{\rm T}+R_{\rm S}} \right]^{-1}V_{\rm ds},$

(5)

where $\phi_{\rm F}$ is the electron quasi-Fermi potential in the channel, $R_{\rm S}$ and $R_{\rm D}$ are the source and drain extension regime resistances respectively, $R_{\rm T}$ is the tunneling junction resistance and $R_{\rm C}(x)$ is the channel regime resistance at distance $x$ from the origin.

As the applied gate voltage $V_{\rm gs}$ is increased, the tunneling resistance $R_{\rm T}$ will decrease, while other resistances will remain the same in Equation (5); this will make the resistive drop a little more comparable in the drain regime. Also the effect of the channel regime resistance ($R_{\rm C}$) will be visible in the aforementioned equation, and the combined effect of these resistances will cause the eQFP($\phi_{\rm F}$) to decrease continuously as $V_{\rm gs}$ is increased.

For higher $V_{\rm ds}$, the channel regime acts like a transition region and in transition regions the electron quasi-Fermi energy (eQFE) will always be above the valence bands and below the conduction bands, as shown in Reference ^[16]. Therefore, at higher values of $V_{\rm ds}$ ($>$ 0.5 V), the eQFPs will be less than the applied drain voltage, $V_{\rm ds}$, even at lower $V_{\rm gs}$, as shown in Figure 4.

To explain the resistive drops in the device, the drain and source contacts were created in such a way that $R_{\rm S}$ and $R_{\rm D}$ drop to zero; therefore the potential drop due to the drain extension regime will reduce to zero, as shown in Figure 5. This will make the midchannel potential and eQFPs stick at a particular potential and the surface channel potential will keep on increasing. In Equation (5), with $R_{\rm D}=0$ and for lower channel widths, the channel regime resistance $R_{\rm C}$ is very small as compared with $R_{\rm T}$; thus the second term in Equation (5) will be negligibly small, which gives a channel eQFP $\phi_{\rm F}\approx V_{\rm ds}$ that is also explained by Figure 6, which shows the variation of the midchannel potential, the surface potential and the eQFP with the gate voltage. We observe that the reduction in the channel electric potentials and the eQFPs for the TFET structure, after a maximum value, occurs because of $I_{\rm ds}R_{\rm D}$ drops only. The point where the peak values of the surface, midchannel and eQF potentials occur is the point after which there is considerably larger current flow, which in turn increases the $I_{\rm ds}R_{\rm D}$ drops; therefore there is an equivalent decrease in voltage ($\delta V=I_{\rm ds}R_{\rm D}$). The gate control over the surface potential is very strong as compared with those over the midchannel potential and the eQFP; therefore the surface potential decreases slowly, while a larger decrease in the midchannel potential and eQFPs is seen, as shown in Figure 4.

Although the drain extension regime resistance, $R_{\rm D}$, is found in every double-gate and nanowire device, such as a double-gate MOSFET, we do not see such channel potential and eQFP patterns. In the case of DG MOSFETs the channel potential will get tied to the source, as it has less potential than the drain and is electrically connected to the DG MOSFET channel. But in the case of TFETs the source is electrically isolated from the channel; therefore, the channel potential will get tied to the drain potential level at higher drain or gate voltages; hence the resistive drop will affect the channel properties in the case of DG TFETs. In the case of bulk or planar TFETs this effect is not visible as the (bulk $\sim$fin) width is very large, which makes the material resistance almost zero in all regimes except the tunnel junction one.

Electron densities for the midchannel and surface are shown in Figures 7 and 8, respectively, for the TFET structure given in Figure 1(a). In the case of DG MOSFETs, the electron densities saturate very fast, while in the case of DG TFETs, the electron densities will completely depend on the applied drain voltages, which determine the eQFP in the whole channel. It is also observed that significant tunneling occurs after inversion only; therefore the $I_{\rm ds}R_{\rm D}$ drop will be visible, at least after the channel inversion. The surface and midchannel electron densities for the structure given in Figure 5 are also the same. Thus it can be concluded that the drain extension resistance does not affect the channel electron densities.

Thus in a TFET, electron densities are controlled by both gate and drain voltages, while in MOSFETs, the gate voltage determines the channel electron density.

3.2 Gate length scaling effects

To generalize the phenomenon observed for the DG TFET, gate length scaling is also taken into account. As discussed in the above section, the channel also acts like a resistance in the case of a TFET. To explore the channel regime resistive effects, we restructure the TFET device under simulation in such a way that the source and drain extension regime resistances drop to zero (see Figure 5) and the device has only the tunnel junction resistance $R_{\rm T}$ and the channel regime resistance $R_{\rm C}$. Now, if we make the channel regime larger, then $R_{\rm C}$ will be increased. Therefore, the resistive drop in the channel will also be increased. Since the midchannel, surface and eQF potentials are taken at $x=0$, at which the channel resistance is almost half of its maximum value, i.e. $R_{\rm C}(0)=\frac{R_{\rm C}(L_{\rm g}/2)}{2}$, there will be a reduction of the midchannel and surface potentials at higher applied gate voltages, as shown in Figure 9, and, in the same way, the eQFP will also be reduced for higher channel lengths.

Thus for larger gate lengths the effective potential at the tunnel junction will be reduced because of the drain extension regimes as well as because of the dominating channel regime resistances, and this will degrade the ON current while the subthreshold swing and OFF current will remain unchanged.

3.3 $\boldsymbol{I}$-$\boldsymbol{V}$ characteristics

Current versus gate voltage characteristics are shown in Figure 10. The dotted lines denote the $I$-$V$ characteristics without an $I_{\rm ds}R_{\rm D}$ drop, while the solid lines denote the $I$-$V$ characteristics with the drain extension regime resistance $R_{\rm D}$. As is clear from the $I$-$V$ plots, there is a significant effect of the drain resistive drop for higher gate voltages and higher drain voltages. To explain this, we can refer to the energy band diagrams given in Figure 3. As shown in Figure 3, the potential drop (the negative of the energy drop) due to drain extension resistance is seen for higher applied gate (drain ) voltages at the channel/drain junction, which in turn causes a drop of the channel potential value at the source/channel junction; therefore the energy barrier at the source/channel junction, and hence also the current, will decrease for higher gate voltages, but at the same time the higher gate voltage has more control over the channel, and hence the barrier width at the source/channel junction reduces, a process which will continue on increasing the drain current with applied gate voltages. Therefore the combined effect of these two determines the $I$-$V$ characteristics, and a drop in the gate transconductance (the slope of the $I_{\rm ds}$-$V_{\rm gs}$ curve) as a result of this will be seen for higher gate voltages. The transconductance determines different kinds of properties for analog circuits, such as the gain of a differential amplifier; therefore if we are using a DG TFET for analog applications, then we should optimize the biasing of the circuit in such a way that these lower transconductance points can be avoided.

4. Conclusions

A detailed investigation using TCAD simulations is discussed for a double-gate tunnel FET channel electrical potential and electron quasi-Fermi potentials. The channel potential decreases with applied gate voltages, which is never seen for n-p-n devices (DG MOSFETs and nanowires). It is found that this drop in channel potential has a great impact on the $I$-$V$ characteristics of the DG TFET, and it is seen because of the resistive drop $I_{\rm ds}R_{\rm D}$ in the drain extension regimes. This drop will increase with increasing drain extension length or decrease in the silicon fin width $T_{\rm Si}$ as the drain regime resistance $R_{\rm D}$ increases. This drain extension regime resistance also affects the electron quasi-Fermi potentials, but the electron densities in the channel regime will not be affected by the drain regime resistive drop. The channel regime resistance is also observed for higher gate length; this has a great effect on the $I$-$V$ characteristics of the DG TFET device. The study is done from channel length 50 nm to 500 nm and it is found that the increasing channel length is the cause of the increasing channel regime resistance and thus the degrading of the ON current. These channel regime electrical properties should be very useful in determining the tunneling current.