1. Introduction

With the rapid development of aerospace technology and deeper exploration of space,the requirements for performance of spacecraft components are also increasing. Correspondingly,the reliability and radiation-hardened performance of complex integrated circuits (ICs) is facing increasingly-strict requirements. Therefore,the single-event effects (SEE) prediction technique for complex ICs has been become a thriving area of research.

The experimental projects investigating SEEs in complex ICs are made according to the type of circuit tested,but most of the test modes selected for different users are not the same. The SEE sensitivity of complex ICs depends not only on the cross section of sensitive modules but also on the behavior of data patterns on the system. Some functional modules within these complex ICs can be measured directly,while others cannot. The sensitivities of different modules may vary greatly,and for the same module may also vary with various test patterns. At present,the SEE sensitivity of complex ICs is characterized mainly by cross section and linear energy transfer,$\sigma$ and LET curves and the error rate under a certain test pattern. However,the SEE sensitivity of complex ICs has a strong dependence on the test patterns^[1]. In many cases,determining how to calculate the cross section of complex ICs according to information obtained from the limited testing patterns is pivotal in the process of cross section prediction. A mathematic model based on the physical meaning of each sensitive parameter and influence coefficient of patterns is established which combines SEU sensitivity parameters and error rates of complex ICs.

The conventional characterization is described by the cross section of memory cells and a certain test pattern. ICs of different manufacturers are tested under their own defined test patterns. The SEE sensitivity obtained is different. So as expected,the SEE sensitivity prediction of complex integrated circuits is inconsistent and part-specific. In this paper,a method dividing the main functional modules is proposed and the intrinsic cross section and the duty cycles of different sensitive modules are measured. The intrinsic cross section is the cross section when the sensitive module is mostly used during the test. The alleged duty cycle of a particular resource is the percentage of time the resource is active. By combining the intrinsic cross section and the duty cycle of different sensitive modules,a universal method of predicting the applied cross section of complex ICs under different test patterns is proposed. The applied cross section is the cross section obtained under a certain functional test pattern. A mathematic model which describes SEU sensitive parameters and error rates of complex ICs is established. Two different prediction methods to calculate the applied error rate of complex ICs according to the intrinsic cross section are proposed and verified by experiments,which provides a universal method for converting the simulation results into the actual on-orbit experimental data.

2. Prediction routes

As for the SEE sensitivity prediction of complex ICs,the aim is to obtain the error rate. The prediction is a process of deriving the applied error rate from the intrinsic cross section. There are mainly two routes to assess the applied error rate.

The first route to predict the applied error rate is described as follows:

(1) The target circuit is divided into several modules which can be tested easily; the division principle is described in Section 3.2.

(2) The intrinsic cross sections of different sensitive modules are obtained; the acquisition method is described in Section 3.4.

(3) The duty cycles of different sensitive modules are calculated when executing a certain test pattern; the calculating method is described in Section 3.5.

(4) The applied cross section is obtained according to the synthesized algorithm described in Section 3.3.

(5) The error rate is calculated with space radiation^[2]; the calculation method is described in Section 3.6.

The route above is applied to the ICs of several sensitive modules,which takes all SEE error rate into account. If the complex IC is of a single sensitive module,there is another route for calculating the error rate.

The second route to predict the applied error rate is described as follows:

(1) The target circuit is divided into several modules which can be tested easily; the division principle is described in Section 3.2.

(2) The intrinsic cross sections of different sensitive modules are obtained; the acquisition method is described in Section 3.4.

(3) The intrinsic error rate of the single sensitive module is obtained by space radiation; the calculation method is described in Section 3.6.

(4) The conversion factors of error rate are obtained; the calculation is described in Section 3.6.

(5) Multiplying the intrinsic error rate by the conversion factor gives a value for applied error rate.

A flowchart of error rate prediction is illustrated in Figure1.

3. Experimental details

3.1 Test samples

The experimental circuit is a 32-bit embedded RISC microprocessor which is illustrated in Figure2. Experimental circuits can be used to meet a variety of aerospace missions in on-board embedded real-time computer systems. Memories and related peripheral circuits just need to be added to form a complete,single-board computer system. The experimental circuit is fabricated in bulk silicon CMOS 180 nm technology,with a substrate thickness of 400 $\mu$m.

3.2 Divided modules and test patterns

SEE evaluation of a microprocessor is an arduous task due to its complexity. Firstly,the target circuit is divided into several modules which can be easily tested; the division principles and assumptions are as follows:

(1) The module is relatively independent and perfect in function,and a separate test can be performed on it.

(2) The module has clear division in the physical layout.

(3) The module is dominated by a single type of single-event effect.

Taking the characteristic of measurability as the major premise and synthesizing the above principles of classification,the target circuit is divided into three parts: cache area,register area,and the rest of the area^[3]. The rest of the area mainly includes combinatorial logic and some registers that cannot be measured directly.

In this paper,various test patterns are executed on different functional modules,which contain test patterns for memory modules and functional modules. During the memory tests,cache and register have the highest utilization. The number of SEUs measured in cache and register areas are recorded separately during the process of irradiation and then the intrinsic cross section of both is determined. The number of SEUs and SEFIs is recorded during the functional tests and then the applied cross section of a certain test pattern is obtained.

3.3 Prediction of the applied cross section

The SEU sensitivities of a microprocessor not only depend on the physical module cross section but also on the duty cycles imposed by the instruction stream. For a storage module,this is the percentage of time when the module holds a live value which is going to be used sometime during pattern execution. Multiplying the average cross section per bit by the total number of bits in the device gives an overestimate of the device cross section because not all bits are used at all times. A better method is to estimate the number of “live and relevant” registers whose SEU will cause observable errors during the relevant pattern execution and use that as the number of bits. A software tool is presented in Figure3 for estimating the duty cycles of registers in a test pattern. By knowing the intrinsic cross section of each module,$\sigma_{\rm i}$,and their associated duty cycle,$f_{\rm i}$,the total SEU cross section of the microprocessor,$\sigma_{\rm T}$,executing that special test pattern can be predicted by:

$$\begin{equation} \sigma _{\rm T} =\sum \sigma _{\rm i} f_{\rm i}. \end{equation}$$

(1)

This prediction can be done if the $\sigma_{\rm i}$ and $f_{\rm i}$ are known. The tool presented in Figure3 can be extended to estimate the $f_{\rm i}$ of different modules^[4].

3.4 Acquisition of intrinsic cross section

The method presented above is used to predict the cross section under different test patterns. Firstly,the intrinsic cross section of different modules needs to be acquired. There are mainly two ways to accomplish this:

(1) To obtain the intrinsic cross section directly by test.

(2) Some modules cannot be accessed directly; these cross sections need to be acquired indirectly.

In this section,a method that uses this basic formula for estimating the intrinsic cross section $\sigma_{\rm i}$ is proposed.

The target circuit is divided into three parts: the cache area,the register area and the rest of the area. So,the cross section of the device is:

$$\begin{equation} \sigma _{\rm T} =\sigma _{\rm cache} f_{\rm cache} +\sigma _{\rm register} f_{\rm register} +\sigma _{\rm rest} f_{\rm rest}. \end{equation}$$

(2)

$\sigma_{\rm cache}$,$\sigma_{\rm register}$,$\sigma_{\rm rest}$ is respectively the intrinsic cross section of the cache area,the register area and the rest area in the microprocessor,$f_{\rm cache}$,$f_{\rm register}$ and $f_{\rm rest}$ is respectively the duty cycle of the cache,the register,and the rest during the execution of a certain test pattern. Three different equations with three unknowns,namely $\sigma_{\rm cache}$,$\sigma_{\rm register}$ and $\sigma_{\rm rest}$ are obtained by changing the value of the $f_{\rm i}$. The three patterns are executed while the microprocessor is irradiated,and the error rate for each of them is measured. Solving these equations will give us the three unknown cross sections^[5].

The cross section of the combinatorial circuits,$\sigma_{\rm comb}$,increases linearly with clock frequency. Cross section of sequential circuits,$\sigma_{\rm seq}$,has shown different behaviors with clock frequency. If we know how $\sigma_{\rm seq}$ changes for the sequential modules used in the circuit under test,this property can be used to break the linear dependencies in our equations by running the test patterns at different clock frequencies. For example,assuming that $\sigma_{\rm seq}$ does not change with clock frequency,there exists a relationship shown as follows while the microprocessor is operated at its nominal frequency ($w_{1})$,half its nominal frequency ($w_{2}$ $=$ $\frac{1}{2}w_{1})$,or another frequency.

$$\begin{equation} \begin{cases} \sigma _{{\rm register}@w_2} =\sigma _{{\rm register}@w_1},\\[2mm] \sigma _{{\rm caches}@w_2} =\sigma _{{\rm caches}@w_1},\\[2mm] \sigma _{{\rm rest}@w_2} =k\sigma _{{\rm rest}@w_1}. \\ \end{cases} \end{equation}$$

(3)

The resulting equations will be:

$$\begin{equation} \begin{cases} \sigma _{{\rm T}@w_1} =\sigma _{{\rm register}@w_1} f_{\rm register} +\sigma _{{\rm caches}@w_1} f_{\rm caches} \\[1mm] \qquad \qquad +\sigma _{{\rm rest}@w_1} f_{\rm rest},\\[2mm] \sigma _{{\rm T}@w_2} =\sigma _{{\rm register}@w_1} f_{\rm register} +\sigma _{{\rm cacches}@w_1} f_{\rm cacches} \\[1mm] \qquad \qquad +\,\frac{1}{2}\sigma _{{\rm rest}@w_1} f_{\rm rest},\\[2mm] \cdots \\ \end{cases} \end{equation}$$

(4)

which can be solved to get separate $\sigma_{\rm rest}$,$\sigma_{\rm cache}$ and $\sigma_{\rm register}$^[5].

In summary,clock frequency dependency can be used just like duty cycles for creating linearly independent equations. Note that this method will not work if $\sigma_{\rm comb}$ and $\sigma_{\rm seq}$ have the same frequency dependency.

The basis of our proposed method is as follows. A set of patterns that exercise a subset of the functional modules of the chip are written,each of them is with known and different duty cycles. These patterns are run while the system is irradiated and the total cross section is measured by counting the total number of errors that occur in the execution. Finally,the resulting system of the linear equations is solved to get the individual cross section.

3.5 Calculation of duty cycle

In this paper,an accurate method to evaluate the applied cross section of microprocessor is presented. The discrepancy on SEE sensitivity caused by different test patterns is considered. It is difficult to determine the duty cycle of registers due to the inherent complexity of real application patterns. Indeed,real application patterns are large and complex,which contain loops,nested loops,conditional statements,and subroutine calls,etc. For a complex pattern with millions of instructions per execution cycle,the task of determining the duty cycle of the register becomes unmanageable. The test pattern is broken down into three manageable parts: the initialization part,the pattern loop part and the data read out part. The duty cycles of different functional modules in these three parts are calculated separately,and then the final duty cycles of functional modules are determined. The flowchart for duty cycle calculation is shown in Figure3.

In Figure3,i is the sensitive module; $f_{\rm i1}$,$f_{\rm i2}$,$f_{\rm i3}$ are the duty cycles of different functional modules,respectively,in part of the initialization,part of the pattern loop,and part of the data read out; 1,2,3 in $f_{\rm i1}$,$f_{\rm i2}$,$f_{\rm i3}$ delegate part of the initialization,part of the pattern loop,and part of the data read out; $t_{\rm i1}$,$t_{\rm i2}$,$t_{\rm i3}$ delegate the usage time of the sensitive modules in part of the initialization,part of the pattern loop,and part of the data read out; $T_{1}$,$T_{2}$,$T_{3}$ delegate the execution time of the pattern in part of the initialization,part of the pattern loop,and part of the data read out. The final duty cycles of different sensitive modules during execution of the entire pattern are obtained according to the calculation rules: $f_{\rm i}=g(f_{\rm i1},f_{\rm i2},f_{\rm i3})=(t_{\rm i1}+t_{\rm i2}+t_{\rm i3})/(T_{1}+T_{2}+T_{3})$.

3.6 Calculation of error rate

After determining the applied cross section,it must be converted into an error rate. Currently,based on the cross section obtained by ground simulation experiments and combining the distribution of heavy-ion and high-energy protons on the space orbit,the calculation of error rate is fulfilled by evaluation software.

The intrinsic error rate and applied error rate of device can be calculated by evaluation software (space radiation) based on the intrinsic cross section and the applied cross section. Multiplying the intrinsic error rate by the conversion factor gives an evaluation value of applied error rate^[1]. The conversion relationship of the two is as below:

$$\begin{equation} R_\varepsilon =\varepsilon R_0 , \end{equation}$$

(5)

where $R_{\varepsilon }$ and $R_{0}$ are the applied error rate and intrinsic error rate respectively. $\varepsilon$ is the conversion factor which is the average value of duty cycles of registers.

The conversion factor can be obtained by heavy-ion testing,which is calculated as follows:

$$\begin{equation} \varepsilon =(\sigma _{\rm ia} /\sigma _0 )({\rm LET}_{\rm th0} /{\rm LET}_{\rm thia} )^2, \end{equation}$$

(6)

where $\sigma_{\rm ia}$ and $\sigma_0$ are the applied cross section and the intrinsic cross section. LET$_{\rm thia}$ is the SEE threshold during the test of applied cross section and LET$_{\rm th0}$ is the SEE threshold during the test of intrinsic cross section.

The conversion factor can also be obtained by simulation of injection,which is calculated as follows:

$$\begin{equation} \varepsilon =E_0 /E, \end{equation}$$

(7)

where $E_{0}$ is the number of observable faults when executing computer fault injections. $E$ is the total number of fault injections.

Therefore,the intrinsic error rate of the device and the applied error rate under a certain test pattern have a relationship,which is shown as follows:

$$\begin{equation} R_\varepsilon =R_0 (\sigma _{\rm ia} /\sigma _0 )({\rm LET}_{\rm th0} /{\rm LET}_{\rm thia} )^2=R_0 E_0 /E. \end{equation}$$

(8)

4. Test results

4.1 Verification of cross section prediction

Different modules were irradiated and their intrinsic cross sections obtained. Experimental results show that the cross section of the combinatorial logic area is far smaller than that of the cache and register areas. So,the cross section of the combinatorial logic area is ignored during the calculation of $\sigma_{\rm T}$.

The applied cross section predicted is obtained according to the method presented above. A comparison between the predicted results and experimental results is shown in Table1.

As can be seen from the data in Table1,when operating on the mode of cache off,the cross sections obtained by the prediction method and experimental test fit well; the deviation is less than 20%. The main uncertainty of the results is the statistical error for a small number of SEUs and also for the total number of ions,which is less than 10$^{7}$. Therefore,the deviation within 20% is deemed acceptable.

With the prediction method described above,another set of experimental data which has been carried out using different heavy-ions are verified. The comparison result is shown in Table2.

According to the data in Table2,the cross sections obtained by the prediction method and experimental test fit well. Deviation of it is within 15% which is considered reasonable.

Although the method in this paper is proposed for microprocessors,it can also be applied to other devices in general. By testing the cross section and duty cycle of individual modules,the sensitivity of any functional modules can be predicted.

4.2 Verification of error rate prediction

The test error rate is calculated by error rate evaluation software based on the applied cross section obtained by on-ground experiments.

Predicting the error rate is handled by the error rate evaluation software based on the applied cross section which is obtained by combining the intrinsic cross section and the duty cycle of different sensitive modules.

As seen from Table3,the deviation between the test error rate and the predicting error rate is less than 15%.

The data validation of the conversion relation between the intrinsic error rate and the applied error rate is as follows: the intrinsic cross section of register is 4.39 × 10$^{-4}$ cm$^{2}$/device,its LET threshold is 1.86 MeV$\cdot$cm$^{2}$/mg,and its error rate is 5.45 × 10$^{-2}$/device$\cdot$day.

When the full functional test pattern is executed on the device,the applied cross section of the device is 2.86 × 10$^{-6}$ cm$^{2}$/device,its LET threshold is 11.3 MeV$\cdot$cm$^{2}$/mg,and its error rate is 1.24 × 10$^{-5}$/device$\cdot$day.

The applied error rate of the device under the same test pattern obtained by Equation (1) is 9.26 × 10$^{-6}$/device$\cdot$day. Therefore,deviation between these two calculations of error rate is on the order of 20%.

5. Conclusion

In this paper,an SEE rate prediction method dividing the main functional modules is proposed. The intrinsic cross section and the duty cycles of different sensitive modules are obtained during the execution of various patterns. A method for extracting the duty cycle is presented and a set of test patterns with different duty cycles are implemented experimentally. By combining the intrinsic cross section and the duty cycle of different sensitive modules,a universal method to predict SEE sensitivities of different test patterns is proposed,which is verified by experiments based on the target circuit of a microprocessor. Verification of cross section prediction shows that the deviation of both the results is less than 20%. A mathematic model which describes SEU sensitive parameters and error rates of complex ICs is established and is verified by heavy ion tests. Verification of the error rate shows that the deviation between the test error rate and the predicting error rate is less than 15%. The prediction technique is able to predict the error rate of a microprocessor for various applications without having to run all of them in radiation experiments. Therefore,this paper provides an effective testing method for the SEE sensitivity analysis of different test patterns and verification of the reliability of the device.