1. Introduction

The integrated voltage controlled oscillator (VCO) is widely used in various system blocks to accomplish predominant radio frequency communication systems^[1]. Among the specifications, such as the phase noise, the tuning range, the dc power consumption and the output power, phase noise is a prime criterion to evaluate the performance of the VCO. The phase noise of a VCO near carrier frequency typically depends on the quality factor ($Q$) of the LC tank used in the oscillator and the noise of the active devices. The flicker noise ($1/f)$ of the GaAs HBT device is better than that of the CMOS or HEMT device^[2]. Furthermore, GaAs HBT is very attractive to be used for millimeter wave applications due to its reliable fabrication process and lower manufacturing cost. Therefore, the GaAs HBT technology is generally considered as a good choice for low phase noise VCO design. Differential topology is generally used instead of the single-ended one to reduce common node noise for VCO, even though it requires more elements. Besides, differential structure offers high loop gain, making it a common method to design differential VCO in radio frequency integrated circuits (RFICs).

Another important determinate factor of phase noise is the amplification configuration of active devices. The common-emitter (CE) is a more favorable configuration due to its moderate input impedance and large output impedance^[3]. In addition, it also has the highest gain compared with the common-base (CB) configuration or common-collector (CC) configuration. However, the CE configuration has a 180$^\circ$ phase shift between the base and the collector, thus a feedback network must be inserted to compensate for the phase shift. One method is to adopt a classical cross-coupled structure^[4], while another is to use a $\pi$-feedback network, which consists of capacitors and inductors. Unlike the construction described in Reference ^[5], a novel $\pi$-feedback structure is employed in this design. It has a significant advantage over the former one in both technology sensitivity and quality factor ($Q$).

In this paper, a differential LC VCO with a novel topology using a $\pi$-feedback network and CE configuration is designed and fabricated using 1-$\mu$m GaAs HBT technology from the WIN semiconductors. The on-wafer test shows that the phase noise of the proposed VCO can achieve $-96.47$ dBc/Hz at 1~MHz offset from the 28.633 GHz carrier frequency. Since the VCO plays a crucial role in the phase-locked loop (PLL), the successful fabrication of the designed VCO is of great importance on building a PLL operation at the Ka band.

2. Circuit design

The HBT device, fabricated by the WIN semiconductors 1-$\mu$m GaAs HBT process, typically exhibits a maximum unit current gain frequency ($f_{\rm T})$ of 75 GHz, and a maximum unit power gain frequency ($f_{\rm max})$ of 80 GHz, which has a vertical structure and a vertical current flow. It is designed by using a hetero-junction between the emitter and the base with a high base doping and a thin base thickness, leading to a high cut-off frequency. This makes the device possibly achieve a fast speed, high transconductance, high linearity and low power consumption, which are good for VCO circuit application. Passive components, including the metal-insulator-metal (MIM) capacitor, micro-strip line, thin film resistor, two metal layers, and back side via holes are also available in the process.

The basic building block of the $\pi$-feedback VCO is shown in Figure 1, in which the common-emitter (CE) configuration is adopted. The $\pi$-network consists of $L_{\rm b}$, $L_{\rm c}$, and $C$ is performed as a feedback path.

The proposed differential $\pi$-feedback VCO is shown in Figure 2, in which two CE configuration $\pi$-networks are adopted. In order to realize a high $Q$ factor, the core of the VCO with AIT (asymmetric inductance tank) and SIT (symmetric inductance tank) will be considered. The $Q$ factor can be expressed as

$Q_{\rm Tank} =\frac{R_{\rm P}}{\omega _0 L},$

(1)

where $R_{\rm P}$ is the parallel resistance of the $LC$ tank at the resonant frequency ($\omega_{0})$, and $L$ is the inductance of the tank. In view of the layout, the area of the AIT is bigger than the SIT, which will seriously affect the chip size. The inductance of the AIT is bigger than the SIT, because the inductance is proportional to the area of the inductors. $\omega_{0}$ depends on the center carrier frequency, therefore, it will be almost the same in both the AIT and the SIT^[6]. Thus, the $Q$ factor of the SIT is definitely superior to the AIT. As to the capacitor, the wave shape of the core stage with asymmetric capacitance has a little distortion in the headroom^[7]; the way to eliminate the headroom distortion is to use symmetric capacitance in the SIT structure called SCSIT.

In order to improve the oscillation frequency and reduce the chip size, two micro-strip lines, instead of conventional spiral inductors, are used in the $\pi$-network. Two transistors in parallel act as a varactor to obtain a broad tuning range. The oscillation frequency can be calculated by

$f=\frac{1}{2\pi \sqrt {\left( {L_{\rm c1} +L_{\rm c2} +L_{\rm b}} \right)\left( {C_{\rm bc} +C_{\rm tune} } \right)}},$

(2)

where $L_{\rm c1}$ and $L_{\rm c2}$ are the inductances of the feedback inductor at the collector. $L_{\rm b}$ is the inductance at the base. $C_{\rm bc}$ is the capacitance of the base-collector (BC) junction of transistor M. $C_{\rm tune}$ is a varactor array composed of eight reverse biased barrier capacitors.

To achieve a wide tuning range, the varactor must contribute to a larger fraction of the total tank capacitance^[8]. The input and output impedances of the $\pi$-network are determined by the value of $L_{\rm c1}$, $L_{\rm c2}$ and $L_{\rm b}$. Furthermore, a high $C$ and a low $L$ result in a high $Q$ value, which benefit phase noise performance^[9], as indicated in Equation (3)^[10]. Thus, a tradeoff must be taken into consideration among the oscillation frequency, impedance match, frequency tuning range and phase noise^[11].

$L\left( {\Delta \omega } \right)=10\lg \left[{\frac{2KT}{P_{\rm sig} }\left( {\frac{\omega _0 }{2Q_{{\rm tan} k} \Delta \omega }} \right)^2} \right].$

(3)

The differential output signals are taken from the emitters to avoid direct connection between the LC tank and the load. Since the differential output ports are at the emitters, the oscillation transistors acting as power suppliers and amplifiers are also performing as buffer stages themselves. Two small capacitors are applied at output nodes for dc decoupling and to further reduce the effect of outside load on the VCO.

3. Measurement results and discussion

All of the passive components, such as micro-strip lines, DC-block and bypass capacitors, were simulated with a full-wave EM simulator. Based on the transient and harmonic simulations using an Agilent advanced design system (ADS), a layout of the designed VCO was accomplished with the Virtuoso layout in Cadence. After rule checking and electromagnetic (EM) simulation, the designed VCO was fabricated using the 1-$\mu$m GaAs HBT process of the WIN semiconductors. The micrograph of the designed VCO is shown in Figure 3 with a chip size of 0.7 $\times$ 0.7 mm$^{2}$. All the devices are arranged symmetrically to have a differential output without the common node noise effect.

The measurements were performed using an Agilent power spectrum analyzer N9030A in the Institute of Microelectronics of the Chinese Academy of Sciences. A three-needle probe ground-signal-ground (GSG) was adopted as the output of the high frequency signal. The total dc current consumption of the VCO is 18 mA with a supply voltage of $-6$ V. A high supply voltage is provided to obtain a high voltage swing, which is helpful to improve the phase noise performance.

Figure 4 illustrates the output spectrum of the VCO with a control voltage of $-4$ V. The maximum output power of the VCO is -7.34 dBm at the output GSG pad. The oscillation frequency variation as a function of control voltage sweep is plotted in Figure 5. The tuning frequency is varied from 28.695 to 28.312 GHz with a control voltage from $-5.5$ to 0~V. The simulated and measured phase noise characteristics of the differential $\pi$-feedback VCO are respectively depicted in Figures 6(a) and 6(b). As shown in Figure 6(b), a phase noise of $-96.47$~dBc/Hz at a 1 MHz offset is observed at the 28.633~GHz oscillation frequency. It seems that the phase noise performance is poorer than the simulated result of $-103.9$~dBc/Hz at 1 MHz. One possible reason is that all the passive elements and wirings were modeled by 2.5-D electromagnetic simulations of the momentum EM simulator in Agilent's advanced design system (ADS), in which its algorithm is not precise enough. Another reason may be that the substrate in the library is not entirely the same as our samples, so it may result in the difference between the simulation and measurement. Besides, some parasitic effects may be produced when the probe is in contact with the tested chip, which was not considered in the simulation. The parasitic effects, including parasitic capacitors and inductors, will bring in additional losses, which will reduce the output power of the VCO. According to Equation (3), the phase noise of the tested VCO increases with the reducing of the output power $P_{\rm sig}$. Based on the above analysis, the existence of the parasitic effects will bring down the phase noise performance.

To improve the simulation accuracy of the VCO, simulation software with high algorithm accuracy, such as fast-cap and Fast-Henry, could be utilized to get a more precise simulation of the capacitors and inductors. Meanwhile, some capacitors and inductors should be introduced between the output and the termination load to represent the parasitic effects produced by the contact between the probe and the tested chip. In addition, the target should be designed to be higher than the expected value to leave a certain margin for the difference between the simulation and the measurement result. Thus the final performance will still be able to meet the demand with the existence of the parasitic effects. To enhance the performance of the VCO, more interconnection layers can be used to shorten the critical feedback path and signal paths, which can further reduce the parasitic effects. Table 1 lists the performance of several previously reported VCOs. It demonstrates that the proposed VCO has superior phase noise performance compared with the other reported results.

4. Conclusion

The design and fabrication of a Ka-band $\pi$-feedback VCO using 1-$\mu$m GaAs HBT technology have been presented in this paper. Low phase noise performance has been realized by using a balanced CE configuration with a novel $\pi$-feedback network. This topology reduces the load of the tank from the active devices and compensates for the 180$^\circ$ phase shift with a $\pi$-network. The measurement result shows that a phase noise of $-96.47$ dBc/Hz at the 1 MHz offset is obtained. The dc current consumption is 18 mA with a supply voltage of $-6$~V. The maximum output power is $-7.34$ dBm. Furthermore, the GaAs HBT device with its excellent ability to handle higher frequencies than the Si-based device is a preferred technology to implement wireless applications for the military and civil service.