J. Semicond. > 2015, Volume 36 > Issue 6 > 065005
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SEMICONDUCTOR INTEGRATED CIRCUITS

A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator

Tao Yang, Yu Jiang, Shengyou Liu, Guiliang Guo and Yuepeng Yan

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 Corresponding author: Tao Yang, Email: yangtao@ime.ac.cn

DOI: 10.1088/1674-4926/36/6/065005

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Abstract: This paper presents a low power, high sensitivity Gaussian frequency shift keying (GFSK) demodulator with a flexible frequency offset canceling method for wireless networks for industrial automation process automation (WIA-PA) transceiver fabricated in 0.18 μm CMOS technology. The receiver uses a low-IF (1.5 MHz) architecture, and the transmitter uses a sigma delta PLL based modulation with Gaussian low-pass filter for low power consumption. The active area of the demodulator is 0.14 mm2. Measurement results show that the proposed demodulator operates without harmonic distortion, deals with ± 180 kHz frequency offset, needs SNR only 18.5 dB at 0.1% bit-error rate (BER), and consumes no more than 0.26 mA from a 1.8 V power supply.

Key words: GFSK, demodulator, DLL, charge pump, PFD, VCDL



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Fig. 1.  Block diagram of a typical low-IF wireless receiver.

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Fig. 2.  Block diagram of the modified DLL-based GFSK demodulator including the frequency offset canceller.

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Fig. 3.  Operation of the modified DLL-based GFSK demodulator with offset cancellation.

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Fig. 4.  Schematic of detect-boosting PFD associated with start-controlled circuit.

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Fig. 5.  (a) Timing diagram of modified start{\_}controlled circuit. (b) Timing diagram of proposed detect-boosting PFD.

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Fig. 6.  Circuit diagram of the self-calibration charge-pump circuit.

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Fig. 7.  The proposed VCDL circuit with symmetric load circuit.

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Fig. 8.  Results of simulation model for time delay in terms of a control voltage $V_{\rm c}$.

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Fig. 9.  Chip microphotograph of the proposed GFSK demodulator.

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Fig. 10.  (a) PN9 modulated GFSK signal spectrum with $P=-60$ dBm, $\Delta f$ $=$ 200 kHz, and symbol rate $=$ 250 KSPS. (b) PN9 $-60$ dBm demodulator output.

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Fig. 11.  Measured BER versus SNR.

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Table 1.   Comparison of different GFSK demodulators

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    Received: 12 December 2014 Revised: Online: Published: 01 June 2015

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      Article Navigation >  Journal of Semiconductors  > 2015  >  36(6): 065005
      Tao Yang, Yu Jiang, Shengyou Liu, Guiliang Guo, Yuepeng Yan. A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator[J]. Journal of Semiconductors, 2015, 36(6): 065005. doi: 10.1088/1674-4926/36/6/065005 ****T Yang, Y Jiang, S Y Liu, G L Guo, Y P Yan. A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator[J]. J. Semicond., 2015, 36(6): 065005. doi: 10.1088/1674-4926/36/6/065005.
      Citation:
      Tao Yang, Yu Jiang, Shengyou Liu, Guiliang Guo, Yuepeng Yan. A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator[J]. Journal of Semiconductors, 2015, 36(6): 065005. doi: 10.1088/1674-4926/36/6/065005 ****
      T Yang, Y Jiang, S Y Liu, G L Guo, Y P Yan. A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator[J]. J. Semicond., 2015, 36(6): 065005. doi: 10.1088/1674-4926/36/6/065005.
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      A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator

      DOI: 10.1088/1674-4926/36/6/065005

      • Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

      Funds:

      Project supported by the National High Technology Research and Development Program of China (No. 2011AA040102).

      More Information
      • Corresponding author: Email: yangtao@ime.ac.cn
      • Received Date: 2014-12-12
      • Accepted Date: 2014-12-31
      • Published Date: 2015-01-25

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