1. Introduction

WIA-PA based on IEEE 802.15.4-2006^{[1, 2]},is proposed by China for wireless industrial applications. Recently,470-510 MHz ISM band was released to the WIA-PA applications,for low-cost short-range applications. It employs GFSK modulation scheme and low-IF receiver architecture,so that the transceiver can be immune to low frequency problems such as flicker noise and DC offset. As shown in Figure 1,in the RF front-end,the complex channel-select filter down-converts RF signal to IF domain,rejects the image,and selects the desired channel. The limiter adjusts the amplitude of received IF signals to achieve a constant envelope. Therefore,it removes the AM noise and retains the frequency information. Linear amplification function is not needed because little information is on the amplitude with respect to the GFSK scheme.

Compared with the VGA scheme,the RSSI block can handle a larger dynamic range while consuming less power and holding a simple circuitry. Normally,the RSSI represents the received signal power level and adjusts the gain of the RF front-end channel by the help of the baseband signal processor. Furthermore,the RSSI is used for localization in wireless sensor network systems^{[3, 4]}. Resolution of the measured RSSI value affects the performance of the wireless communication system. Therefore,the RSSI circuit needs to be thoroughly analyzed and carefully designed^{[5, 6, 7]}. Former works quantitatively derived the RSSI value but seldom considered the rectifier,low-pass filter (LPF)^[8] and rail-to-rail buffer^{[9, 10]}. These three blocks are essentially the critical building blocks of an RSSI circuit besides the limiter circuit and they should be taken into consideration carefully.

The RSSI circuit should meet a number of requirements,including low cost,low power,wide dynamic range (DR),high detection sensitivity and robust to PVT variations. Successive-detection architecture based on piecewise-linear approximation is adopted for realizing the logarithmic amplifier because the wide dynamic variation of the received signal can be represented within a limited indication range^{[11, 12, 13, 14, 15, 16]}. It is essentially composed of several full-wave rectifiers and a low-pass filter,which are in combination with the proposed limiting amplifier circuits.

This paper is organized as follows. Section 2 analyzes the performance of RSSI theoretically and discusses the proposed RSSI architecture design. Section 3 describes circuit designs focusing on the proposed limiting amplifier,rectifier,LPF and rail-to-rail buffer circuits. The measurement results are shown in Section 4 and conclusions are given in Section 5.

2. Architecture of the proposed RSSI

2.1 Theoretical analysis of RSSI

Quantitative analyses of the RSSI circuit based on the successive detection architecture that the line in dB relationship between the narrow band modulated input signal level and the output voltage as well as the maximum deviation from an ideal logarithmic function^{[5, 6, 7]} with a reasonable dynamic range and detection sensitivity are described completely. Successive-detection architecture has commonly been used because it is more accurate than the alternative structures based on PN-junctions. Also,a PN-junction-based logarithm amplifier has limited dynamic range and strong temperature dependency^[13]. Meanwhile,some nonidealities such as AM-to-PM conversion^[17],the output amplitude of limiting amplifier and common voltage effects,and so on,are also going to be considered.

The actual RSSI value is obtained by summing the output voltages from each branch in the successive detection architecture.

$\begin{equation} {\rm RSSI}(V_{\rm I})=\sum^N_{i=0}x_{\rm i}(V_{\rm I}), \end{equation}$

(1)

where $N$ is the number of the limiter and $x_{\rm i}(V_{\rm I})$ is the output voltage of ($i+$1)th branch comprising of the rectifier and the LPF and it is the DC level of the saturated and rectified signal of $A^{i}v_{\rm I}(t)$ where $i=$ 0,1,$\cdots$,$N$,$v_{\rm I}(t)$ is the input signal in time domain. So $x_{\rm i}(V_{\rm I})$ has two different ways depending on the magnitude of $A^{i}V_{\rm I}$. Figure 2(a) shows $A^{i}V_{\rm I}$ ＜ $V_{\rm s}$ and Figure 2(b) shows $A^{i}V_{\rm I}$ $\geqslant$ $V_{\rm s}$ for $i=$ 0,1,$\cdots$,$N$. $V_{\rm s}$ is the saturated output voltage level,and $A$ is the voltage gain of each limiting amplifier. For the continuous phase frequency modulated signal,$x_{\rm i}(V_{\rm I})$ does not depend on the modulated frequency but only on the amplitude $V_{\rm I}$,which means that the derived equations of the RSSI value,max error and dynamic range can be used for the frequency modulated signal such as GFSK. Only a narrow band phase-modulated signal has the same way that the RSSI value also depends on $V_{\rm I}$.

$\begin{equation} \begin{split} {\rm RSSI}(V_{\rm I}) {} =\sum^k_{i=0}x_i(V_{\rm I})|A^iV_{\rm I} ＜ V_{\rm s}+\sum^N_{i=k+1}x_i(V_{\rm I})|A^iV_{\rm I} \leqslant V_{\rm S} \\ =\sum^k_{i=0} \frac{2V_{\rm I}}{\pi}A^i+\sum^N_{i=k+1} \left\{ \frac{2V_{\rm I}}{\pi}A^i\left[1- \right.\right. \\ \left.\left. \sqrt{1-\left(\frac{V_{\rm s}}{A^iV_{\rm I}} \right)} \right]+\left[1-\frac{2}{\pi}\sin^{-1}\left(\frac{V_{\rm s}}{A^iV_{\rm I}}\right)\right]V_{\rm s} \right\}. \end{split} \end{equation}$

(2)

To approximate the ideal logarithmic function accurately,the RSSI value should increase linearly as the amplitude of the input signal $V_{\rm I}$ grows exponentially^[6].

$\begin{equation} {\rm RSSI}\left( \frac{V_{\rm s}}{A^k}\right) -{\rm RSSI}\left( \frac{V_{\rm s}}{A^{k+1}}\right)\approx V_{\rm s},\quad 1 \leqslant k \leqslant N-2. \end{equation}$

(3)

From Equation (3),the RSSI value adds $V_{\rm s}$ every time as $V_{\rm I}$ is increased $A$ times. So the ideal logarithmic RSSI curve can be represented by

$\begin{equation} \begin{split} {\rm RSSI}_{\rm ideal} (V_{\rm I}) {} =V_{\rm s} \log_{\rm A} \left( \frac{V_{\rm I}}{V_{\rm S}} \right) +NV_{\rm S},\frac{V_{\rm S}}{A^{k+1}} \leqslant V_{\rm I} ＜ \frac{V_{\rm S}}{A^k}, \\ 1 \leqslant k \leqslant N-1. \end{split} \end{equation}$

(4)

From Equations (2) and (3),the piece-wise linear RSSI curve can be represented by

$\begin{equation} \begin{split} {\rm RSSI}_{\rm approx} (V_{\rm I}) {} =\frac{A^{k+1}}{A-1} \left(V_{\rm I} \frac{V_{\rm S}}{A^{k+1}} \right) +(N-k-1)V_{\rm S}, \\ \frac{V_{\rm S}}{A^{k+1}} \leqslant V_{\rm I} ＜ \frac{V_{\rm S}}{A^k},\quad 1 \leqslant k \leqslant N-1. \end{split} \end{equation}$

(5)

As shown in Equation (5),besides $V_{\rm I}$,the RSSI value relates to the single-stage voltage gain and the saturated output voltage level of each limiting amplifier cell.

From Equations (4) and (5),the maximum RSSI error can be estimated when

$\begin{equation} \frac{\partial |{\rm RSSI}_{\rm ideal}(V_{\rm I})-{\rm RSSI}_{\rm approx}(V_{\rm I})|}{\partial V_{\rm I}}=0. \end{equation}$

(6)

From Equations (4)-(6),the maximum RSSI error in dB mode can be obtained when

$\begin{equation} V_{\rm I}=\frac{V_{\rm S}(A-1)}{A^{k+1}\ln A}. \end{equation}$

(7)

Substitute Equation (7) in $|{\rm RSSI}_{\rm ideal}(V_{\rm I})-{\rm RSSI}_{\rm approx}(V_{\rm I})|$,the maximum RSSI error in dB mode can be described as

$\begin{equation} {\rm RSSI}_{\rm error,\,max,\,dB}=10 \ln A \times \left(\frac{\ln \dfrac{A-1}{\ln A} -1}{\ln A}+\frac{1}{A-1} \right). \end{equation}$

(8)

As shown in Equation (8),the RSSI error depends only on the single-stage voltage gain.

The RSSI dynamic range in dB mode can be obtained^[7]

$\begin{equation} \begin{split} {\rm RSSI}_{\rm DR,\,dB} {} =20 \log_{10} A \times \left\{ N+1\right. \\ \left. -\log_{\rm A} \left[ \frac{2}{A}\left( \frac{20\log_{10}A}{\pi} \right)^2 \right] \right\}. \end{split} \end{equation}$

(9)

As shown in Equation (9),the RSSI dynamic range is determined by both the single stage voltage gain and the number of stages of a limiter.

The RSSI has a trade-off between dynamic range and detection sensitivity. The detection sensitivity can be obtained as

$\begin{equation} {\rm RSSI}_{\rm DS}=\frac{{\rm RSSI}_{\rm approx,\,max}-{\rm RSSI}_{\rm approx,\,min}}{{\rm RSSI}_{\rm DR,\,dB}}. \end{equation}$

(10)

The RSSI total power equals the sum of the single power of the limiter which is scalable to the power of the GBW,in other words,it is constrained by the dynamic range,maximum detection error and the bandwidth required by the systems.

$\begin{equation} \begin{split} {\rm RSSI}_{\rm power,total} {} =NP_{\rm s} \propto N (A \times B_{\rm s})^2 \\ =N \left( A_{\rm t}^{\frac{1}{N}}-\frac{B_{\rm t}}{\sqrt{2^{\frac{1}{N}}-1}} \right)^2, \end{split} \end{equation}$

(11)

where $B_{\rm s}$,$B_{\rm t}$ and $A_{\rm t}$ are the single stage bandwidth,the total bandwidth and the total gain of limiting amplifier respectively. The single stage gain $A$,bandwidth $B_{\rm s}$ and noise are completely dependent on the circuit architecture which will be discussed and optimized to kill the PVT effects in the circuit analysis and design section. Once the overall gain $A_{\rm t}$ and bandwidth $B_{\rm t}$ of the limiting amplifier are specified,the voltage gain of each stage $A$ is obviously reduced as the cascading number of the stage increases. However,this introduces more poles since the number of gain stage increases. The bandwidth of each stage $B_{\rm s}$ therefore has to be increased in order to maintain an overall bandwidth.

The effects of nonidealities are discussed below,which includes the $A$ and $V_{\rm s}$ deviation and mismatch existing between different stages of the limiting amplifier,the residual DC offset with a DC offset cancellation method,the AM-to-PM conversion,the common mode voltage variation and the overall noise.

From Equation (5),the deviation of RSSI value due to $A$ and $V_{\rm s}$ can be obtained by differentiating them severally. For simplicity and without of loss of generality,Equation (4) is chosen to analyze the variation.

$begin{equation} \begin{split} {} {\rm RSSI}_{\rm deviation} =\frac{\partial {\rm RSSI}_{\rm ideal} (V_{\rm I})}{\partial A}\times \upDelta A+\frac{\partial {\rm ideal}_{\rm ideal} (V_{\rm I})}{\partial V_{\rm s}}\times \upDelta V_{\rm s} \\ =V_{\rm s}\frac{\log_{\rm A} \left( \dfrac{V_{\rm s}}{V_{\rm I}}\right)}{\ln A}\times \frac{\upDelta A}{A}+V_{\rm s} \left[ N+\log_{\rm A} \left(\frac{V_{\rm I}}{V_{\rm s}} \right)-\frac{1}{\ln A} \right] \\ \quad \times \frac{\upDelta V_{\rm s}}{V_{\rm s}}. \end{split} \end{equation}$

(12)

From Equation (12),while $V_{\rm I}$ decreases,the deviation of the RSSI value due to $A$ variation increases,and while $V_{\rm I}$ increases,the deviation of the RSSI value due to $V_{\rm s}$ variation decreases.

The transfer characteristic of each limiting amplifier will be affected if $A$ and $V_{\rm s}$ mismatch exists between different stages. According to the successive detection architecture,the RSSI value is obtained by summing all the output voltage of each branch. So $A$ and $V_{\rm s}$ can be approached using 1st order approximation as

$\begin{equation} \Pi^i_{k=0}A_k=A^i \left( 1+\frac{\sum^i_{k=0}\upDelta A_k}{A} \right), \end{equation}$

(13)

$\begin{equation} V_{\rm s,i}=V_{\rm s}+\upDelta V_{\rm s,i}=V_{\rm s} \left(1+\frac{\upDelta V_{\rm s,i}}{V_{\rm s}} \right). \end{equation}$

(14)

Meanwhile,the residual DC offset and the input noise limits the minimum input signal level. In other words,it may contaminate the dynamic range of RSSI$_{\rm DS}$. $V_{\rm offset}$ exists regardless of the signal amplitude,so the left part of RSSI value expression in Equation (2) can be modified for $V_{\rm I} \geqslant V_{\rm offset}$.

$\begin{equation} \begin{split} {} {\rm RSSI}(V_{\rm I}) =\frac{1}{T}\int^T_0|A^{\rm i}v_{\rm I}(t)+A^{\rm i}v_{\rm offset}(t)|{\rm d}t \\ =\frac{2}{\pi} A^{\rm i}V_{\rm I} \sqrt{1-\left(\frac{V_{\rm offset}}{V_{\rm I}} \right)^2}+\frac{2}{\pi}V_{\rm offset}\sin^{-1}\left(\frac{V_{\rm offset}}{V_{\rm I}} \right). \end{split} \end{equation}$

(15)

The common mode voltage variation can be equivalent to DC offset.

The input-referred noise per unit bandwidth will be represented according to the proposed limiting amplifier next section. It also limits the minimum input signal power level.

There is another practical issue,which is the AM-to-PM conversion. This output phase modulation caused by input amplitude variation is mainly due to different delays of bandwidth-limited gain cell for different input levels. This phase variation will degrade the RSSI sensitivity. The phase variation can be expressed in terms of input signal band $f_{\rm in}$ and total gain cell bandwidth as

$\begin{equation} \upDelta \phi=17.6^\circ \frac{f_{\rm in}}{B_{\rm t}} N. \end{equation}$

(16)

Shown in Figure 3 are linear error and power consumption versus gain stage numbers,which are obtained from Equations (8) and (11). Seven stages are the optimal number with all of 0.5 dB RSSI linear error and less power consumption. From Equation (16),in order to reduce the phase variation,B_t=$10$f_{\rm in}$with$f_{\rm in}$ = 1.5 MHz. From Equations (12) and (13),A ≥ 12 dB is evaluated to reduce the effects of A variation to total gain. From Equation (9),RSSI dynamic range RSSI$_{\rm DR,dB}$ can be calculated to be about 80 dB. From Equations (12) and (14),the rail-to-rail output circuit is used to reduce the $V_{\rm s}$ variation. From Equation (15),an optimal input signal level should be twice the input-referred DC offset with the help of powerful DC-offset loop and noise-cancelled mechanics. Once the limiting architecture is proposed with the $V_{\rm s}$,the detection sensitivity RSSI$_{\rm DS}$ is chosen about 12 mV/dB. The above calculated and simulated results are used as the initial parameters to reduce the designing iterative process of RSSI.

2.2.Implementation of proposed RSSI

As shown in Figure 4,a general RSSI circuit based on the successive detection architecture consists of the cascade of N limiting amplifier cell,of which voltage gain is $A$ and saturated output voltage level is $V_{\rm s}$,plus $N+$ 1 rectifiers,an LPF and a rail-to-rail buffer.

Two-path I/Q RSSI structure is adopted to reduce the output voltage glitch^[19] and the chip area rapidly. The residual harmonic components are sufficiently attenuated by the small on-chip RC filter. In traditional single path RSSI,the output current of the full-wave current rectifier includes the second-order harmonic component as shown in Equation (17). Therefore,large capacitance is needed to filter the output voltage ripple. According to Equation (18),the second-order harmonic component of the output current can be ideally cancelled.

$\begin{equation} I_{\rm Total-1p}=\sin^2(\omega t)=\frac{1}{2}-\frac{1}{2}\cos (2\omega t), \end{equation}$

(17)

$\begin{equation} I_{\rm Total-2p}=\sin^2(\omega t)+\cos^2 (\omega t)=1. \end{equation}$

(18)

The limiting amplifier is basically an amplifier chain that enlarges different magnitudes of input signal into saturation. This amplifier chain has to provide a small signal gain of at least 80 dB in order to cover the required input dynamic range in WIA-PA application. Meanwhile,it has to yield a high-pass function with the help of DC extraction,DCOC and CMFB circuits at each stage to alleviate the dc offset due to mismatch,variation and residue of DC value maximally. The designed upper bandwidth is ten times that of the IF 1.5-MHz in order to reduce the AM-PM conversion effect,while the lower band is set at 100 kHz which causes little influence on data band near IF. Each section of the rectifier is obtained by rectifying each gain cell output of the limiting amplifier. The sum of the output of the cascaded section with a low pass filter is used to measure the signal strength.

3. Circuit analysis and design

3.1.Limiting amplifier

A pseudo differential structure always suffers from path mismatch. It is more severe in a high gain device,because the accumulated offset in the front stage may smear the input small signal and generate a wrong saturated output voltage in the following gain stage^[14],and in order to avoid driving the diode load into velocity saturation region,the proposed circuit employs cascaded diode connected transistors load^[20]. To avoid the offset being amplified,a feed forward type offset cancellation method^[21] is applied as shown in Figure 5. The offset in the previous stage which is extracted by an RC network will be subtracted from the input signal by the cross-connected pair M11 and M12 in the current stage. The frequency response of this gain stage with the help of the small signal analysis can be derived as

$\begin{equation} \begin{split} A_{\rm v} ={} A_{\rm DC} \times H_{\rm BPF}(s)=\frac{g_{\rm m1,\,2}}{g_{\rm m6,\,9}+g_{\rm m7,\,10}} \\[2mm] \times \frac{sR_{\rm lpf}C_{\rm lpf}}{(sR_{\rm lpf}C_{\rm lpf}+1)(s\frac{C_{\rm PO}}{g_{\rm m6,\,9}+g_{\rm m7,\,10}}+1)}, \end{split} \end{equation}$

(19)

where $C_{\rm PO}$ represents the parasitic capacitance of the output node,$g_{\rm m1,\,2}$,$g_{\rm m6,\,9}$ and $g_{\rm m7,\,10}$ are the trans-conductance of the transistor M1,M2,M6,M9 and M7,M10. $R_{\rm lpf}$,$C_{\rm lpf}$ are the components of the DC abstract circuit.

The pseudo-differential structure has poor common mode behavior. The output common level fluctuation will be reduced by a factor of the loop gain with the help of a common mode feedback (CMFB) circuit. Directly applying the DC information from the previous extraction circuit as the output common mode voltage does not cause additional parasitic capacitance at the output node. Moreover,no extra power will be consumed. The sensed common mode voltage is compared with a reference voltage $V_{\rm cm}$. The error signal is amplified and fed back to the bias circuit M13 and M14 of the gain stage^[14].

From Figure 5,the input-referred noise per unit bandwidth can be represented as

$\begin{equation} V_{\rm v}^2=8kT\gamma \frac{(g_{\rm m1}+g_{\rm m3}+g_{\rm m5}+g_{\rm m6}+g_{\rm m7})(g_{\rm m6}+g_{\rm m7})^4}{(g_{\rm m1}g_{\rm m6}g_{\rm m7})^2}. \end{equation}$

(20)

From Equation (20),increasing $g_{\rm m1}$ can reduce noise effectively. The flick noise can be ignored with the LPF circuit.

The simulation result of the limiter is shown in Figure 6. The frequency response of the limiter with forward offset cancellation circuit shows the band-pass function with about 88~dB total gain and 12 MHz bandwidth.

3.2 Rectifier

As shown in Figure 7,the proposed output current programmable full-wave rectifier consists of doubled unbalanced source-coupled pairs with the cross-coupled input stage and parallel-connected output stage. The proposed full-wave rectifier is more precise and smooth compared to the traditional full-wave rectifier^[11],which is proved by the measurement results. As shown in Equation (21),the output current of the full-wave current rectifier is a function of the reference bias current and the input signal^[22]. The programmable reference bias current controls the tradeoff between the dynamic range and detection sensitivity of RSSI. Here,the reference (1x) current is compensated with a replica biasing circuit for PVT variations.

$\begin{equation} \begin{split} {} V_{\rm RSSI} =(I_{\rm l}+I_{\rm Q})\times R_{\rm pull{\_}up} =(x_{\rm i}(V_{\rm II})+x_{\rm q}(V_{\rm IQ}))\times R_{\rm pull{\_}up} \\[2mm] =[f(V_{\rm II}+A_{\rm t} \times I_{\rm programblebias})+f(V_{\rm IQ}+A_{\rm t} \times I_{\rm programblebias})] \\[2mm] \quad \times R_{\rm pull{\_}up}, \end{split} \end{equation}$

(21)

where $R_{\rm pull{\_}up}$ is the PULL UP register as shown in Figure~8.

3.3 The LPF and buffer

3.3.1   Self-adaptive bias

Besides the programmable reference (1x) current mirror,the transfer curve of the RSSI keeps stable under various PVT variations further with the help of the self-adaptive bias circuit by reducing the effects of the $R_{\rm pull{\_}up}$ of the LPF which is shown at the top right corner of Figure 7. The programmable IBIAS will be changed with the $V_{\rm ref}$ pad. So Equation (21) can be modified as

$\begin{equation} \begin{split} V_{\rm RSSI} {} = \left[ f\left(V_{\rm II}+A_{\rm t} \times \frac{V_{\rm DD}-V_{\rm ref}}{R_{\rm pull{\_}up}}\right)\right. \\[2mm] \quad \left. +f\left( V_{\rm IQ}+A_{\rm t} \times \frac{V_{\rm DD}-V_{\rm ref}}{R_{\rm pull{\_}up}} \right) \right] \times R_{\rm pull{\_}up} \\[2mm] =[f(V_{\rm II}+A_{\rm t} \times (V_{\rm DD}-V_{\rm ref})) \\[2mm] \quad +f(V_{\rm IQ}+A_{\rm t} \times (V_{\rm DD}-V_{\rm ref}))]. \end{split} \end{equation}$

(22)

3.3.2   LPF

The bandwidth of the LPF should be much lower than the frequency of the input signal and the stop band attenuation is larger to reduce ripples on the real RSSI value. As shown in Figure 8,a passive RC filter with two poles is provided^[8]. The LPF and rectifier comprises the summer which should have the same weighting factor for each branch.

3.3.3   Rail-to-rail buffer

Usually,the RSSI output value is used as the input of ADC which has large capacitance at the input node. Meanwhile,the RSSI value has a wide range and in order not to sacrifice the dynamic range of RSSI,as shown in Figure 8,a constant-gm op-amp with rail-to-rail input and output-stage-based buffer is added between them.

As shown in Figure 8,the constant-gm input stage of the proposed two-stage op-amp is based on the configuration that consists of four MOSFETS M2,M3,M6,M7 as dummy differential pairs to select a different differential pair M1,M4,M5,M8 as input pair,according to the different common-mode voltage $V_{\rm B}$^[10] which can range from $V_{\rm SS}$ to $V_{\rm DD}$ for the rail-to-rail input stage. To obtain the constant $g_{\rm m}$,$I_{\rm n}=I_{\rm p}$,$\frac{\mu_{\rm n} C_{\rm ox}W}{L}=\frac{\mu C_{\rm ox}W}{L}$. However,when the difference between the $V_{\rm B}$ and the common mode voltage $V_{\rm cm}$ is small,the variation will be raised. So,the sizes of the dummy MODFETS can be set three times greater than the corresponding differential input pairs. In addition,a class-AB output stage is employed to obtain a wide output range^[9]. The purpose of the class-AB control circuit is to prevent the output transistors or any other transistors in the circuit from switching off,as this would deteriorate the step response of the stage^[10]. To reduce noise and offset,the class-AB driver circuit M19,M20 which biased by the M22,M25 has been incorporated in the folded-cascaded summing circuit M11-M18 of the rail-to-rail input stage. The amplifier is compensated using two split miller capacitors between the output stage M27,M28 and current mirrors.

The simulation result shows that the proposed op-amp has a constant $g_{\rm m}$ within 4.5{\%} and consumes all of 200 $\mu$A with the real ADC load.

4. Measured results

Based on the structure shown in Figure 4,this proposed high resolution,process/temperature variation tolerant RSSI is fabricated in the TSMC 0.18 $\mu$m 1P6M RF CMOS technology and draws no more than 2 mA from a 1.8 V power supply. The chip microphotograph of the RSSI is shown in Figure 9. Its active area is 0.24 mm$^{2}$.

Figures 10(a)-10(c) display the RSSI value and its maximum error in dB mode with the dynamic range of input signal power from $-70$ to 0 dBm (to 50 $\upOmega )$ at $+27$,$-40$ and $+85$~$\du$ respectively. Figure 10(d) compares the process variation in dB mode of different chips on the same wafer at the same temperature.

Depending on the proposed RSSI circuits and rational modified circuits,such as self-adaptive bias and 1 : 1 programmable current mirrors,the proposed RSSI exhibits good temperature-independence and excellent robustness against process variation characteristics which matches well with the theoretical analysis.

As shown in Figures 10(a),10(b),10(c),the maximum errors in dB mode are within ($-0.5$ dB,$+0.5$ dB) at 27 $\du$,within ($+1.2$ dB,$+1.3$ dB) at $+85$ $\du$ and within ($-1.5$ dB,$-12.5$ dB) at $-40$ $\du$ respectively. So,total RSSI temperature error is within ($-1.5$ dB,$+1.3$ dB) from $-40$ to $+85$ $\du$ with 70 dB dynamic range. Figure 10(d) shows the process variation error is within ($-0.25$ dB,$+0.25$ dB) from $-70$ to 0 dBm. The corresponding output voltage is from 0.81 to 1.657 V and the RSSI slope is 12.1 mV/dB while consuming all of 2 mA from a 1.8 V power supply.

The comparison of different RSSIs performance is shown in Table 1. According to the spec of WIA-PA,the proposed RSSI has the optimization results.

5. Conclusions

In this paper,a high resolution,process/temperature variation tolerant received signal strength indicator (RSSI) for WIA-PA receiver is proposed. To achieve robust performance under 1.8 V operation by a standard TSMC 0.18 $\mu$m 1P6M RF CMOS technology,a novel RSSI circuit based on the successive detection I/Q architecture is proposed with the help of the theoretical analysis of the value level,dynamic range,detection sensitivity,maximum variation error and non-ideal effects of RSSI including the LPF. In order to improve the performance of the RSSI,a novel gain stage with feed-forward offset cancellation and common mode feedback mechanism is proposed and followed by a doubled unbalanced source-coupled pairs rectifier which is finer than a traditional one. Considering the characteristic of RSSI and usage as input of followed ADC which has a large capacitor at the input node,a constant-gm rail-to-rail op-amp buffer is proposed at last. Depending on the proposed RSSI circuits and rational modified circuits such as self-adaptive bias and 1 : 1 programmable current mirrors,etc.,the proposed RSSI exhibits good temperature-independence and excellent robustness against process variation characteristics. Measurement results show that the proposed RSSI has a dynamic range more than 70 dB and the maximum linearity error is within $\pm$0.5 dB for an input power from $-70$ to 0 dBm (dBm to 50 $\upOmega$),the corresponding output voltage is from 0.81 to 1.657 V and the RSSI slope is 12.1 mV/dB while consuming all of 2 mA from a 1.8 V power supply. Furthermore,by the help of the integrated compensation circuit,the proposed RSSI shows the temperature error within $\pm$1.5 dB from $-40$ to 85~$\du$,and process variation error within $\pm$0.25 dB.

Acknowledgment

The author wishes to thank Yan Yuepeng for valuable discussions on the system and block design of the RSSI. The author is also indebted to Li Jie,Liu Shengyou and Guo Guiliang for the support of the chip test.