1. Introduction

Development of infrared focal plane arrays (FPA) has led to the development of many kinds of imaging systems^[1]. The performance of FPAs depends on the capabilities of the IR detector and silicon read out circuit. The IR FPAs made of compound semiconductor detectors GaAs, InGaAs, InP, MCT, are electrically connected to silicon ROIC^[2] through indium bumps. The ROIC circuit consists of unit cells for charge integration and charge to voltage conversion, timing and control circuits, signal processing stage, pixel voltage multiplexers, and amplification stages as illustrated in Figure 1.

Performance of readout circuits is largely determined by unit cell performance. ROIC design for infrared photo-detector arrays requires a large charge handling capacity, cryogenic temperature operation, high injection efficiency, minimum detector bias voltage variations with minimum power dissipation and noise. Different constraints lead to a preference for different kinds of unit cells and an astute optimization is required for picking the best topology for the targeted specifications^[3]. A high performance readout circuit should provide a stable bias voltage in the range of 0 to 1.5 V to the detector to reduce detector noise^[4-8]. Low input impedance ROICs extract maximum photo current from the detector which results in high injection efficiency^{[2, 9, 11, 12, 14]}. A block diagram of the ROIC is shown in Figure 1. Since the detector is interfaced to the ROIC at node V_DE the photo-induced current flows into the source of transistor M1, which is closely matched to the current through M2, resulting in equal gate source voltage across these two transistors. This provides a constant interface voltage as shown in Figure 2. The current mirror topology makes it possible to provide the optimum bias voltage to the detector through a proper choice of V_{DET_ADJT}.

This paper proposes a high performance current mirroring integration (CMI) readout circuit. The circuit uses a combination of MOS and MIM capacitors for providing large in-pixel integration capacitance to support snapshot mode operation. In addition, it provides large charge handling capacity by rail-to-rail operation of high-swing cascode current mirrors. The proposed CMI circuit can be used not only with detectors which require stable zero detector bias but also those which operate at higher bias voltages such as quantum-dot infrared photo-detectors (QDIP). The proposed circuit uses a master clock and start pulse (SP) as digital inputs to the ROIC. All synchronizing signals required for ROIC operation are then generated on-chip by a timing and control unit.

2. Current mode injection ROIC

Figure 2 shows the basic schematic view of the CMI readout circuit. The circuit operation is as follows: Infrared radiation induces a current in IR detector. This current passes through M1 and M3. Current through M3 is mirrored to M4. Since M2 is in series with M4, the currents through M1 and M2 are equal. Consequently, the gate source voltages of M1 and M2 are equal. This forces the voltage at V_DE to be equal to that at V_{DET_ADJT}.

If the output resistance of M1 and M2 is infinite, the ratio of their currents will be given by $I_{\rm sd2}/I_{\rm sd1} = \frac{\left(W/L\right)_2}{\left(W/L\right)_1}$.

However, because of the finite output resistance of the transistors used in the circuit, the current mirroring ratio will deviate from its ideal relationship. The error factor introduced by the finite output impedance, for the matched current mirror pair is given by:

$\begin{equation} \epsilon \equiv \frac{I_{\rm sd2}}{I_{\rm sd1}} = \frac{1 + \lambda V_{\rm ds2}}{1 + \lambda V_{\rm ds1}}. \end{equation}$

(1)

For a simple current mirror with λ = 0.058 (which is typical for UMC 180 nm process for 3.3 V transistors), V_sd2 = 2 V, and V_sd1 = 1 V, ∈ = 1.055. So the error could be nearly 5.5%. Accordingly the mismatch in the mirrored current I₂ and hence the integrated value of ROIC current may have inaccuracy of 5.5%.

The detector bias in the CMI structure can be expressed as:

$\begin{equation} V_{\rm DET} = V_{\rm VDD} - V_{\rm DET\_{\rm ADJT}} + {\frac{\mu_{\rm n} (\frac{W}{L})_{\rm M2}}{\mu_{\rm p} (\frac{W}{L})_{\rm M3}}} {\Delta} V_{\rm thn} + {\Delta} V_{\rm thn}, \end{equation}$

(2)

where ${\Delta}V_{\rm thn}$ and ${\Delta}V_{\rm thp}$ are the mismatch values of the threshold voltages of the NMOS and PMOS transistors respectively. As ${\Delta}V_{\rm thn}$ and ${\Delta}V_{\rm thp}$ are very small within each pixel, the detector bias is very stable. The detector bias can be programmed to any value between 0 and 2.0 V by choosing appropriate V_{DET_ADJT} bias voltages. This is important because the detector bias voltage V_DET needs to be optimized as per detector requirements. A detector bias voltage close to zero is optimal for minimum dark current and detector noise. This mode of operation can be supported in CMI topology^{[13, 15]}.

The proposed CMI unit cell uses a modified current mirror to reduce the current mismatch error. It requires ten functional transistors. Additionally, two transistors are used as MOS capacitors for charge integration as shown in Figure 3. Cascaded PMOS transistors M1_1, M2_1 and M5_1 have been used to minimize mismatch within 1%. We have optimized the size of the integration capacitor through a parallel combination of metal insulator metal (MIM) and metal oxide semiconductor (MOS) capacitor to meet large charge handling capacity requirements within the constraint of 900 μm² pixel area. The rest of the circuit components are selected with minimum size to meet the pixel area specifications.

The proposed circuit uses a combination of cascode current mirror and a Wilson current mirror at the input stage. The Wilson current mirror (M1-M4) has been used to optimize the integrated voltage swing with minimum systematic error and improve linearity. Further, the cascode current mirror (M2_1, M2, M1, M1_1) improves accuracy. The source follower amplifier (M6-M7) further improves linearity and provides a buffer for signal integration and signal processing at the sample and hold circuit. In order to support snapshot mode, capacitor C₃ has been used on each ROIC pixel to sample and hold the pixel output value for the last frame, freeing up the rest of the circuit to perform the next integration. The integration capacitor and the permissible voltage swing determines the charge handling capacity of the circuit.

To meet the requirement of the large charge handling capacity within a limited pixel area is a challenge using modern CMOS processes due to their low swing. Figure 4 shows the relationship between charge handling capacity per unit voltage and the integration capacitor value. We have achieved large charge handling capability by using a suitable combination of MIM (28% of total capacitance) capacitor C₁ and MOS capacitors (M8 and M9). The MOS capacitors in general add nonlinearity due to their inherent structure. However, these provide nearly four times higher capacitance per unit area. The bias voltage and sizes of MIM and MOS capacitors have been optimized to give a large charge handling capacity with good linearity.

The pixel voltage is selected through row and column select signals. The output voltage of the selected pixel is then transferred to the column amplifier. Sequential selection of column amplifiers has been implemented using an analog multiplexer. A final buffer then drives the external load to provide the pixel information at the output. As shown in Figure 3, the RST switch resets all pixel values simultaneously to Bias1. The circuit uses a common source amplifier, which provides the driving current for charging and discharging the sampling capacitors C₃. The high value of C₃ capacitor is important for minimization of systematic pixel-to-pixel nonlinearity due to sequential readout. Optimal implementation of MOS capacitor C₃ with 1.8 V MOS capacitor helps in optimization of the sampling capacitor value. The 1.8 V MOS capacitor provides large capacitor/area ~ 8 fF/μm². The higher value of capacitor C₃ reduces pixel-to-pixel error. However, optimization of voltage swing is necessary for good linearity. Optimum swing has been selected from 0.3 to 1.6 V. This is because the highest voltage limit for C₃ capacitor is 1.8 V and the lower voltage level has been selected based on NMOS threshold voltage requirements. Pixel area distribution is shown in Figure 5.

The ROIC chip requires only two external digital signals: master clock (Clock) and start pulse (SP). These two signals are internally used for the implementation of timing and control relations of ROIC operation. Initially a low level on the start pulse initializes all the flip-flops synchronously. The output of ROIC pixels are sequentially read out through row and column control signals ROW<1...4> and COL<1...4>. The snapshot mode of integration has been controlled by the internally generated reset (RST) pulse. The RST signal resets all pixels simultaneously to a known bias voltage Bias1 before starting the next integration. ROIC pixels transfer integrated information to their S/H circuitry through the global transfer pulse (SH_TR) before the rising edge of global reset (RST) as shown in Figure 6. This timing relation is very important for the snapshot mode operation of ROIC. The column amplifier has been used for signal conditioning and provides an interface for analog signal transfer from ROIC pixels to the column bus. The high DC gain of the differential opamp (> 98 dB) provides high accuracy and its unity gain bandwidth of > 10 MHz is useful for providing better settling time at the highest frame rate of 5 kHz. Figure 6 shows the timing requirements of the ROIC.

Readout noise of ROIC is an important factor for infrared photo detectors. Under low illumination conditions, readout circuit noise is the dominant component of noise, while under high illumination conditions photon-shot noise dominates over other noise components. The magnitude of photon shot noise is proportional to the square root of the number of the signal electrons. Reset noise is due to reset of capacitors through MOS transistors inside the pixel circuit. It is also referred to as KTC noise. 1/f noise is contributed by column current sources and other column amplifiers. Noise performance of ROIC depends on the cumulative noise contribution of switching and random noise. Reset noise, multiplexer noise (due to non-ideal isolation and cross talk) and amplifier thermal noise are major factors affecting the noise performance. Johnson has provided a detailed noise analysis of ROICs for direct injection (DI)^[8], charge transfer and integration amplifier (CTIA)^[5] unit cells. In general, correlated double sampling (CDS) improves noise performance of the ROIC through subtraction of correlated noise. However the size of CDS capacitor is limited due to pixel area constraint and for small value of CDS capacitor, the noise equivalent voltage KT/C will be high. We have optimized ROIC noise through proper selection of transistor parameters and capacitor values.

The noise analysis has been verified through simulations to establish that due to pixel area limitation, the readout noise of ROIC is actually better without CDS.

3. Simulation performance

The induced detector current has been mirrored to the integration capacitance C₁ using the transistors M5_1 and M5. The selection of appropriate bias voltage (Bias1 = 1.2 V, Bias2 = 0.5 V) helps to achieve better linearity, along with large charge handling capacity. ROIC design has been simulated for various input currents at 2 kHz frame rate and the best fit line has been piloted from simulation results. The ROIC linearity in Figure 7 shows the simulation of ROIC linearity at 2.0 kHz frame rate and 5 MHz pixel rate. Full circuit post-layout ROIC simulation shows 99.9% linearity.

The ROIC parameters e.g. power, noise, charge-handling capacity, linearity, injection efficiency have also been simulated. The low input impedance of ROIC leads to high injection efficiency of 99.96% in simulation.

Dynamic noise simulation has been performed using pseudo steady state (PSS) analysis on a cadence spectre simulator. Figure 8 shows the input equivalent noise plot and calculated RMS noise for 8 MHz noise bandwidth. The ROIC performance depends on the performance of the buffer amplifier. Figure 9 shows the simulation result for buffer amplifier.

4. Experimental results

The test setup uses a 16-bit off-chip digitizer, EPLD for synchronization of ROIC output and digitizer clocks. Data acquisition system and lab-view based software has been used for digital data acquisition, linearity and noise measurement. The linearity of ROIC output has been plotted for different current inputs at 2 kHz frame rate and 5 MHz pixel rate. The integration current given to the input when multiplied with the frame time of 500 μs, provides the charge handling capacity. Linearity has been measured through a best fit regression line of integration current versus ROIC output voltage. All ROIC pixels have been routed to pads and a high precision source and measurement unit (SMU) was used for current measurement. The measured linearity of ROIC output voltage is 99.8% against its simulation value of 99.9%. The measurement inaccuracy of the test setup in the low current range of pA to nA is the reason for the slightly lower value of measured linearity versus the simulated value. The ROIC output for low input currents are also highlighted in Figure 10.

The ROIC noise has been measured through digitization of ROIC output through a 16 bit off-chip digitizer. The ROIC output data has been acquired through DAQ and noise has been computed and plotted in Figure 11.

The charge handling capacity has been measured using the linearity plot and we have achieved 15 Me at saturation as shown in Figure 10. The ROIC output saturates at 1.05 V and at average digital count of 20000 as shown in Figure 12. The ratio of charge handling capacity and average saturation counts provide ROIC conversion gain of 750 e^-/count. The average noise is 1.35 counts as shown in Figure 11. The equivalent average pixel noise has been computed as 1016 e^-, as measured at 5 MHz pixel rate. Experimental results show 99.9% linearity at 77 K compared to its value at room temperature of 99.8%.

The device can read currents from 10 pA to 12 nA range and its injection efficiency is 99.8%. The measurement test setup is shown in Figure 13. Detailed test results and comparison are given in Table 1. Figure 14 shows micrographic view of die.

5. Conclusion

The proposed ROIC circuit has low input impedance and it can extract maximum signal from a detector. The ROICs also support bias tunability through external voltage V_{DET_ADJT}. This bias voltage optimization can be used for the optimization of integrated spectral performance of infrared detectors. The average charge handling requirements of quantum dot infrared detector is 10 to 15 Me along with snapshot mode of integration. The ROIC design presented here meets both requirements along with high injection efficiency, linearity, with low noise and medium power. The circuit has been tested at room temperature and at cryogenic temperatures (77 K). The ROIC performance is highly stable at these temperatures.

Acknowledgement: The authors acknowledge with thanks the support extended by Shri Tapan Mishra, Director, Space Applications Centre, Ahmedabad, India. The authors also acknowledge with thanks the valuable suggestions made by Mr. Sandip Paul. We would like to thank Shri Saji A Kuriakose, Deputy Director, Sensor Development Area, Space Applications Centre, Ahmedabad, India for their support and VLSI Design Group, IIT-Bombay for insightful discussions on placement and routing of ROIC.