1. Introduction

III-V compound semiconductors have attracted a great deal of attention as a solution for the saturation of the current drive and the performance of Si complementary metal-oxide-semiconductors (CMOS) in the post scaling generation. In spite of this continuous demand for the MOSFET application,it has been a difficult challenge to obtain III-V metal-oxide-semiconductor (MOS) interfaces with a low interface trap density ($D_{\rm it})$ for a long time,because the unstable interface between the semiconductor and the high-$k$ dielectrics will generate the native oxide of the III-V semiconductor,which is the primary cause of the interface quality degrading; some other effects will also be induced,such as Fermi level pinning,frequency dispersion of $C$-$V$,and hysteresis characteristics of $C$-$V$^{[1, 2, 3, 4]}.

InGaAs has been regarded as a promising channel material due to their superior electron mobility and light electron mass^[5]. However,the inferior high-$k$/InGaAs interface still degrades the performance of InGaAs MOSFET. In order to improve the interface quality,InGaAs surface passivation has been widely used. Surface passivation can decrease the amount of dangling bonds,the native oxides,and the $D_{\rm it}$ values effectively. It has been reported that hydrogen cleaning and the post annealing process significantly remove the InGaAs (110) surface oxide and a high quality surface has been obtained after passivated by Si-H$_{x}$ groups; this passivation method has effectively reduced the dangling bonds on the (110) surface and created a passivating silicon control monolayer^[6]. Takagi et al. used a sulfur cleaning method in InGaAs samples with different In content and different orientation to research the S-passivation mechanism^[7]; they also reported that the electron cyclotron resonance (ECR) plasma nitridation of InGaAs surfaces forms interfacial nitride layers and reduces $D_{\rm it}$ of 2 $\times$ 10$^{11}$ cm$^{-2}$ eV$^{-1^[8]. Tang et al. have demonstrated the interface passivation layer (IPL) of nitrogen incorporation in Ga$_{2}$O$_{3}$(Gd$_{2}$O$_{3})$ (GGO) and NH$_{3}$-plasma nitrided GGO (GGON) to improve the interface quality with low interface-state density (1 $\times$ 10$^{12}$ cm$^{-2}$ eV$^{-1})$ and low gate leakage current (8.5 $\times$ 10$^{-6}$ A/cm$^{2})$ of the InGaAs MOS device^[9]. Zhu et al. have reported the GaAs MOS capacitors with HfTiO as the gate dielectric and Al$_{2}$O$_{3}$ as the interface passivation layer are fabricated and show low interface-state density (7.2 $\times$ 10$^{12}$~eV$^{-1}$ cm$^{-2})$,low leakage current density (3.6 $\times$ 10$^{-7}$ A/cm$^{2}$ at $V_{\rm g}$ $=$ 1 V) and good $C$-$V$ behavior^[10]. Among these methods,the techniques with N$_{2}$ plasma treatment and sulfur passivation have been widely used,but most of the studies used only one passivation method to research the mechanism^{[11, 12]},while fewer comparison studies between these two methods in the same experiment condition could be found.

In this paper,we compared the effect of nitridation and sulfur passivation for In$_{0.53}$Ga$_{0.47}$As on the Al/Al$_{2}$O$_{3}$/InGaAs MOS capacitors properties,and analyzed the advantages of the two passivation techniques respectively. We analyzed the effects of these two passivation methods on frequency dispersion,hysteresis characteristics,border traps,and the interface traps. The $C$-$V$ curves,$I$-$V$ curves and transmission electron microscope (TEM) images were also presented to characterize the interface properties.

2. Experimental methods

Figure 1 shows the schematic diagram of the fabricated In$_{0.53}$Ga$_{0.47}$As MOS capacitor. A Si-doped n-In$_{0.53}$Ga$_{0.47}$As layer with doping concentration of (5.5-9.5) $\times$ 10$^{16}$ cm$^{-3}$ was grown on heavily doped (100) InP substrate by the metal organic chemical vapor deposition method. The In$_{0.53}$Ga$_{0.47}$As surfaces were prepared by degreasing the wafers in acetone and alcohol for 5 min each,followed by a 1 min etch in 10% HCl and a 5 min etch in 25% NH$_{4}$OH. A 3 nm Al$_{2}$O$_{3}$ layer was grown by the Beneq atom layer deposition (ALD) system at 200° after pre-treating the surface of wafers. The deposition rate of Al$_{2}$O$_{3}$ on the In$_{0.53}$Ga$_{0.47}$As surface was 0.11 nm/cycle. Here,the following three pre-treating conditions were used: (1) deposited Al$_{2}$O$_{3}$ directly after etching by HCl and NH$_{4}$OH; (2) N$_{2}$ plasma treatment for 10 min: we used the plasma generator located in the ALD chamber to provide N$_{2}$ plasma,N$_{2}$ flow was 400 sccm,the carrier gas was also N$_{2}$ which had a flow of 100 sccm,and the RF power was 100 W; (3) only (NH$_{4})$$_{2}$S$_{x}$ treatment: 20% (NH$_{4})$$_{2}$S$_{x}$ for 15 min and DIW rinse for 30 s. Al metal gate contacts (about 200~nm) were made by e-beam evaporation to form the MOS capacitors with an area of 7.85 $\times$ 10$^{-5}$ cm$^{2}$. After post metallization annealing (PMA) at 300° in N$_{2}$ ambient for 30 s,the backside ohmic contacts were fabricated by Al evaporation^[13]. HP 4284 LCR and Agilent B1500 meters were used for the capacitance-voltage ($C$-$V$) and current-voltage ($I$-$V$) measurements. The cross-sectional TEM micrographs of three treated In$_{0.53}$Ga$_{0.47}$As wafers have also been presented.

3. Results and discussion

Figure 2 shows room temperature frequency dispersion with frequencies of 1 kHz,10 kHz,100 kHz,and 1 MHz of $C$-$V$ curves of no treatment,N$_{2}$ plasma treatment,and (NH$_{4})$$_{2}$S$_{x}$ treatment Al/Al$_{2}$O$_{3}$/In$_{0.53}$Ga$_{0.47}$As MOS capacitors. We obtained the corresponding flat-band voltage ($V_{\rm FB})$ at 0.22,-0.2,and 0.2 V from $C$-$V$ characteristics measured at 1 MHz,the $V_{\rm FB}$ values were extracted by calculating the flat-band capacitance ($C_{\rm FB})$ from the formula

where the $\varepsilon_{\rm s}$ is the electron constant of InGaAs,$\varepsilon_{\rm i}$ is the electron constant of Al$_{2}$O$_{3}$,$\varepsilon_{0}$ is the vacuum permittivity,$k$ is the Boltzmann constant,$T$ is the Kelvin temperature,$q$ is electron charge,$N_{\rm A}$ is the doping concentration and parameter ``$d$'' is the thickness of Al$_{2}$O$_{3}$. Compared with the ideal $C$-$V$ characteristic $V_{\rm FB}$ value (-0.35 V),all the samples show a positive shift of $V_{\rm FB}$,but the shift of the sample with N$_{2}$ plasma treatment is obviously smaller than the others,which indicates the existence of a negative charge in the dielectrics that can be neutralized by N$_{2}$ plasma. Compared with the capacitor without treatment (3.3% frequency dispersion),the samples with different passivation methods show small capacitance frequency dispersion (1.5% for N$_{2}$ plasma treatment and 0.8% for (NH$_{4})$$_{2}$S$_{x}$ treatment) near $V_{\rm FB}$,indicating that these two processing methods can effectively improve the interface properties and reduce the $D_{\rm it}$. By the N$_{2}$ plasma treatment,the present nitridation process could increase the amount of Ga-N bonds and reduce the amount of the Ga dangling bonds and As dimmers as well as III-V oxides at the MOS interfaces^[8]. By the (NH$_{4})$$_{2}$S$_{x}$ treatment,the sulfur cleaning can effectively remove the native oxides and prevent the surface from being oxidized^[7]. Moreover,the frequency dispersion of the passivated samples in the accumulation region (2.5% for N$_{2}$ plasma treatment and 3.3% for (NH$_{4})$$_{2}$S$_{x}$ treatment) is smaller than the un-passivated one with 5.5% frequency dispersion. Concerning the origin of the frequency dispersion in the accumulation in high-$k$/III-V stacks,the interaction between the slow traps distributed in the interface and carriers may be the possible reason^[14],and the passivation methods used in our case can effectively reduce the slow traps.

The Castagnè-Vapaille method is employed to discuss the effect of N$_{2}$ plasma treatment and (NH$_{4})$$_{2}$S$_{x}$ treatment against $D_{\rm it}$^[15]. The $D_{\rm it}$ value was calculated from the formula:

where $D_{\rm it}$ is in cm$^{-2}$ eV$^{-1}$,$C_{\rm OX}$ is the oxide capacitance,$A$ is the electrode area,$q$ is electron charge,$C_{\rm Lf}$ is low frequency capacitance,and $C_{\rm Hf}$ is high frequency capacitance. The energy distributions of $D_{\rm it}$ extracted for the samples without treatment,with N$_{2}$ plasma treatment,and with (NH$_{4})$$_{2}$S$_{x}$ treatment are depicted in Figure 3. Compared with the untreated capacitor which shows the $D_{\rm it}$ value of 1.05 $\times$ 10$^{12}$ cm$^{-2}$eV$^{-1}$ at $E_{\rm i}$ $+$ 0.24 eV,the passivated ones show obvious improvement in the quality of the interface with a $D_{\rm it}$ value of 4 $\times$ 10$^{11}$ cm$^{-2}$eV$^{-1}$ at $E_{\rm i}$ $+$ 0.32 eV for N$_{2}$ plasma treatment sample and a $D_{\rm it}$ value of 2.6 $\times$ 10$^{11}$ cm$^{-2}$eV$^{-1}$ at $E_{\rm i}$ $+$ 0.26 eV for (NH$_{4})$$_{2}$S$_{x}$ treatment sample. The $D_{\rm it}$ value indicates that the (NH$_{4})$$_{2}$S$_{x}$ treatment method can prevent the surface being oxidized and reduce the interface state density effectively.

Figure 4 illustrates the small hystereses of 92,82,and 89 mV for three samples measured at room temperature,which indicates that the Al$_{2}$O$_{3}$ deposited at 200℃ followed by 300℃ PMA treatment contains only a small amount of border traps and that is the main reason for the hysteresis^[16]. Figure 5 shows the shift of effective border trap density $\Delta N_{\rm bt}$ with gate voltage for Al/Al$_{2}$O$_{3}$/In$_{0.53}$Ga$_{0.47}$As capacitors without treatment,with N$_{2}$ plasma treatment,and with (NH$_{4})$$_{2}$S$_{x}$ treatment. A border trap is one of the near-interface slow traps that can electrically communicate with the underlying substrates^[17]. The effective border trap density per unit energy was extracted from the $C$-$V$ hysteresis characteristics at 1 MHz and calculated from the capacitance difference during the forward and reverse $C$-$V$ scans $C_{\rm rf} =\left| {C_{\rm r} -C_{\rm f} } \right|$,where $C_{\rm r}$ and $C_{\rm f}$ are the capacitance densities at a given $V_{\rm g}$ during reverse and forward scans,respectively^[18]. The effective border trap density $\Delta N_{\rm bt}$ can be obtained by integrating the value of the $C_{\rm rf}$ as shown in the formula:

where $q$ is electron charge,and parameter ``$A$'' is the area of MOS capacitor. The sample without treatment demonstrates the maximum $\Delta N_{\rm bt}$ value of 6 $\times$ 10$^{11}$ V$^{-1}$cm$^{-2}$ and the (NH$_{4})$$_{2}$S$_{x}$ treatment one shows the adjacent $\Delta N_{\rm bt}$ value of 5.5 $\times$ 10$^{11}$ V$^{-1}$cm$^{-2}$,and the N$_{2}$ plasma treatment sample presents the minimum $\Delta N_{\rm bt}$ value of 3.9 $\times$ 10$^{11}$ V$^{-1}$cm$^{-2}$ near the $V_{\rm FB}$; this result conforms with the $C$-$V$ hysteresis characteristics of the corresponding samples as seen in Figure 4.

Figure 6 shows the $I$-$V$ characteristics of all MOS capacitors. Owing to the fact that the $V_{\rm FB}$ of each sample is different,we compared the gate leakage current density ($J_{\rm g})$ at $V_{\rm FB}$ $+$ 1 V. The sample without treatment shows the $J_{\rm g}$ value of 1.5 $\times$ 10$^{-4}$ A/cm$^{2}$ at the voltage of 1.22 V,while the ones with N$_{2}$ plasma treatment and (NH$_{4})$$_{2}$S$_{x}$ treatment show the $J_{\rm g}$ values of 1.6 $\times$ 10$^{-6}$ and 1.2 $\times$ 10$^{-6}$ A/cm$^{2}$ at the voltage of 0.8 and 1.2 V,respectively. It is obvious that the $J_{\rm g}$ is significantly reduced after N$_{2}$ plasma or (NH$_{4})$$_{2}$S$_{x}$ treatment. Compared with the N$_{2}$ plasma treated capacitor,the (NH$_{4})$$_{2}$S$_{x}$ treated one shows a lower $J_{\rm g}$ value from the voltage of 0.2 to 1.5 V,and then increases rapidly,agreeing well with the $D_{\rm it}$ results in Figure 3,indicating that both of the passivated methods can effectively repair the interface traps,moreover the N$_{2}$ plasma treatment is more powerful to reduce the tunneling current caused by the traps^[19].

Figures 7(a)-7(c) show cross-sectional TEM images of the Al$_{2}$O$_{3}$/In$_{0.53}$Ga$_{0.47}$As interfaces without treatment,with N$_{2}$ plasma treatment,and with (NH$_{4})$$_{2}$S$_{x}$ treatment,respectively. Compared with the capacitor without treatment,the samples with N$_{2}$ plasma treatment and (NH$_{4})$$_{2}$S$_{x}$ treatment show a thicker amorphous layer. The difference of the amorphous thickness for all samples may be due to the different interfacial layers which are formed by N$_{2}$ plasma treatment and (NH$_{4})$$_{2}$S$_{x}$ treatment,respectively. Here,the measured thickness of the amorphous is $\sim$4.5 nm and the designed Al$_{2}$O$_{3}$ thickness is 3 nm for the N$_{2}$ plasma treatment sample,so we speculate the thickness of the interfacial layer is $\sim$1.5 nm. In the same way,we estimated the thickness of the interfacial layer to be $\sim$1 nm for the (NH$_{4})$$_{2}$S$_{x}$ treatment sample because the measured amorphous thickness is $\sim$4 nm. Obviously,the interfacial layer of the sample with N$_{2}$ plasma treatment is thicker than the one with (NH$_{4})$$_{2}$S$_{x}$ treatment; this result may be the reason for the phenomenon that the value of $J_{\rm g}$ for the sample with N$_{2}$ plasma treatment is the minimum when the voltage is greater than 1.5 V as shown in Figure 6.

4. Conclusions

We compared and studied the impact of N$_{2}$ plasma treatment and (NH$_{4})$$_{2}$S$_{x}$ treatment for n-type In$_{0.53}$Ga$_{0.47}$As surfaces on Al/Al$_{2}$O$_{3}$/InGaAs MOS capacitors properties. We found that both of the methods could effectively remove the native oxides and passivate the surface. The sample with N$_{2}$ plasma treatment showed the best hysteresis characteristics ($\sim$82 mV) and the smallest frequency dispersion (2.5%) in the accumulation region,it also showed the minimum $\Delta N_{\rm bt}$ value and good $I$-$V$ properties,indicating that the nitridation process could increase the amount of Ga-N bonds,reduce the amount of Ga dangling bonds and border traps,decrease the tunneling current caused by the interface traps and improve the electron mobility. On the other hand,the sample with (NH$_{4})$$_{2}$S$_{x}$ treatment demonstrated the smallest frequency dispersion (0.8%) near the $V_{\rm FB}$ and also presented the minimum $D_{\rm it}$ value of 2.6 $\times$ 10$^{11}$ cm$^{-2}$eV$^{-1}$,indicating that the sulfur passivation could effectively remove the native oxides,prevent the surface being oxidized,enhance the gate control ability and improve MOSFET performance. According to the advantages of these two methods,a technique combining the N$_{2}$ plasma treatment with the (NH$_{4})$$_{2}$S$_{x}$ treatment should be explored to further passivate the Al$_{2}$O$_{3}$/InGaAs interlayer.