1. Introduction

As the complexity of data converters architectures is increasing day by day, it is a time saving approach to find out the electrical performance and to determine their relevant data features by using behavioral models^{[1, 2]} to simulate it. A specific simulation environment has been developed for this purpose, which gives freedom to designers to do behavioral modelling of pipelined ADCs in a time-domain. In the early days, for modeling of analog and mixed signal blocks^[3] like data converters, it has been realized at the device level to get an accurate performance to consider non-ideal effects like noise, comparator offset, distortion, op-amp gain error and capacitor mismatching etc.^{[4, 5, 6, 7, 8]}. All the non-idealities shift the ideal residue graph either in the horizontal or vertical direction^{[9, 10, 11, 12, 13, 14, 15]}. The only problem with that modeling style was the technology and architecture dependency which required more simulation time. Looking at the complexity of the designs, there is a need to have an accurate and speedy model. So, the trends started moving towards behavioral modeling.

In this paper, a high performance 14-bit pipelined RSD (redundant-signed-digit) ADC is proposed which has been validated using behavioral modeling. All blocks of the Pipelined ADC describe their behavior by using the mathematical characteristics and are programed in MATLAB. In real circuits, there may be some sources of errors like the ADC comparator, amplifier offsets, and non-exact $\pm V_{\rm ref}$ values; this paper focuses on the new methodology of digital error correction logic/RSD to handle some of these errors. Digital error correction logic/RSD is coded in a hardware description language i.e. To check the dynamic performance, VHDL and MATLAB programming is used. To illustrate the operation of the Pipelined ADC and to find out SNDR, SNR and SFDR with the proposed technique, 1024 point FFT is applied. This paper is organized as follows. Two different topologies of Pipelined ADCs i.e. 1-bit/stage and 1.5-bit/stage architecture are discussed in Section 2. The proposed design for digital error correction logic and non-ideal MDAC errors are described in Section 3 and in Section 4, the dynamic performance of the 14-bit pipelined ADC of the proposed design is presented. The conclusion is covered in Section 5.

2. Architecture of pipelined ADC

The pipelined ADC^{[16, 17, 18, 19, 20, 21, 22, 23, 24, 25]} is an array of $n$ individual stages arranged in a cascaded manner. There are units like the sample-and-hold circuit, the $m$-bit digital to analog converter, the $m$-bit analog to digital converter ($m$ is a generalized number which indicates the number of bits/stage), an analog subtractor and a 2$^m$ gain amplifier which are the building blocks of the pipelined ADC^{[7, 8]}.

2.1 1-bit/stage pipelined ADC

The block diagram of the 14-bit pipelined ADC, which includes the single stage architecture (for $m=$ 1) is shown in Figures 1(a) and 1(b). For every clock cycle, the sample and hold circuit samples the input voltage $V_{\rm in}$ during the sampling phase and holds the sampled value during the hold phase. The function of the DAC is to convert the digital output back to an analog voltage value, so that it gets subtracted from $V_{\rm in}$ and produces the new output voltage that is known as the residue of that particular stage which works as the input voltage for the succeeding stage. The residue voltage is defined as:

$$\begin{equation} V_{\rm res}=(V_{\rm in}-V_{\rm dac})2^m. \end{equation}$$

(1)

If each stage of the pipelined ADC produces $n$ bits and the number of stages is $m$, then the total bits produced by the ADC will be $m$ × $n$ bits. The resolution of the ADC depends on the topology chosen at each stage. If we consider that each stage has 1 bit/stage topology and each stage takes $k$ seconds to complete the process, there will be a latency of $k$ × $m$ seconds and the throughput of the ADC will be 1/$k$ samples per second. The ADC's speed depends upon the settling time of the S/H and DAC unit. The one bit comparator is simply a one bit ADC and produces the output, $D_{\rm out}$, which compares the input voltage with its $V_{\rm mid}$ value, as shown by

$$\begin{equation} D_{\rm out}= \begin{cases} 1, \quad V_{\rm in} \geqslant V_{\rm mid} \\[2mm] 0, \quad V_{\rm in} < V_{\rm mid} \end{cases} \end{equation}$$

(2)

If we consider negative and positive reference voltages as ($\pm V_{\rm ref}$), then the output from the digital to analog converter, $V_{\rm dac}$, is given as

$$\begin{equation} V_{\rm dac}= \begin{cases} -V_{\rm ref}, \quad D_{\rm out}=0, \\[2mm] +V_{\rm ref}, \quad D_{\rm out}=1. \end{cases} \end{equation}$$

(3)

The amplifier is used with a gain of two and the switched-capacitor (SC) amplifier^{[9, 10]} is used to perform these two functions altogether, as shown in Figure 1(b). If feedback capacitor and input capacitors are used of the same value, the ideal residue voltage from each stage after passing through the summer will be $V_{\rm res}$, which is given by:

$$\begin{equation} V_{\rm res}=2V_{\rm in}-V_{\rm dac}. \end{equation}$$

(4)

An ideal transfer graph of output voltage w.r.t change in input voltage or residue voltage graph is shown in Figure 2.

The output voltage, $V_{\rm res}$ from the previous stage becomes input voltage as $V_{\rm in}$ for the next stage. Each stage has its own gain of 2, so that $V_{\rm res}$ from the stages further down the pipelined ADC are making their transitions at a faster rate. While considering an example of 4-bit pipelined ADC, Figure 3 shows various residues as well as digital outputs.

If $+V_{\rm ref}$ is 1 V, $-V_{\rm ref}$ is 0 V, $V_{\rm mid}$ is 0.5 V and the input for the first stage is 0.7 V, $D_{\rm out}$ will be “1” as the digital output from stage1 and the residue will be 2 × 0.7 - 1 $=$ 0.4 V, which will act as an input for the second stage. Now 0.4 V is less than $V_{\rm mid}$, so digital output is “0” and $V_{\rm ref}$ is 0.4 × 2 $+$ 0 $=$ 0.8 V, as the input for the third stage. As 0.8 V is more than 0.5 V so digital output is “1” and the input for the next stage will be 0.8 × 2 $-$ 1 $=$ 0.6 V. At the fourth stage, as 0.6 V is greater than $V_{\rm mid}$ so the digital output will be “1”. In this way, the complete digital output will be 1011 from all four stages. Due to the comparator offset error, suppose the output of stage 1 has shifted from 0.4 to 0.5 V, in that case the digital output from stage 2 will be “1” instead of “0”. $V_{\rm res}$ will be 0.5 × 2 - 1 $=$ 0 V for the next stage and the digital output will change correspondingly. The change in residue voltage is shown in Figure 4. Now the complete output becomes 1100 instead of 1011 which is shown in Figure 5. The technique which is used to relax from this error is the 1.5 bit/stage pipelined ADC.

2.2 1.5 bit/stage pipelined ADC

The most popular topology in pipelined ADCs is the 1.5-bit per stage implementation, and is shown in Figures 6(a) and 6(b). The accuracy requirements of the ADCs have been relaxed with lower inter stage amplifier gain and more resolution and higher speed can be achieved^{[11, 12, 13]}. In this topology, each stage of the ADC is composed of two comparators. The following equations show the functionality of the 1.5 bit/stage and it generates two digital output bits ($Q$ and $P$) for digital correction are given^{[11, 12, 13]} as: $$P = 0, \quad V_{\rm in}\leqslant -V_{\rm ref}/4,$$ $$P = 1, \quad V_{\rm in}> -V_{\rm ref}/4,$$ and $$Q = 0, \quad V_{\rm in}\leqslant +V_{\rm ref}/4,$$ $$Q = 1, \quad V_{\rm in}> -V_{\rm ref}/4,$$

Based on the QP values, the residue output, $V_{\rm OUT}$ will be: $$\begin{equation*} \begin{split} V_{\rm OUT}&=2V_{\rm in}+V_{\rm ref}, \quad {\rm QP}=00, \\[2mm] V_{\rm OUT}&=2V_{\rm in}, \quad {\rm QP}=01, \\[2mm] V_{\rm OUT}&=2V_{\rm in}-V_{\rm ref}, \quad {\rm QP}=11, \end{split} \end{equation*}$$

Figure 7 shows the residue graph for the same.

The DAC acts as a multiplexer, which can decide the operation of $V_{\rm ref}$ with input voltage. $V_{\rm ref}$ may be added, subtracted or pass the input without modification. The extra 0.5-bit redundancy is used to overcome the errors and inaccuracies by the comparators. By digital error correction logic, this redundancy will be canceled out later on. The amplifier gain is again kept as the same 1-bit/stage, which is ideally 2. In this way, with the lower gain of the inter stage amplifier, the bandwidth is maximized. Because the gain-bandwidth product is constant, the speed of the converter will increase. By taking the example of the 7-bit pipelined ADC with the 1.5 bit/stage, Figure 8 shows the residue, input, and output voltages stage by stage when 0.3 V is considered as the input of stage 1^[12]. The ideal digital output comes out as 1100110. Figure 9 shows how this operation nullifies the effect of non-ideal effects on pipelined ADC without changing the actual digital output^[13]. In Figure 10, it is clearly shown how two digital outputs are used for redundancy by the Architecture, which is why it is also known as redundant signed digit (RSD).

The binary conversion logic starts from the Q and P generated by the last stage. For binary conversion from each stage, it generates an output bit and a carry bit to the next higher stage, which plays a vital role in generating the next output bit. The last carry generated from the most significant stage, C1, will become the sign digit, $D_{0}$.

3. Proposed architecture of pipelined ADC

In the existing architecture of the 1.5 bit/stage pipelined ADC architecture, a huge number of delay units are used to store digital outputs of different stages^{[14, 15]}. For the 4 stages pipelined ADC, stage 1 uses four delay units and Stage 2 uses three, and succeeding stages use one less delay unit as compared to the previous stage. So, it shows a latency of clock pulses equal to the number of stages. Each stage is producing 2 bits ideally but one bit is a redundant bit from each stage but in a specified way. In this paper, a new method is proposed to remove the bit and to generate the final digital output. Here each addition operation should not wait for the carry bit calculated from the previous addition. The whole process is completed in two steps. As shown in Figure 11, only half adders are used instead of full adders as per the existing architecture. In the first step, the two inputs of the half adders are taken from two different stages. The one input is used from the current stage and other input from the previous stage and two outputs sum and carry will be produced from the half adder. In the second step these sum bits and carry bits are used as input bits for the next step. Here a half adder and one exclusive-or gate is used. The sum bit from the last stage is taken out as LSB of final digital representation of analog value. The carry bit from the last stage is added to the sum bit of the second last stage and the sum bit generated from that half adder is considered as the second last digital output bit. An exclusive-or operation is performed on the carry bit generated from the second last stage and the carry generated from the half adder. In this way, all 14 bits out of 28 bits of digital output get generated and 14 bits are reduced.

Non-ideal effects in ADC

MDAC in a pipelined ADC is a main source of errors. MATLAB programs are used to analyze errors like finite DC gain of op-amp, capacitor mismatch or it can be defined as gain error $-\frac{C_{\rm s}}{C_{\rm f}}$ and comparator offset ($V_{\rm off}$).

Capacitor matching: The capacitor ratio $\frac{C_{\rm s}}{C_{\rm f}}$ is really important for the gain of a SC MDAC. Unequal values of the capacitors $C_{\rm s}$ and $C_{\rm f}$ make a change in residue output, which will be proportional to the mismatch of capacitors. An accurate capacitor matching^{[7, 8, 9, 10]} is required to design a high resolution pipeline ADC. The value of the capacitor is obtained from:

$$\begin{equation} C=\frac{\varepsilon A}{t_{\rm ox}} \end{equation}$$

(5)

where $\varepsilon_{\rm ox}$ is the dielectric constant of silicon dioxide, $A$ is the area of the capacitor and $t_{\rm ox}$ is the thickness of the oxide. The capacitance value is directly proportional to the area and inversely proportional to the oxide thickness. Since the gain of the MDAC is determined by the capacitor ratio $\frac{C_{\rm s}}{C_{\rm f}}$, so the accuracy of a capacitor ratio is more important than the accuracy of capacitance in switched capacitor circuits.

If the difference of both capacitors is small, the accuracy of the capacitor ratio improves and accurate output can be achieved. A mismatch error due to over-etching can be minimized by applying capacitors in an array of small equal sized unit capacitors. By laying out capacitors in common centric geometry, the variation of oxide thickness can be minimized and hence a mismatch error will be minimized and the ratio accuracy of capacitors will be improved. Pipelined ADCs are implemented by the switched capacitor (SC). It is given by

$$\begin{equation} V_{\rm res}=\left(1+\frac{C_{\rm s}}{C_{\rm f}} \right)V_{\rm in}-\left(\frac{C_{\rm s}}{C_{\rm f}} \right)V_{\rm dac}. \end{equation}$$

(6)

Ideally $C_{\rm s}=C_{\rm f}$ and Equation (4) is achieved. Let $\Delta$ be the relative capacitor mismatch error i.e. $\Delta=(C_{\rm s}-C_{\rm f})/C_{\rm f}$, so to include the effect of the capacitor mismatch, Equation (4) is modified to Equation (6) (Delic-Ibukic and Hummels, 2006). This causes a change in stage gain (slope of residue curve) causing gain error as well as a change in the sub-DAC value to be subtracted.

Putting $\Delta$ in Equation (4) leads to

$$\begin{equation} \begin{split} V_{\rm res}{}& =(2+\Delta)V_{\rm in}-(1+\Delta)(V_{\rm dac}) \\[2mm]& =[2V_{\rm in}-(V_{\rm dac})]+\Delta (V_{\rm in}-V_{\rm dac}). \end{split} \end{equation}$$

(7)

Figure 12 shows the effect of capacitor mismatch on the transfer function of a 1.5-bit MDAC.

Comparator offset: Depending upon the strength of the input signal which may be larger, smaller or equal to the reference level, a comparator produces an output signal. While computing the difference between input signal and reference signal, an internal offset voltage will get added to this difference. So it might be possible that when two inputs are close together, the comparator may mislead further stages of pipelined ADC by giving the wrong output.

Figure 13 shows the effect of comparator offset. The dotted line shows a transfer function without any error and the solid line shows a transfer function with an offset voltage in a comparator.

Op-amp's finite DC gain: An operational amplifier plays a vital role in the switched capacitor used in pipelined ADCs^[6]. The circuit configuration of a subtractor and amplifier is already illustrated in Figure 6(b). We can represent the parasitic capacitance at the input of the operational amplifier as $C_{\rm P}$ and its gain as $A$.

During the sampling phase, both the capacitors ($C_{\rm s}$ and $C_{\rm f}$) are connected to the input, sampling an input signal on the capacitors so the charge at the $V_x$ node during the sampling phase is given as:

$$\begin{equation} qx(\Phi_1)=(V_x-V_{\rm in})(C_{\rm S}+C_{\rm f}). \end{equation}$$

(8)

During the amplifying phase, depending on the output of a sub-ADC, the $C_{\rm S}$ is connected to $\pm V_{\rm ref}$ or to ground. The total charge stored at the $V_x$ node during this clock phase is given by

$$\begin{equation} qx(\Phi_2)=(V_x-V_{\rm dac})C_{\rm S}+(V_x-V_{\rm res})C_{\rm f}+V_xC_{\rm p}. \end{equation}$$

(9)

Solving Equations (7) and (8) above gives

$$\begin{equation} V_{\rm res}=\frac{1}{1+\dfrac{1}{A\beta}} \left[\left(1+\frac{C_{\rm s}}{C_{\rm f}} \right)V_{\rm in}-\frac{C_{\rm s}}{C_{\rm f}}V_{\rm dac} \right]. \end{equation}$$

(10)

The DC gain requirement of an op-amp for no missing codes is $A \geqslant 2^{n+1}$ for 1/4 LSB accuracy. If the error due to finite op-amp gain is smaller than 1/4 LSB of the remaining resolution, then it could not make any changes in output. Figure 14 shows the effect of finite DC gain error of the op-amp used in a 1.5-bit MDAC. There is another offset other than comparator offset that rises due to the OPAMP used in the MDAC, considering the effect of op-amp offset, the residue is given by

$$\begin{equation} V_{\rm res} \approx \left(1-\frac{1}{A\beta} \right) \left[\left(1+\frac{C_{\rm s}}{C_{\rm f}} \right)V_{\rm in}-\frac{C_{\rm s}}{C_{\rm f}}V_{\rm dac}+\frac{V_{\rm os}}{\beta} \right], \end{equation}$$

(11)

where $V_{\rm os}$ is the offset due to op-amp, $\beta$ is the feedback factor and the effect of op-amp offset voltage is shown in Figure 15.

4. Result and discussions

The simulation software MATLAB is used to simulate and to analyze the performance of the proposed architecture of the 14-bit Pipelined ADC. The pipelined ADC is assumed to have 14-bits resolution and the mismatch error is assumed to be within 0.1-0.5%, to illustrate the operation of the pipelined ADC and to find out SNDR, SNR and SFDR with the proposed technique by applying 1024 point FFT. With this proposed method SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR becomes 102.8 dB. Additional benefit of the proposed architecture is that it utilizes less hardware without compromising its simulation speed. To validate the proposed architecture of 14-bit pipelined ADC with the ideal and the non-ideal models, MATLAB and Xilinx tools are used. Several simulations are executed to obtain SNDR, SFDR and SNR (signal-to-noise ratio), and other ADC specifications. Figure 16 shows the 1024 FFT, where the results corresponding to SNR, SNDR and SFDR are reflected. Model validation was done by reconstructing the digital output into its original analog form. A comparison table has been made to compare the proposed model with existing models shown in Table 1, which is able to prove the accuracy of the proposed model of pipelined ADC.

5. Conclusion

A novel architecture of pipelined redundant-signed-digit analog to digital converter (RSD-ADC) has been presented in this paper featuring high SNR, SFDR and SNDR with efficient background correction logic. The ADC is implemented using MATLAB and VHDL programs. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. The proposed digital correction logic demonstrates the functionality of 14-bit pipelined ADC with each stage of 1.5 bit. This prototype ADC Architecture accounts for capacitor mismatch, comparator offset and finite op-amp gain error in the MDAC (residue amplification circuit) stages. The simulation results show that SNR, SNDR and SFDR can be enhanced to 85.9, 85.89, and 102.8 dB respectively. It is shown that the proposed architecture reduces the requirement of digital hardware, silicon area and the complexity of the design.