1. Introduction

In recent years,the fast increase in the data bandwidth of wireless communication systems has driven the development of high-resolution analog-to-digital converters (ADCs) with high sampling rates. Among the variety of ADC architectures,the pipelined ADC is a preferred choice to meet the requirements of these high-speed and high-resolution applications. Traditionally,multi-bit pipelined ADCs are implemented with a sample-and-hold amplifier (SHA) at the front-end^{[1, 2]}. However,the design of the front-end SHA is a very challenging task in high-speed,high-resolution applications due to the stringent tradeoffs between the signal-to-noise ratio (SNR),the linearity,and the power dissipation. Because the front-end SHA is essentially a switched-capacitor sample-and-hold circuit followed by a unit-gain buffer,it is possible to integrate the SHA into the first-stage multiplying digital-to-analog converter (MDAC) to form the so-called SHA-less pipelined ADC,which has an obvious advantage of low power consumption due to the elimination of the high-performance opamp in the dedicated front-end SHA^[3]. However,critical problems of SHA-less pipeline architecture are the front-end sampling clock skew and the offset of the comparators in the first-stage sub-ADC^{[4, 5, 6]}. In SHA-less pipelined ADCs,especially for those employing a multi-bit first stage to reduce power consumption,the skew of the front-end sampling clock together with the comparator's offset in the sub-ADC of the first stage generate a large dynamic offset at high input frequencies,which would lead to missing code when the overall offset exceeds the built-in redundancy of the pipelined architecture. Therefore,dedicated circuit design techniques must be employed to reduce the clock skew and comparator offset to ensure the residue of the first stage does not exceed the input range of the second stage.

Many research works have been carried out to solve the dynamic offset issues caused by the skew of the front-end sampling clock and the comparator offset. A straightforward method for solving the skew problem is to match elaborately the sampling networks of the MDAC and the comparators^[3]. This method is effective for low speed ADC with low frequency input signals. However,for ADCs with over 100-MS/s sampling rates,the devices in the sampling networks and the comparators are usually designed with a small size to ensure high-speed conversion,which results in large comparator offset in the sub-ADC and brings difficulties to match the sampling network. Another technique is to dynamically calibrate the clock skew of the sampling network in the first stage^[5],in which an additional comparator is used to monitor the first-stage residue voltage. If the residue voltage exceeds a given reference voltage,the delay in the clock path of the MDAC or the sub-ADC is adjusted accordingly by a calibration block to obtain a small clock skew. This method can calibrate the offset caused by the clock skew effectively,but cannot deal with the comparator offset,which may result in conversion failures especially for multi-bit stage architectures. Comparator offset calibration methods in References ^{[8, 9]} use a negative feedback circuit to adjust the current injecting to the output loads of the preamp in the comparator and reduce the offset significantly,but the additional current sources used to adjust the offset slow down the operation speed of the comparator and deteriorate the clock skew issues. Therefore,these methods are not suitable for SHA-less pipelined ADCs that require high-speed operation of comparators. Cancellation of comparator offset for SHA-less pipelined ADC is addressed in Reference ^[9],but the detailed implementation of the comparator with offset cancellation is not expressed wherein.

In this paper,a 14-bit,100-MS/s pipelined ADC without dedicated SHA is presented. The ADC adopts a 3-bit first stage to reduce power consumption,which shows a much more narrow tolerable dynamic offset than a traditional 1.5-bit stage. In addition to elaborate matching of sampling network,a background offset cancellation circuit is proposed to reduce the offset of the comparators in the first-stage sub-ADC. In a short period inserted in the sampling phase of the comparator,a charge-pump based offset detection circuit generates a pair of calibration signals to adjust the substrate voltage of the differential load transistors in the preamplifier of the comparator. Very low offset of the comparator can be obtained because of the negative feedback loop operating in the background,which ensures the overall offset of the first stage be corrected by the built-in redundancy of the pipelined ADC. Section 2 describes the architecture of the ADC. Section 3 covers the details of circuit design for the main building blocks. Section 4 presents the measurement results and finally Section 5 concludes the paper.

2. ADC architecture

It is well known that eliminating the dedicated SHA not only eliminates its power,but also its noise contribution. This allows the rest of the stages in the pipeline ADC to use smaller capacitors for a given noise budget,which further saves power consumption. Also,eliminating the SHA makes the ADC easier to drive,since for a given noise budget,the first stage of the pipeline can use a smaller sampling capacitor^[3]. The linearity of the front-end sampling circuit is also improved,because smaller switches with less nonlinear parasitic in the input sampling network can be used for smaller sampling capacitor. Additionally,using a multi-bit first stage has been shown to offer significant power savings for high-resolution pipelined ADCs at the cost of increased circuit complexity^[4].

Based on the above considerations,an SHA-less architecture with a multi-bit first stage is adopted for the presented ADC,as shown in Figure 1. In order to achieve optimum trade-off between power dissipation,device matching,and design complexity,the first two stages of the pipeline ADC are designed as 3-bit stages,followed by eight 1.5-bit stages and a final 3-bit flash stage. Both the flash and the MDAC in stage-1 simultaneously sample the input signal and the quantized output of the flash drives the MDAC to produce the residue signal. Because the nominal gain of the MDAC is 4 for the 3-bit first stage,it offers a redundancy of 1 bit to tolerate the dynamic offset generated by the sampling clock skew and the comparator offsets. As can be seen,there is also a 1-bit overlap (redundancy) for digital error correction between each two neighboring stages. This gives a total of 15 internal bits out of the digital error correction block,of which only 14 bits are used. The last bit is used to implement a foreground calibration of the capacitor mismatch according to the algorithm in Reference ^[6].

As seen from Figure 1,a dedicated comparator offset cancellation block is employed in stage-1 to ensure the overall dynamic offset does not exceed the correction range. A detailed description of this comparator offset cancellation block is given in the following section. Although not shown in Figure 1,there are also a bandgap-based reference voltage generator and a clock generator,which provide the required reference voltages and two-phase,non-overlapping clock signals for the MDAC and the comparators,respectively.

3. Circuit implementation

3.1 Structure of the first stage

The structure of the 3-bit first stage of the presented ADC and the timing of the control signals are shown in Figures 2(a) and 2(b),respectively. The MDAC op-amp and the switching network are shown on top of the one out of the eight flash comparators given in the dash box. For simplicity,only a single-ended version is represented,although the implementation is fully differential. Because there is no dedicated SHA in the architecture,the capacitors $C_{\rm S}$[7:0] and $C_{1}$ are charged by the input signal $V_{\rm IN}$ simultaneously in the tracking phase,$\phi_{\rm 1P}$. The skew in the sampling clock will generate a dynamic offset voltage $V_{\rm SKEW}$,between the sampled results of the MDAC and the comparator,as shown in Figure 2(c). Obviously,the value of $V_{\rm SKEW}$ increases with the frequency of the input signal. In order to ensure high linearity,the switches used to sample $V_{\rm IN}$ are realized as bootstrapped switches^[4],as shown in Figure 2(a). In the phase of $\phi_{2}$,the 8 comparators generate conversion results through comparing $V_{\rm IN}$ with given reference voltages after the rising edge of $\phi_{\rm 2D}$. In the same phase,the 8-bit output data of the comparators are used to control the corresponding DAC switches,which connect the bottom plates of $C_{\rm S}$[7:0] to the correct reference voltage ($V_{\rm BOT}$ or $V_{\rm TOP})$. The obtained residue voltage on the common top plates of $C_{\rm S}$[7:0] is amplified by the residue amplifier with a nominal gain of 4.

The ideal residue voltage transfer curve of the 3-bit first stage is expressed by the solid lines in Figure 3. As can be seen,the sub-ADC generates 9 levels because 8 comparators are used. Although the encoded output of the first stage has 4 bits,the most significant bit (MSB) is only used to indicate the over-range case of the input signal. Therefore,the first stage is essentially a 3-bit stage^[3]. As the gain of the residue amplifier is 4,the ideal maximum value of $V_{\rm RES}$ is $V_{\rm REF}$/2,which offers one-bit redundancy to the dynamic offset of the stage. With a $V_{\rm REF}$ of 1V,the allowable maximum dynamic offset of the stage can be calculated as 125 mV. If the overall offset voltage exceeds this value,$V_{\rm RES}$ will exceed the correction range,resulting in conversion failure,as shown in Figure 3. Because the total dynamic offset is the sum of the offset generated by clock skew,$V_{\rm SKEW}$,and the comparator offset,$V_{\rm OFFSET}$,circuit design should ensure

$$\begin{equation} \label{eq1} \left| {V_{\rm OFFSET} +V_{\rm SKEW}} \right|<\frac{V_{\rm REF}}{2^3}. \end{equation}$$

(1)

In order to meet the requirement of Equation (1),the skew of the sampling clock network and the comparator offsets must be reduced extensively. In circuit implementation,the schematic and layout design for the switches and capacitors in the sampling path are elaborately matched to realize low clock skew,as shown in Figure 2(a). However,as the sampling rate of this paper is up to 100 MS/s,the transistor in the switches and the comparators are designed with small sizes to ensure high speed operations,which limits the matching performances to a given extent. Therefore,a background comparator offset cancellation circuit is proposed to obtain small enough overall dynamic offsets for the first stage,which is discussed in the following sub-section.

3.2 Proposed comparator with background offset cancellation

The schematic of the proposed comparator with background offset cancellation is shown in Figure 4(a),which is composed of a switched-capacitor front-end,an analog block consisting of a pre-amplifier (preamp) and a latch,an output stage,and an offset cancellation circuit. The timings of the control clock signals are given in Figure 4(b).

As seen from Figure 4,in the tracking phase ($\phi_{\rm 1P}$ and $\phi_{1}$ are high),capacitors $C_{\rm 1P}$,$C_{\rm 1N}$ and $C_{\rm 2P}$,$C_{\rm 2N}$ sample the differential input voltages,$V_{\rm IN+}$,$V_{\rm IN-}$,and the differential reference voltages,$V_{\rm REF+}$,$V_{\rm REF-}$,through the switches $S_{1}$-$S_{6}$,respectively. When $\phi _{2}$ is high,the differential difference between the value of $V_{\rm IN}$ sampled at the falling edge of $\phi_{\rm 1P}$ and $V_{\rm REF}$ is generated on the right plates of the capacitors ($V_{\rm X+}$,$V_{\rm X-})$. It can be calculated that the differential voltage of $V_{\rm X+}$ and $V_{\rm X-}$ in the $\phi_{2}$ phase is

$$\begin{equation} \label{eq2} V_{\rm X+} -V_{\rm X-} =\frac{(V_{\rm IN+} -V_{\rm IN-} )-(V_{\rm REF+} -V_{\rm REF-} )}{2}. \end{equation}$$

(2)

The obtained difference between $V_{\rm IN}$ and $V_{\rm REF}$ is amplified to a larger value by the preamp in the $\phi_{2}$ phase. After the rising edge of $\phi_{\rm 2D}$,the amplified difference is regenerated to the power (or ground) rail by the latch,and the comparison results are obtained at the outputs of G$_{1}$ and G$_{2}$,which are also used for decoding and D/A conversion in the MDAC.

The proposed offset calibration is operated in the tracking phase when $\phi_{\rm 1P}$ and $\phi_{1}$ are high. As shown in Figure 4(b),two additional clock signals $\phi_{\rm CAL}$ and $\phi_{\rm CS}$ are designed to control the offset cancellation process. When $\phi_{\rm 1P}$ is high,both $V_{\rm X+}$ and $V_{\rm X-}$ are driven by $V_{\rm CM}$. In the reset period when $\phi_{\rm CAL}$ is high,the outputs of the latch ($V_{\rm 1O+}$ and $V_{\rm 1O-})$ are reset to the same voltage,while in the cancellation period when $\phi_{\rm CAL}$ is low,$V_{\rm 1O+}$ and $V_{\rm 1O-}$ are regenerated to $V_{\rm DD}$ or ground according to the offset in the comparator. The results of $V_{\rm 1O+}$ and $V_{\rm 1O-}$ are sampled by the 2 DFFs (G$_{3}$ and G$_{4})$ at the rising edge of $\phi_{\rm CS}$ to generate the digital control signals $V_{\rm C+}$ and $V_{\rm C-}$. Because $\phi_{\rm CAL}$ is always low when $\phi_{2}$ is high,the offset sampling process has no effect on the normal operation of the comparator.

Ideally,if there is no offset in the comparator,$V_{\rm C+}$ (or $V_{\rm C-})$ will generate “1" and “0" alternatively with equal possibilities. However,if the referred-to-the-input (RTI) offset is positive and larger than a given value,$V_{\rm C+}$ will output constant “1",and $V_{\rm C- }$will output constant “0" at every rising edge of $\phi_{\rm CS}$. On the other hand,if the RTI offset is negative,$V_{\rm C+}$ and $V_{\rm C-}$ will output constant “0" and “1",respectively. Therefore,the digital states of $V_{\rm C+}$ and $V_{\rm C-}$ indicate the polarity of the RTI offset,but have no information about the amount of the offset.

In order to cancel the comparator offset with the help of $V_{\rm C+}$ and $V_{\rm C-}$,a negative feedback network based on a charge pump is proposed,as shown in Figure 4(a). The transistors M$_{\rm C4}$ and M$_{\rm C5}$ in the charge pump are biased with $V_{\rm B4}$ and $V_{\rm B5}$,providing a current sink and a current source,respectively. The signals $V_{\rm C+}$ and $V_{\rm C-}$ control the charging and discharging of the capacitor $C_{\rm C}$ through the switches M$_{\rm C6}$ and M$_{\rm C7}$,respectively. The difference between the output voltage of the charge pump,$V_{\rm PUMP}$,and a given reference voltage,$V_{\rm B2}$,is amplified by a low-gain differential amplifier to generate a pair of differential control signals,$V_{\rm A+}$ and $V_{\rm A-}$,which are used to adjust the substrate voltage of the load transistors,M$_4$ and M$_5$,of the preamp. Therefore,the offset sampling circuit and the charge-pump based offset cancellation circuit form a negative feedback structure.

It can be deduced that $V_{\rm C+}$ (or $V_{\rm C-})$ will toggle between “1" and “0" after the negative feedback system locks to its stable state,which means that the offset of the comparator is reduced to a very small value. Because the overall structure can be thought of as a first-order feedback system in the vicinity of locking,it is always able to approach the locked state with the proper selection of circuit parameters,such as the value of $V_{\rm B2}$,and the gain and operation point of the error amplifier.

The simulated curves on the critical nodes with an artificially added RTI offset of 10 mV and -10 mV are given in Figures 5(a) and 5(b),respectively. The simulation is carried out with a clock frequency of 100 MHz. In both cases,because $V_{\rm PUMP}$ is initialized to a very low value,$V_{\rm A+}$ is much larger than $V_{\rm A-}$ at the beginning. Therefore,$V_{\rm C+}$ output constant “1" after the start of the cancellation process,which charges $C_{\rm C}$ and results in a steady increase in $V_{\rm PUMP}$. The system approaches to a locked state in a short time,and $V_{\rm C+}$ toggles between “0" and “1" alternatively for both cases,which means the offsets are cancelled to very low values. In Figure 5(a),$V_{\rm A+}$ is larger than $V_{\rm A-}$ after being locked because the RTI offset is 10 mV,while in Figure 5(b),$V_{\rm A+}$ is lower than $V_{\rm A-}$ because the added RTI offset is -10 mV.

The simulation results show that the proposed circuit is able to cancel the comparator offset effectively in the background at very high speed,and this is because the calibration circuits add very little loads to the main comparator. The only price is some increase in power and circuit area consumption. However,compared to the power and area saving due to the eliminating of the front-end SHA,the proposed circuit is still very power and area efficient.

3.3 Residue amplifier in the first stage

In order to ensure high gain,large swing and good linearity for the residue amplifier in the first stage,a two-stage operational transconductance amplifier (OTA) with Miller-compensation is employed^[4],with a simplified schematic shown in Figure 6. The first stage uses PMOS inputs with a telescopic structure and the second stage is a differential pair with NMOS inputs. As analyzed in Reference ^[4],the first stage with PMOS inputs can achieve good trade-off between 1/$f$ noise and power consumption. Separate switched-capacitor common-mode feedback (CMFB) circuits are designed both for the first and second stages to ensure stable operation of the OTA with a high common-mode rejection ratio.

The simulated residue curves of the 3-bit first stage with a -1 to 1 V ramp input signal is given in Figure 7 ($V_{\rm REF}$ is 1 V),which verifies the proper operation of the first stage. As the clock skew and offsets due to layout and fabrication mismatches are not accounted for in the simulation,the residue curve is almost bounded in the range of -0.5 to 0.5 V.

4. Measurement results

The presented pipelined ADC is fabricated in a 1P6M 0.18-$\mu$m CMOS technology with metal-insulator-metal (MIM) capacitors. The micrograph is shown in Figure 8,and the chip area is 3 × 4 mm$^{2}$ . As can be seen,because the performance of the 3-bit first stage is most important for the ADC,it consumes the largest area among other blocks. The bias currents and device sizes for the subsequent stages are scaled down along the pipeline to save chip area and power consumption. The presented ADC consumes 237 mW from a 1.8-V power supply.

In order to verify the effectiveness of the proposed comparator with background offset cancellation,the dynamic performances are measured with the offset cancellation turned on and off,respectively. The measurements are carried out with an input signal of 30.1 MHz sine wave under a sampling rate of 100 MS/s. The measured spectrum with the offset cancellation circuit turned off is shown in Figure 9(a),which shows that the signal-to-noise and distortion ratio (SNDR) and the spurious- free dynamic range (SFDR) are only 55.4 dB and 77.8 dB,respectively. As stated above,the poor dynamic performances are mainly resulted from the large overall dynamic offsets in the first stage. As the comparators in the first stage are designed with small sizes to realize high-speed operation,their intrinsic offsets are relative large. The measured spectrum with the comparator offset cancellation circuit turned on is shown in Figure 9(b),which shows that the SNDR and the SFDR are improved to 70.2 dB and 85.4 dB by the proposed offset cancellation circuit,respectively,corresponding to an effective-number-of-bit (ENOB) of 11.4 bit.

The measured differential nonlinearity (DNL) and integral nonlinearity (INL) with offset cancellation turned on is shown in Figures 10(a) and 10(b),respectively. The presented ADC achieves a maximum DNL of 0.22 LSB and a maximum INL of 1.4 LSB.

To evaluate the efficiency of the presented ADC,the figure of merit (FOM) is calculated with the definition^[1]:

$$\begin{equation} \label{eq3} F_{\rm OM} =\frac{P}{2^{\rm ENOB} f_{\rm S} }, \end{equation}$$

(3)

where $P$ is the power consumption and $f_{\rm S}$ is the sampling rate. Therefore,the presented ADC achieves a FOM of 0.88 pJ.

The performances of the presented ADC are summarized in Table 1 with comparison to other recently reported 14-bit high-speed pipelined ADCs,which shows that the presented ADC achieves a relatively high ENOB with good power efficiency.

5. Conclusion

This paper presents a 14-bit 100-MS/s pipelined ADC without dedicated front-end SHA. In order to solve the issues of the performance degradation resulted from the dynamic offset generated by clock skew and the comparator offset in the first stage of the presented SHA-less pipelined ADC,a background offset cancellation circuit is proposed to suppress the offset of the comparators in the first-stage sub-ADC,which ensures the overall offset be corrected by the built-in redundancy. Fabricated in a 0.18-$\mu$m CMOS technology,the presented ADC occupies a chip area of 12 mm$^{2}$,and consumes 237 mW from a 1.8-V power supply. Measurement results show that a 71-dB SNDR and an 85.4-dB SFDR are achieved with a 30.1-MHz sine-wave input under a sampling rate of 100 MS/s.