Processing math: 100%
J. Semicond. > 2016, Volume 37 > Issue 3 > 035002

SEMICONDUCTOR INTEGRATED CIRCUITS

A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background

Xiaofei Wang1, , Hong Zhang2, Jie Zhang2, Xin Du2 and Yue Hao1

+ Author Affiliations

 Corresponding author: Wang Xiaofei, Email:xjtuwxf@126.com

DOI: 10.1088/1674-4926/37/3/035002

PDF

Abstract: A 14-bit 100-MS/s pipelined analog-to-digital converter(ADC) without dedicated front-end sample-and-hold amplifier(SHA) is presented. In addition to elaborate matching of the sampling network in the first stage, a background offset cancellation circuit is proposed in this paper to suppress the offset of the comparators in the first-stage sub-ADC, which ensures the overall offset does not exceed the correction range of the built-in redundant structure. Fabricated in a 0.18-μm CMOS technology, the presented ADC occupies a chip area of 12 mm2, and consumes 237 mW from a 1.8-V power supply. Measurement results with a 30.1-MHz input sine wave under a sampling rate of 100 MS/s show that the ADC achieves a 71-dB signal-to-noise and distortion ratio(SNDR), an 85.4-dB spurious-free dynamic range(SFDR), a maximum differential nonlinearity(DNL) of 0.22 LSB and a maximum integral nonlinearity(INL) of 1.4 LSB.

Key words: SHA-lesspipelined ADCclock skewcomparator offsetbackground

In recent years,the fast increase in the data bandwidth of wireless communication systems has driven the development of high-resolution analog-to-digital converters (ADCs) with high sampling rates. Among the variety of ADC architectures,the pipelined ADC is a preferred choice to meet the requirements of these high-speed and high-resolution applications. Traditionally,multi-bit pipelined ADCs are implemented with a sample-and-hold amplifier (SHA) at the front-end[1, 2]. However,the design of the front-end SHA is a very challenging task in high-speed,high-resolution applications due to the stringent tradeoffs between the signal-to-noise ratio (SNR),the linearity,and the power dissipation. Because the front-end SHA is essentially a switched-capacitor sample-and-hold circuit followed by a unit-gain buffer,it is possible to integrate the SHA into the first-stage multiplying digital-to-analog converter (MDAC) to form the so-called SHA-less pipelined ADC,which has an obvious advantage of low power consumption due to the elimination of the high-performance opamp in the dedicated front-end SHA[3]. However,critical problems of SHA-less pipeline architecture are the front-end sampling clock skew and the offset of the comparators in the first-stage sub-ADC[4, 5, 6]. In SHA-less pipelined ADCs,especially for those employing a multi-bit first stage to reduce power consumption,the skew of the front-end sampling clock together with the comparator's offset in the sub-ADC of the first stage generate a large dynamic offset at high input frequencies,which would lead to missing code when the overall offset exceeds the built-in redundancy of the pipelined architecture. Therefore,dedicated circuit design techniques must be employed to reduce the clock skew and comparator offset to ensure the residue of the first stage does not exceed the input range of the second stage.

Many research works have been carried out to solve the dynamic offset issues caused by the skew of the front-end sampling clock and the comparator offset. A straightforward method for solving the skew problem is to match elaborately the sampling networks of the MDAC and the comparators[3]. This method is effective for low speed ADC with low frequency input signals. However,for ADCs with over 100-MS/s sampling rates,the devices in the sampling networks and the comparators are usually designed with a small size to ensure high-speed conversion,which results in large comparator offset in the sub-ADC and brings difficulties to match the sampling network. Another technique is to dynamically calibrate the clock skew of the sampling network in the first stage[5],in which an additional comparator is used to monitor the first-stage residue voltage. If the residue voltage exceeds a given reference voltage,the delay in the clock path of the MDAC or the sub-ADC is adjusted accordingly by a calibration block to obtain a small clock skew. This method can calibrate the offset caused by the clock skew effectively,but cannot deal with the comparator offset,which may result in conversion failures especially for multi-bit stage architectures. Comparator offset calibration methods in References [8, 9] use a negative feedback circuit to adjust the current injecting to the output loads of the preamp in the comparator and reduce the offset significantly,but the additional current sources used to adjust the offset slow down the operation speed of the comparator and deteriorate the clock skew issues. Therefore,these methods are not suitable for SHA-less pipelined ADCs that require high-speed operation of comparators. Cancellation of comparator offset for SHA-less pipelined ADC is addressed in Reference [9],but the detailed implementation of the comparator with offset cancellation is not expressed wherein.

In this paper,a 14-bit,100-MS/s pipelined ADC without dedicated SHA is presented. The ADC adopts a 3-bit first stage to reduce power consumption,which shows a much more narrow tolerable dynamic offset than a traditional 1.5-bit stage. In addition to elaborate matching of sampling network,a background offset cancellation circuit is proposed to reduce the offset of the comparators in the first-stage sub-ADC. In a short period inserted in the sampling phase of the comparator,a charge-pump based offset detection circuit generates a pair of calibration signals to adjust the substrate voltage of the differential load transistors in the preamplifier of the comparator. Very low offset of the comparator can be obtained because of the negative feedback loop operating in the background,which ensures the overall offset of the first stage be corrected by the built-in redundancy of the pipelined ADC. Section 2 describes the architecture of the ADC. Section 3 covers the details of circuit design for the main building blocks. Section 4 presents the measurement results and finally Section 5 concludes the paper.

It is well known that eliminating the dedicated SHA not only eliminates its power,but also its noise contribution. This allows the rest of the stages in the pipeline ADC to use smaller capacitors for a given noise budget,which further saves power consumption. Also,eliminating the SHA makes the ADC easier to drive,since for a given noise budget,the first stage of the pipeline can use a smaller sampling capacitor[3]. The linearity of the front-end sampling circuit is also improved,because smaller switches with less nonlinear parasitic in the input sampling network can be used for smaller sampling capacitor. Additionally,using a multi-bit first stage has been shown to offer significant power savings for high-resolution pipelined ADCs at the cost of increased circuit complexity[4].

Based on the above considerations,an SHA-less architecture with a multi-bit first stage is adopted for the presented ADC,as shown in Figure 1. In order to achieve optimum trade-off between power dissipation,device matching,and design complexity,the first two stages of the pipeline ADC are designed as 3-bit stages,followed by eight 1.5-bit stages and a final 3-bit flash stage. Both the flash and the MDAC in stage-1 simultaneously sample the input signal and the quantized output of the flash drives the MDAC to produce the residue signal. Because the nominal gain of the MDAC is 4 for the 3-bit first stage,it offers a redundancy of 1 bit to tolerate the dynamic offset generated by the sampling clock skew and the comparator offsets. As can be seen,there is also a 1-bit overlap (redundancy) for digital error correction between each two neighboring stages. This gives a total of 15 internal bits out of the digital error correction block,of which only 14 bits are used. The last bit is used to implement a foreground calibration of the capacitor mismatch according to the algorithm in Reference [6].

Figure  Fig1.  Architecture of the presented ADC.

As seen from Figure 1,a dedicated comparator offset cancellation block is employed in stage-1 to ensure the overall dynamic offset does not exceed the correction range. A detailed description of this comparator offset cancellation block is given in the following section. Although not shown in Figure 1,there are also a bandgap-based reference voltage generator and a clock generator,which provide the required reference voltages and two-phase,non-overlapping clock signals for the MDAC and the comparators,respectively.

The structure of the 3-bit first stage of the presented ADC and the timing of the control signals are shown in Figures 2(a) and 2(b),respectively. The MDAC op-amp and the switching network are shown on top of the one out of the eight flash comparators given in the dash box. For simplicity,only a single-ended version is represented,although the implementation is fully differential. Because there is no dedicated SHA in the architecture,the capacitors CS[7:0] and C1 are charged by the input signal VIN simultaneously in the tracking phase,ϕ1P. The skew in the sampling clock will generate a dynamic offset voltage VSKEW,between the sampled results of the MDAC and the comparator,as shown in Figure 2(c). Obviously,the value of VSKEW increases with the frequency of the input signal. In order to ensure high linearity,the switches used to sample VIN are realized as bootstrapped switches[4],as shown in Figure 2(a). In the phase of ϕ2,the 8 comparators generate conversion results through comparing VIN with given reference voltages after the rising edge of ϕ2D. In the same phase,the 8-bit output data of the comparators are used to control the corresponding DAC switches,which connect the bottom plates of CS[7:0] to the correct reference voltage (VBOT or VTOP). The obtained residue voltage on the common top plates of CS[7:0] is amplified by the residue amplifier with a nominal gain of 4.

Figure  Fig2.  The 3-bit first stage. (a) Conceptual structure. (b) Timing of the control clock signals. (c) Impact of the sampling clock skew.

The ideal residue voltage transfer curve of the 3-bit first stage is expressed by the solid lines in Figure 3. As can be seen,the sub-ADC generates 9 levels because 8 comparators are used. Although the encoded output of the first stage has 4 bits,the most significant bit (MSB) is only used to indicate the over-range case of the input signal. Therefore,the first stage is essentially a 3-bit stage[3]. As the gain of the residue amplifier is 4,the ideal maximum value of VRES is VREF/2,which offers one-bit redundancy to the dynamic offset of the stage. With a VREF of 1V,the allowable maximum dynamic offset of the stage can be calculated as 125 mV. If the overall offset voltage exceeds this value,VRES will exceed the correction range,resulting in conversion failure,as shown in Figure 3. Because the total dynamic offset is the sum of the offset generated by clock skew,VSKEW,and the comparator offset,VOFFSET,circuit design should ensure

|VOFFSET+VSKEW|<VREF23.
(1)

Figure  Fig3.  Residue voltage transfer curve with effect of comparator offset and clock skew for the 3-bit first stage.

In order to meet the requirement of Equation (1),the skew of the sampling clock network and the comparator offsets must be reduced extensively. In circuit implementation,the schematic and layout design for the switches and capacitors in the sampling path are elaborately matched to realize low clock skew,as shown in Figure 2(a). However,as the sampling rate of this paper is up to 100 MS/s,the transistor in the switches and the comparators are designed with small sizes to ensure high speed operations,which limits the matching performances to a given extent. Therefore,a background comparator offset cancellation circuit is proposed to obtain small enough overall dynamic offsets for the first stage,which is discussed in the following sub-section.

The schematic of the proposed comparator with background offset cancellation is shown in Figure 4(a),which is composed of a switched-capacitor front-end,an analog block consisting of a pre-amplifier (preamp) and a latch,an output stage,and an offset cancellation circuit. The timings of the control clock signals are given in Figure 4(b).

Figure  Fig4.  Proposed comparator with background offset cancellation. (a) Schematic. (b) Control timing.

As seen from Figure 4,in the tracking phase (ϕ1P and ϕ1 are high),capacitors C1P,C1N and C2P,C2N sample the differential input voltages,VIN+,VIN,and the differential reference voltages,VREF+,VREF,through the switches S1-S6,respectively. When ϕ2 is high,the differential difference between the value of VIN sampled at the falling edge of ϕ1P and VREF is generated on the right plates of the capacitors (VX+,VX). It can be calculated that the differential voltage of VX+ and VX in the ϕ2 phase is

VX+VX=(VIN+VIN)(VREF+VREF)2.
(2)

The obtained difference between VIN and VREF is amplified to a larger value by the preamp in the ϕ2 phase. After the rising edge of ϕ2D,the amplified difference is regenerated to the power (or ground) rail by the latch,and the comparison results are obtained at the outputs of G1 and G2,which are also used for decoding and D/A conversion in the MDAC.

The proposed offset calibration is operated in the tracking phase when ϕ1P and ϕ1 are high. As shown in Figure 4(b),two additional clock signals ϕCAL and ϕCS are designed to control the offset cancellation process. When ϕ1P is high,both VX+ and VX are driven by VCM. In the reset period when ϕCAL is high,the outputs of the latch (V1O+ and V1O) are reset to the same voltage,while in the cancellation period when ϕCAL is low,V1O+ and V1O are regenerated to VDD or ground according to the offset in the comparator. The results of V1O+ and V1O are sampled by the 2 DFFs (G3 and G4) at the rising edge of ϕCS to generate the digital control signals VC+ and VC. Because ϕCAL is always low when ϕ2 is high,the offset sampling process has no effect on the normal operation of the comparator.

Ideally,if there is no offset in the comparator,VC+ (or VC) will generate “1" and “0" alternatively with equal possibilities. However,if the referred-to-the-input (RTI) offset is positive and larger than a given value,VC+ will output constant “1",and VCwill output constant “0" at every rising edge of ϕCS. On the other hand,if the RTI offset is negative,VC+ and VC will output constant “0" and “1",respectively. Therefore,the digital states of VC+ and VC indicate the polarity of the RTI offset,but have no information about the amount of the offset.

In order to cancel the comparator offset with the help of VC+ and VC,a negative feedback network based on a charge pump is proposed,as shown in Figure 4(a). The transistors MC4 and MC5 in the charge pump are biased with VB4 and VB5,providing a current sink and a current source,respectively. The signals VC+ and VC control the charging and discharging of the capacitor CC through the switches MC6 and MC7,respectively. The difference between the output voltage of the charge pump,VPUMP,and a given reference voltage,VB2,is amplified by a low-gain differential amplifier to generate a pair of differential control signals,VA+ and VA,which are used to adjust the substrate voltage of the load transistors,M4 and M5,of the preamp. Therefore,the offset sampling circuit and the charge-pump based offset cancellation circuit form a negative feedback structure.

It can be deduced that VC+ (or VC) will toggle between “1" and “0" after the negative feedback system locks to its stable state,which means that the offset of the comparator is reduced to a very small value. Because the overall structure can be thought of as a first-order feedback system in the vicinity of locking,it is always able to approach the locked state with the proper selection of circuit parameters,such as the value of VB2,and the gain and operation point of the error amplifier.

The simulated curves on the critical nodes with an artificially added RTI offset of 10 mV and -10 mV are given in Figures 5(a) and 5(b),respectively. The simulation is carried out with a clock frequency of 100 MHz. In both cases,because VPUMP is initialized to a very low value,VA+ is much larger than VA at the beginning. Therefore,VC+ output constant “1" after the start of the cancellation process,which charges CC and results in a steady increase in VPUMP. The system approaches to a locked state in a short time,and VC+ toggles between “0" and “1" alternatively for both cases,which means the offsets are cancelled to very low values. In Figure 5(a),VA+ is larger than VA after being locked because the RTI offset is 10 mV,while in Figure 5(b),VA+ is lower than VA because the added RTI offset is -10 mV.

Figure  Fig5.  Simulated offset cancellation results of the proposed comparator with (a) 10 mV and (b) -10 mV RTI offset.

The simulation results show that the proposed circuit is able to cancel the comparator offset effectively in the background at very high speed,and this is because the calibration circuits add very little loads to the main comparator. The only price is some increase in power and circuit area consumption. However,compared to the power and area saving due to the eliminating of the front-end SHA,the proposed circuit is still very power and area efficient.

In order to ensure high gain,large swing and good linearity for the residue amplifier in the first stage,a two-stage operational transconductance amplifier (OTA) with Miller-compensation is employed[4],with a simplified schematic shown in Figure 6. The first stage uses PMOS inputs with a telescopic structure and the second stage is a differential pair with NMOS inputs. As analyzed in Reference [4],the first stage with PMOS inputs can achieve good trade-off between 1/f noise and power consumption. Separate switched-capacitor common-mode feedback (CMFB) circuits are designed both for the first and second stages to ensure stable operation of the OTA with a high common-mode rejection ratio.

Figure  Fig6.  Simplified schematic of the first-stage residue amplifier.

The simulated residue curves of the 3-bit first stage with a -1 to 1 V ramp input signal is given in Figure 7 (VREF is 1 V),which verifies the proper operation of the first stage. As the clock skew and offsets due to layout and fabrication mismatches are not accounted for in the simulation,the residue curve is almost bounded in the range of -0.5 to 0.5 V.

Figure  Fig7.  Simulated residue curve of the first stage without clock skew and comparator offset.

The presented pipelined ADC is fabricated in a 1P6M 0.18-μm CMOS technology with metal-insulator-metal (MIM) capacitors. The micrograph is shown in Figure 8,and the chip area is 3 × 4 mm2 . As can be seen,because the performance of the 3-bit first stage is most important for the ADC,it consumes the largest area among other blocks. The bias currents and device sizes for the subsequent stages are scaled down along the pipeline to save chip area and power consumption. The presented ADC consumes 237 mW from a 1.8-V power supply.

Figure  Fig8.  (Color online) Chip photo of the presented ADC.

In order to verify the effectiveness of the proposed comparator with background offset cancellation,the dynamic performances are measured with the offset cancellation turned on and off,respectively. The measurements are carried out with an input signal of 30.1 MHz sine wave under a sampling rate of 100 MS/s. The measured spectrum with the offset cancellation circuit turned off is shown in Figure 9(a),which shows that the signal-to-noise and distortion ratio (SNDR) and the spurious- free dynamic range (SFDR) are only 55.4 dB and 77.8 dB,respectively. As stated above,the poor dynamic performances are mainly resulted from the large overall dynamic offsets in the first stage. As the comparators in the first stage are designed with small sizes to realize high-speed operation,their intrinsic offsets are relative large. The measured spectrum with the comparator offset cancellation circuit turned on is shown in Figure 9(b),which shows that the SNDR and the SFDR are improved to 70.2 dB and 85.4 dB by the proposed offset cancellation circuit,respectively,corresponding to an effective-number-of-bit (ENOB) of 11.4 bit.

Figure  Fig9.  Measured spectrum with a 30.1 MHz sine input under sampling rate of 100 MS/s. (a) Offset cancellation turned off. (b) Offset cancellation turned on.

The measured differential nonlinearity (DNL) and integral nonlinearity (INL) with offset cancellation turned on is shown in Figures 10(a) and 10(b),respectively. The presented ADC achieves a maximum DNL of 0.22 LSB and a maximum INL of 1.4 LSB.

Figure  Fig10.  Measured (a) DNL and (b) INL.

To evaluate the efficiency of the presented ADC,the figure of merit (FOM) is calculated with the definition[1]:

FOM=P2ENOBfS,
(3)
where P is the power consumption and fS is the sampling rate. Therefore,the presented ADC achieves a FOM of 0.88 pJ.

The performances of the presented ADC are summarized in Table 1 with comparison to other recently reported 14-bit high-speed pipelined ADCs,which shows that the presented ADC achieves a relatively high ENOB with good power efficiency.

Table  1.  Performance summary and comparison.
DownLoad: CSV  | Show Table

This paper presents a 14-bit 100-MS/s pipelined ADC without dedicated front-end SHA. In order to solve the issues of the performance degradation resulted from the dynamic offset generated by clock skew and the comparator offset in the first stage of the presented SHA-less pipelined ADC,a background offset cancellation circuit is proposed to suppress the offset of the comparators in the first-stage sub-ADC,which ensures the overall offset be corrected by the built-in redundancy. Fabricated in a 0.18-μm CMOS technology,the presented ADC occupies a chip area of 12 mm2,and consumes 237 mW from a 1.8-V power supply. Measurement results show that a 71-dB SNDR and an 85.4-dB SFDR are achieved with a 30.1-MHz sine-wave input under a sampling rate of 100 MS/s.



[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
Fig1.  Architecture of the presented ADC.

Fig2.  The 3-bit first stage. (a) Conceptual structure. (b) Timing of the control clock signals. (c) Impact of the sampling clock skew.

Fig3.  Residue voltage transfer curve with effect of comparator offset and clock skew for the 3-bit first stage.

Fig4.  Proposed comparator with background offset cancellation. (a) Schematic. (b) Control timing.

Fig5.  Simulated offset cancellation results of the proposed comparator with (a) 10 mV and (b) -10 mV RTI offset.

Fig6.  Simplified schematic of the first-stage residue amplifier.

Fig7.  Simulated residue curve of the first stage without clock skew and comparator offset.

Fig8.  (Color online) Chip photo of the presented ADC.

Fig9.  Measured spectrum with a 30.1 MHz sine input under sampling rate of 100 MS/s. (a) Offset cancellation turned off. (b) Offset cancellation turned on.

Fig10.  Measured (a) DNL and (b) INL.

DownLoad: CSV
DownLoad: CSV
DownLoad: CSV

Table 1.   Performance summary and comparison.

DownLoad: CSV
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
1

A 10 bit 200 MS/s pipeline ADC using loading-balanced architecture in 0.18 μm CMOS

Linfeng Wang, Qiao Meng, Hao Zhi, Fei Li

Journal of Semiconductors, 2017, 38(7): 075003. doi: 10.1088/1674-4926/38/7/075003

2

A 430 mW 16 b 170 MS/s CMOS pipelined ADC with 77.2 dB SNR and 97.6 dB SFDR

Hui Zhang, Dan Li, Lei Wan, Hui Zhang, Haijun Wang, et al.

Journal of Semiconductors, 2016, 37(3): 035003. doi: 10.1088/1674-4926/37/3/035003

3

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

Nan Zhao, Qi Wei, Huazhong Yang, Hui Wang

Journal of Semiconductors, 2014, 35(9): 095009. doi: 10.1088/1674-4926/35/9/095009

4

A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC

Shubin Liu, Zhangming Zhu, Yintang Yang, Lianxi Liu

Journal of Semiconductors, 2014, 35(5): 055008. doi: 10.1088/1674-4926/35/5/055008

5

A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB

Ke Wang, Chaojie Fan, Jianjun Zhou, Wenjie Pan

Journal of Semiconductors, 2013, 34(8): 085015. doi: 10.1088/1674-4926/34/8/085015

6

A 12-bit, 40-Ms/s pipelined ADC with an improved operational amplifier

Wang Yu, Yang Haigang, Yin Tao, Liu Fei

Journal of Semiconductors, 2012, 33(5): 055004. doi: 10.1088/1674-4926/33/5/055004

7

SHA-less architecture with enhanced accuracy for pipelined ADC

Zhao Lei, Yang Yintang, Zhu Zhangming, Liu Lianxi

Journal of Semiconductors, 2012, 33(2): 025010. doi: 10.1088/1674-4926/33/2/025010

8

A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

Lei Qianqian, Lin Min, Chen Zhiming, Shi Yin

Journal of Semiconductors, 2011, 32(4): 045006. doi: 10.1088/1674-4926/32/4/045006

9

A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

Yang Jinda, Wang Xianbiao, Li Li, Cheng Xu, Guo Yawei, et al.

Journal of Semiconductors, 2011, 32(8): 085005. doi: 10.1088/1674-4926/32/8/085005

10

Hierarchical distribution network for low skew and high variation-tolerant bufferless resonant clocking

Xu Yi, Chen Shuming, Liu Xiangyuan

Journal of Semiconductors, 2011, 32(9): 095011. doi: 10.1088/1674-4926/32/9/095011

11

A robust and simple two-mode digital calibration technique for pipelined ADC

Yin Xiumei, Zhao Nan, Sekedi Bomeh Kobenge, Yang Huazhong

Journal of Semiconductors, 2011, 32(3): 035001. doi: 10.1088/1674-4926/32/3/035001

12

A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC

Yin Rui, Liao Youchun, Zhang Wei, Tang Zhangwen

Journal of Semiconductors, 2011, 32(2): 025006. doi: 10.1088/1674-4926/32/2/025006

13

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-μm CMOS

Zhang Zhang, Yuan Yudan, Guo Yawei, Cheng Xu, Zeng Xiaoyang, et al.

Journal of Semiconductors, 2010, 31(9): 095014. doi: 10.1088/1674-4926/31/9/095014

14

An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

Zhang Zhang, Yuan Yudan, Guo Yawei, Cheng Xu, Zeng Xiaoyang, et al.

Journal of Semiconductors, 2010, 31(7): 075006. doi: 10.1088/1674-4926/31/7/075006

15

A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

Chen Lijie, Zhou Yumei, Wei Baoyue

Journal of Semiconductors, 2010, 31(11): 115006. doi: 10.1088/1674-4926/31/11/115006

16

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

Cai Xiaobo, Li Fule, Zhang Chun, Wang Zhihua

Journal of Semiconductors, 2010, 31(11): 115007. doi: 10.1088/1674-4926/31/11/115007

17

A novel low-voltage operational amplifier for low-power pipelined ADCs

Fan Mingjun, Ren Junyan, Guo Yao, Li Ning, Ye Fan, et al.

Journal of Semiconductors, 2009, 30(1): 015009. doi: 10.1088/1674-4926/30/1/015009

18

A CMOS Dynamic Comparator for Pipelined ADCs with Improved Speed/Power Ratio

Liu Ke, Yang Haigang

Journal of Semiconductors, 2008, 29(1): 75-81.

19

Alloy Temperature Dependence of Offset Voltage and Ohmic Contact Resistance in Thin Base InGaP/GaAs HBTs

Yang Wei, Liu Xunchun, Zhu Min, Wang Runmei, Shen Huajun, et al.

Chinese Journal of Semiconductors , 2006, 27(5): 765-768.

20

A Novel Clock Feedthrough Frequency Compensation forFast-Settling of Folded-Cascode OTA

Ning Ning, Yu Qi, Wang Xiangzhan, Dai Guanghao, Liu Yuan, et al.

Chinese Journal of Semiconductors , 2006, 27(10): 1737-1741.

1. Wang, L., Meng, Q., Zhi, H. et al. A 10 bit 200 MS/s pipeline ADC using loading-balanced architecture in 0.18 μm CMOS. Journal of Semiconductors, 2017, 38(7): 075003. doi:10.1088/1674-4926/38/7/075003
  • Search

    Advanced Search >>

    GET CITATION

    Xiaofei Wang, Hong Zhang, Jie Zhang, Xin Du, Yue Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. Journal of Semiconductors, 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002
    X F Wang, H Zhang, J Zhang, X Du, Y Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. J. Semicond., 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002.
    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 3824 Times PDF downloads: 78 Times Cited by: 1 Times

    History

    Received: 25 July 2015 Revised: Online: Published: 01 March 2016

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Xiaofei Wang, Hong Zhang, Jie Zhang, Xin Du, Yue Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. Journal of Semiconductors, 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002 ****X F Wang, H Zhang, J Zhang, X Du, Y Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. J. Semicond., 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002.
      Citation:
      Xiaofei Wang, Hong Zhang, Jie Zhang, Xin Du, Yue Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. Journal of Semiconductors, 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002 ****
      X F Wang, H Zhang, J Zhang, X Du, Y Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background[J]. J. Semicond., 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002.

      A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background

      DOI: 10.1088/1674-4926/37/3/035002
      Funds:

      Project supported by the National Natural Science Foundation of China(No.61474092).

      More Information
      • Corresponding author: Wang Xiaofei, Email:xjtuwxf@126.com
      • Received Date: 2015-07-25
      • Accepted Date: 2015-09-07
      • Published Date: 2016-01-25

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return