1. Introduction

Dynamic logic circuits are widely used in modern digital VLSI circuits because of the supreme speed and area characteristics of dynamic CMOS logic circuits over static CMOS logic circuits. However, dynamic CMOS logic circuits have less immunity to noise and increased power dissipation than a static CMOS logic circuit. The lower value of the noise margin makes dynamic CMOS logic circuits more sensitive to noise as compared to the static CMOS logic circuit. With the increasing rigorous noise requirement and leakage current due to hostile technology scaling, the noise tolerance and less leakage dynamic circuits have to be improved for reliable operation of VLSI system designed using very deep submicron process technology. As technology scales down the leakage current increases, therefore, as there is continued scaling of the transistor dimensions in the nanoscale regime, a circuit design is required which mitigates leakage current.

In this paper domino logic and DOIND logic based circuits are used to analyze different parameters. The proposed DOIND logic technique has less leakage current as compared to domino logic circuit. The organization of this paper is as follows. Section 2 describes the previous work related to leakage reduction in the domino logic circuit. Section 3 describes the DOIND logic and its characteristics. Section 4 presents the simulation results followed by the conclusion in Section 5.

2. Related work

There are several techniques to control leakage current at transistor level design in domino logic circuits. Body biasing is one effective technique for leakage current reduction in submicron VLSI systems.

The INDEP approach^[1] is the technique which mitigates the leakage current in nanoscale circuits. This technique has two extra inserted transistors between pull up and pull down networks, which are input logic dependent. This technique is used for static CMOS circuits and offers a sufficient delay penalty.

The sleepy keeper approach^[2] uses two weak keeper transistors which are connected parallel to the sleep transistors and the gate terminals of both sleepy keepers are controlled by the output voltage. This technique reduces delay and area as compare to the sleepy stack approach^{[10, 11]} but has additional dynamic power dissipation.

Dual threshold voltage domino logic^[3] has low threshold voltage transistors and high threshold voltage transistors. Low threshold voltage transistors are connected in a critical path which improve the performance and high threshold voltage transistors are connected in a non critical path to mitigate the leakage current. This technique effectively reduces leakage power dissipation, but has a lower noise margin.

Dual threshold voltage with sleep switch domino logic^[4] has the same configuration as dual threshold voltage domino logic except an extra high threshold voltage transistor is connected between the dynamic node and ground. This technique is used to reduce leakage current in sleep mode.

The variable threshold voltage keeper^[5] is another leakage reduction technique for domino logic circuits. In this technique the threshold voltage of the keeper transistor is dynamically modified by using body biasing to reduce the power and it also enhances the speed of the domino logic circuit. Noise immunity also improves as compared to the standard domino logic circuit, but it required extra circuitry to generate body bias voltage.

Leakage biased domino circuit^[6] maintains the high speed of the circuit with fine grain leakage reduction. This technique reduces by several fold the steady state leakage current as compared to the low Vth domino logic circuit.

A hybrid circuit^{[7, 9]} is presented for an XOR/XNOR gate which reduces leakage power, dynamic power and layout area as compared to a standard dynamic circuit, but has a considerable delay penalty.

3. DOIND logic

For high performance integrated circuits the critical paths are often implemented with domino logic circuits. The operating principles of domino logic circuits are reviewed in this section. To reduce the leakage current in the domino logic circuit proposed, DOIND logic is also reviewed.

3.1 Domino logic circuit

A standard domino logic circuit is shown in Figure1. The operation of domino circuit is as follows.

(1) When the clock signal is low, the domino logic circuit is in the precharge phase. During the precharge phase, the node N1 is charged to $V_{\rm dd}$ through MP1. $V_{\rm out}$ of the circuit is low which turns on the keeper transistor (MP2).

(2) When the clock signal is high, the circuit enters into the evaluation phase. In this phase according to the input combination of pull down network dynamic node N1 is discharged to ground or remains high.

(3) The inverter output voltage can also make at most one transition during the evaluation phase from 0 to 1.

To avoid a cascading and charge sharing problem, the inverter and weak keeper transistor are respectively used^{[12, 13]}. The performance of the circuit degrades by adding the keeper transistor. Upsizing the keeper transistor improves the robustness at the cost of delay and power dissipation and a small sized keeper is desired for high speed application. Hence there is a trade-off between delay and power for improved noise and leakage immunity^[14].

3.2 DOIND logic circuit

A proposed DOIND (domino logic with clock and input dependent transistors) logic circuit^[18] is shown in Figure2. It has two DOIND transistors MPD (PMOS) and MND (NMOS) connected between node X and node Y. The gate terminal of DOIND transistors (MPD and MND) are $V_{0}$ and $V_{1}$ which are clock and input logic dependent respectively. The Body terminal of all PMOS transistors is connected to $V_{\rm dd}$ and the Body terminal of all NMOS transistors is connected to Gnd. The operation of the DOIND logic circuit is as follows.

(1) When the clock signal is low, $V_{0}$ is 0 (low) so that MP1 and MPD are turned on and the DOIND logic circuit comes in the precharge phase.

(2) During the precharge phase, the node N1 is charged to $V_{\rm dd}$ through MP1 and MPD. $V_{\rm out}$ of the circuit is low which turns on the keeper transistor (MP2).

(3) When the clock signal is high, the circuit enters into the evaluation phase. In the evaluation phase, input logic for $V_{1}$ depends on the input combination of the pull down network.

(4) For example, in buffer logic when input $V_{\rm in}$ $=$ 1 (high) then $V_{1}$ should be 1 (MND $=$ ON) so that dynamic node N1 becomes 0 and when input $V_{\rm in}$ $=$ 0 (low) then $V_{1}$ should be 0 (MND $=$ OFF) so that dynamic node N1 becomes 1.

As the DOIND approach forms a stacking effect^[8] hence there is a reduction in leakage current. Figure3 shows the different pull down networks for different circuits for both domino and DOIND logic. If we assume, in the pull down network input NMOS transistor is MN2 then the operating status of each transistor for DOIND logic based buffer logic is given in Table1.

Figure4 shows DC characteristics of domino logic and DOIND logic based CMOS buffer in which the graph clearly shows that the DOIND logic based circuit has a better response and improved noise marginas compared to the domino logic based circuit.

Pseudo codes for different DOIND logic for the selection of inputs of DOIND transistors are given as:

Pseudo code of DOIND Buffer logic for selection of V0 and V1 signals

Input: A; primary input signal,

Output: Vout: a Boolean logic output where high logic $=$ `1' and low logic $=$ `0',

V0, V1: DOIND transistors input signals.

if Clk $=$ `0'

V0 $=$ V1 $=$ `0'

else

if (A $=$ `0') then

V0 $=$ `1'

V1 $=$ `0'

Vout $=$ `0'

else

V0 $=$ `1'

V1 $=$ `1'

Vout $=$ `1'

end if

end if

end

Pseudo code of AND2 DOIND logic for selection of V0 and V1 signals

Input: {A, B}: primary input signals,

Output: Vout: a Boolean logic output where high logic $=$ `1' and low logic $=$ `0',

V0, V1: DOIND transistors input signals.

if Clk $=$ `0'

V0 $=$ V1 $=$ `0'

else

if (A $=$ B) then

if (A $=$ `0') then

V0 $=$ `1'

V1 $=$ `0'

Vout $=$ `0'

else

V0 $=$ `1'

V1 $=$ `1'

Vout $=$ `1'

end if

else

V0 $=$ `1'

V1 $=$ `0'

Vout $=$ `0'

end if

end if

end

Pseudo code of OR2 DOIND logic for selection of V0 and V1 signals

Input: {A, B}: primary input signals,

Output: Vout: a Boolean logic output where high logic $=$ `1' and low logic $=$ `0',

V0, V1: DOIND transistors input signals.

if Clk $=$ `0'

V0 $=$ V1 $=$ `0'

else

if (A $=$ B) then

if (A $=$ `0') then

V0 $=$ `1'

V1 $=$ `0'

Vout $=$ `0'

else

V0 $=$ `1'

V1 $=$ `1'

Vout $=$ `1'

end if

else

V0 $=$ `1'

V1 $=$ `1'

Vout $=$ `1'

end if

end if

end

Pseudo code of XOR2 DOIND logic for selection of V0 and V1 signals

Input: {A, B}: primary input signals,

Output: Vout: a Boolean logic output where high logic $=$ `1' and low logic $=$ `0',

V0, V1: DOIND transistors input signals.

if Clk $=$ `0'

V0 $=$ V1 $=$ `0'

else

if (A $=$ B) then

V0 $=$ `1'

V1 $=$ `0'

Vout $=$ `0'

else

V0 $=$ `1'

V1 $=$ `1'

Vout $=$ `1'

end if

end if

end

Pseudo code of Half Adder DOIND logic for selection of V0, V1, V2 and V3 signals

Input: {A, B}: primary input signals,

Output: {Carry, Sum}: Boolean logic outputs where high logic $=$ `1' and low logic $=$ `0',

V0, V1, V2, V3: DOIND transistors input signals.

if Clk $=$ `0'

V0 $=$ V1 $=$ V2 $=$ V3 $=$ `0'

else

if (A $=$ B) then

if (A $=$ `0') then

V0 $=$ `1'

V1 $=$ `0'

V2 $=$ `1'

V3 $=$ `0'

Carry $=$ `0'

Sum $=$ `0'

else

V0 $=$ `1'

V1 $=$ `1'

V2 $=$ `1'

V3 $=$ `0'

Carry $=$ `1'

Sum $=$ `0'

end if

else

V0 $=$ `1'

V1 $=$ `0'

V2 $=$ `1'

V3 $=$ `1'

Carry $=$ `0'

Sum $=$ `1'

end if

end if

end

The circuits for the 1-bit half adder based on domino logic and DOIND logic are given in Figures 5 and 6 respectively.

4. Simulation results

The TSPICE simulator is used for extraction of domino logic and DOIND logic based combinational circuits with a supply voltage of 1 V. All the simulation data were obtained at 70 nm technology node. The channel width and channel length are the same for NMOS transistors which are equal to the technology node and channel width of all PMOS is 2X the channel length except the keeper transistor. The channel length of the keeper transistor is 5X and width is 2X the technology node for the buffer, AND and OR logics, and the channel length of the keeper transistor in XOR logic is 10X and the width is 2X the technology node. The 50 MHz clock frequency ($f)$ has been taken for the simulation. Different simulated data for 2 input AND, OR, XOR and Half Adder are given in Tables 2, 3 and 4.

4.1 Effect on leakage current

For a low leakage current in the deep submicron CMOS circuit designing scaling of the supply voltage is the most effective technique. However, a reduction in $V_{\rm dd}$ decreases the performance of the circuit and to maintain performance the threshold voltage ($V_{\rm th})$ is also reduced. This reduction in $V_{\rm th}$ causes the leakage currents to increase exponentially and it becomes a significant contributor to the total power dissipation of the circuit. The supply voltage ($V_{\rm dd})$ scaling threshold voltage ($V_{\rm th})$ also scales, which causes performance degradation with some leakage current penalty. The relation between leakage current and threshold voltage is given by^{[15, 16]}:

$$\eqalign{ & {{\text{I}}_{{\text{Leakage}}}} = {{\text{I}}_{\text{0}}}\frac{{{\text{(}}{{\text{V}}_{{\text{gs}}}} - {{\text{V}}_{{\text{th}}}}{\text{)}}}}{{\eta {V_t}}}\left( {1 - \exp \frac{{ - {V_{ds}}}}{{{V_t}}}} \right), \cr & \eta = 1 + \frac{{{C_d}}}{{{C_{ox}}}}, \cr}$$

(1)

where $I_{0}$ is saturation current, $V_{\rm gs}$ is gate to source voltage, $V_{\rm t}$ is thermal equivalent voltage, $V_{\rm ds}$ is drain to source voltage, $\eta$ is sub-threshold slope factor, $C_{\rm d}$ is the depletion layer capacitance of the source/drain junction, and $C_{\rm ox}$ is the gate oxide capacitance.

Figures 7(a)-7(d) show that the DOIND logic circuit has less leakage current as compared to the domino logic circuit for different logic circuits with both Clock = 0 and Clock = 1. From Table2, the optimal leakage current state of AND, OR, XOR and Half Adder are {clock=0, input=(0, 0)} for both domino and DOIND logic except DOIND based XOR {clock=0, input=(1, 1)}. The DOIND approach decreases the average leakage current 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively, as given in Table3.

4.2 Effect on static power

Figures 8(a)-8(d) show that the DOIND logic circuit has less static power dissipation as compared to the domino logic circuit for different logic circuits with both Clock = 0 and Clock = 1. From Table2, the optimal static power state of AND, OR, XOR and Half adder are {clock=0, input=(0, 0)} for both domino and DOIND logic except DOIND based XOR {clock=0, input=(1, 1)}. The DOIND approach decreases the average static power 22.36%, 23.16%, 61.42% and 59.92% for 2 input AND, OR, XOR and Half Adder respectively, which are given in Table3.

4.3 Effect on static energy

The static energy component is proportional to $V_{\rm dd}$ whereas the dynamic energy component is proportional to the square of $V_{\rm dd}$. The static and dynamic energy componentsare given by^[17]:

$${{\text{E}}_{{\text{dynamic}}}} = \alpha {{\text{C}}_{\text{L}}}{\text{V}}_{dd}^2,$$

(2)

$${{\text{E}}_{{\text{static}}}} = {{\text{I}}_{{\text{leakage}}}}{{\text{V}}_{{\text{ddTdelay}}}},$$

(3)

where $\alpha$ is transition activity, $C_{\rm L}$ is load capacitance, $I_{\rm leakage}$ is leakage current, and $T_{\rm delay}$ is circuit delay.

Figures 9(a)-9(d) show that for AND, static energy is less for the DOIND logic circuit for all possible combinations with both Clock = 0 and Clock = 1 as compared to the domino logic circuit. From Table2, the static energy for DOIND logic in OR logic is more for all input combinations if Clock = 0 and Clock = 1 except {clock = 1, input = (0, 0)}. For XOR logic, the static energy is less for the DOIND logic circuit for both Clock = 0 and Clock = 1 as compared to the domino logic circuit except {clock = 0, input = (1, 0)} and {clock = 0, input = (0, 1)}. For the Half adder, the static energy is high for the DOIND logic circuit for Clock = 0 and low for Clock = 1 for all input combinations as compared to the domino logic circuit.

From Table3, saving of average static energy for the DOIND approach is 66.43%, $-365.79$%, 7.74% and 2.06% for 2 input AND, OR, XOR and Half Adder respectively.

4.4 Effect on dynamic power

Dynamic power is proportional to the square of $V_{\rm dd}$. The dynamic power component is given by^[17]:

${{\text{P}}_{{\text{dynamic}}}} = \alpha {{\text{C}}_{\text{L}}}{\text{f V}}_{dd}^2{\text{ }}$

(4)

Figure10 shows that dynamic power is less for the DOIND logic circuit as compared to the domino logic circuit for AND and OR logic and high for XOR and Half Adder. From Table4, saving of dynamic power for the DOIND approach is 21.75%, 2.82%, $-11.16$% and $-11.02$% for 2 input AND, OR, XOR and Half Adder respectively given in Table4.

4.5 Effect on dynamic EDP and dynamic PDP

To design an energy efficient circuit in low power, the application energy delay product and power delay product are important parameters. The EDP and PDP of any circuit should be as small as possible for low power circuit design.

Dynamic energy delay product (EDP) and dynamic power delay product (PDP) are given by:

${\text{ED}}{{\text{P}}_{{\text{dynamic}}}} = {{\text{E}}_{{\text{dynamic}}}} \times {{\text{T}}_{{\text{delay}}}},$

(5)

${\text{PD}}{{\text{P}}_{{\text{dynamic}}}} = {{\text{E}}_{{\text{dynamic}}}} \times {\text{Clock frequency}} \times {\text{Tdelay}}{\text{.}}$

(6)

Figure11 shows that dynamic EDP for the DOIND logic circuit and domino logic circuits. Dynamic EDP and Dynamic PDP are given in Table4. It can be observed that EDP and PDP are more for the DOIND logic circuit as comparable to domino logic for all circuits except AND logic. EDP and PDP for DOIND logic increase because the delay of circuit dominates energy as EDP is a function of delay and energy and PDP is a function of delay and dynamic power.

4.6 Delay analysis

From Table4 it is observed that the DOIND logic circuit has some delay penalty as comparable to the domino logic circuit. The DOIND approach has a delay penalty of 27.88% for the buffer as comparable to the domino logic approach. The DOIND approach also has delay penalties of 6.82%, 28.02%, 76% and 73.79% for 2 input AND, OR, XOR and Half Adder respectively. The delay for the DOIND approach based XOR and Half Adder is large as compared to buffer, AND and OR because XOR and Half Adder contains PMOS in the pull down networks.

4.7 Area analysis

The layout of the domino logic based buffer and DOIND logic based buffer is shown in Figures 12 and 13 respectively. It is observed that the approximate area of the domino logic based buffer and DOIND logic based buffer are 2.24 and 2.59 $\mu$m$^{2}$ respectively. The area penalty of the proposed technique is 13.51% as compared to the domino logic for the buffer circuit. This area penalty is the maximum and is in the buffer circuit. As we increase the number of input or the complexity of the circuit, the area penalty will decrease. The penalty of the area in any DOIND approach based logic circuit is only because of two extra transistors. The area penalty is inversely proportional to the number of the input variables.

4.8 Power delay area product (PDAP) analysis

Table5 presents that the improvement in power delay and area product (PDAP) of the DOIND logic based buffer is 47.76% as compared to the domino logic based buffer.

5. Conclusion

This paper presents the comparative analysis of different parameters for domino logic and DOIND logic based 2 input AND, OR, XOR and Half Adder circuits. The DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively.

The DOIND approach decreases the average static power by 22.36%, 23.16%, 61.42% and 59.92% for 2 input AND, OR, XOR and Half Adder respectively. The saving of average static energy for the DOIND approach is 66.43%, $-365.79$%, 7.74% and 2.06% for 2 input AND, OR, XOR and Half Adder respectively.

The dynamic power is less for the DOIND logic circuit as compared to the domino logic circuit for AND and OR logic and high for XOR and Half Adder. The savings of dynamic power for the DOIND approach are 21.75%, 2.82%, $-11.16$% and $-11.02$% for 2 input AND, OR, XOR and Half Adder respectively.

EDP and PDP are more for the DOIND logic circuit as compared to domino logic for all circuits except AND logic. A dominating delay factor is responsible for the increase in EDP and PDP. The maximum area penalty is 13.51% for the DOIND logic based buffer circuit as compared to the domino logic circuit. For the proposed logic circuit PDPA is also improved as compared to the domino logic circuit.