J. Semicond. > 2016, Volume 37 > Issue 6 > 064006
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SEMICONDUCTOR DEVICES

Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

Huoxi Xu1 and Jingping Xu2,

+ Author Affiliations

 Corresponding author: Jingping Xu, Email: 799904108@qq.com

DOI: 10.1088/1674-4926/37/6/064006

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Abstract: LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1×1011 eV-1cm-2), gate leakage property (3.6×10-3 A/cm2 at Vg=1 V+Vfb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.

Key words: Ge MOS capacitor, La2O3, N or/and Ti incorporation, interface properties, k value

Germanium (Ge) has attracted extensive attention as a promising candidate of channel material for high-performance metal-oxide-semiconductor (MOS) field effect transistors because of its high intrinsic carrier mobility. High permittivity (high-k) oxides, such as HfO2[1-3], ZrO2[4], Al2O3[5, 6], and TiO2[7], have been coupled with Ge substrates as gate dielectrics to further scale down the size of the devices. However, high-k oxide/Ge structure generally suffers from the dilemma related to thermodynamic and electrical compatibility due to the parasitically grown Ge oxide (GeOx) at the oxide/Ge interface[8, 9], which leads to a large amount of defects at/near the interface, thus deteriorating the device performances. It is reported that La2O3 film, when directly in contact with Ge, exhibits many good electrical properties, including small hysteresis and frequency dispersion, and low interface-state densities owing to the formation of stable lanthanum germanate (LaGeO)[10, 11]. However, the low k value of gate dielectric limits the scalability of the device to the smaller equivalent oxide thickness[12]. By simultaneously incorporating titanium (Ti) and nitrogen (N) into La2O3 film[13], a high k value could be obtained because Ti-based oxides have an extremely high relative permittivity and N incorporation could suppress Ge out diffusion to form low k LaGeO. On the other hand, Ti incorporation could deteriorate interface properties due to Ti-induced defects at/near the interface[13-15], but N incorporation could improve the interface quality by suppressing Ge, O inter diffusion to generate extra defects at/near the interface[15, 16]. So, it is still an issue which dielectric is more suitable for Ge MOS devices among LaON, LaTiO and LaTiON. Therefore, in this work, N or/and Ti is/are incorporated into La2O3 by the sputtering method to fabricate Ge MOS capacitors with LaON, LaTiO or LaTiON as the gate dielectric and their electrical properties are carefully investigated. It is found that the electrical properties of these devices are closely associated with N or/and Ti incorporation. Among the devices, LaTiON/Ge capacitors exhibit the highest k value, and relatively better interface quality, gate leakage property and device reliability. So, LaTiON is a promising high-k gate dielectric for high-performance Ge MOS devices.

Sb-doped n-type (100) Ge wafers with a resistivity of 0.10-0.11 Ω·cm were used as substrates to fabricate MOS capacitors. The wafers were cleaned in organic solvents followed by a rinse in de-ionized water and diluted HF (1, :, 50) for several cycles. After N2 drying, the wafers were immediately transferred into a sputtering chamber. LaON film (~8 nm) was deposited on the Ge substrate by sputtering a La2O3 target at a power of 30 W in Ar and N2 at room temperature (denoted as LON sample). LaTiO and LaTiON films (~7.5 nm) were also deposited on Ge substrate by reactive co-sputtering a La2O3 target at a power of 30 W and a Ti target at a power of 17.4 W in Ar or in Ar and N2 (denoted as LTO and LTON samples, respectively). For comparison, a control sample with La2O3 (~7.5 nm) as the gate dielectric was prepared by sputtering a La2O3 target at a power of 30 W in Ar (denoted as LO sample). Then, all the samples received post-deposition annealing (PDA) at 500 ℃ for 5 min in N2. Then, Al was evaporated and patterned as the gate electrode with an area of 7.85×10-5 cm2. Finally, forming-gas annealing was carried out at 300 ℃ for 20 min to achieve better electrical contacts. After the samples fabrication, the gate-leakage current was measured by using an HP4156A precision semiconductor parameter analyzer. High-frequency (HF, 1 MHz) capacitance-voltage (C-V) characteristics were measured by an HP4284A precision LCR meter. High-field stress (10 MV/cm for 3600 s), with the capacitors biased in accumulation by the HP 4156A, was used to examine the device reliability in terms of flat-band voltage shift and gate-leakage current increase. Transmission electron microscopy (TEM) was used to observe the interface between the dielectrics and Ge. The physical thickness of the gate dielectrics was determined by a multi-wavelength ellipsometer and TEM. All electrical measurements were carried out under electrically-shielded and light-tight conditions at room temperature.

Presented in Figures 1(a)-1(c) are the cross-sectional TEM pictures of LO (La2O3/Ge), LON (LaON/Ge) and LTON (LaTiON/Ge) samples. It can be seen that an interlayer can be hardly observed at the interface in the three samples. For the LO sample, this should be ascribed to Ge out diffusion into the whole La2O3 bulk to form a stable low-k LaGeO compound during PDA[10, 12], thus suppressing the formation of unstable GeOx. As a result, the LO sample exhibits good-quality interface due to reduced defects at/near the interface[10, 12]. However, for LON and LTON samples, this is probably attributed to N incorporation preventing Ge from out diffusion, thus effectively suppressing the growth of interlayer, similar to the case on Si and GaAs substrates[17, 18]. Comparing the TEM pictures of LON and LTON samples, it can also be seen that the interface of LaTiON/Ge is rougher than that of LaON/Ge. A possible reason is that the incorporated Ti in LaTiON strongly reacts with the Ge substrate at the interface[13-15], similar to the situation of HfTi-based oxides in contact with Ge[15].

Figure  1.  TEM pictures of (a) La2O3/Ge MOS, (b) LaON/Ge MOS and (c) LaTiON/Ge MOS.
DownLoad: Full-Size Img PowerPoint

Typical HF (1-MHz) C-V curves for LO, LON, LTO and LTON samples are shown in Figure 2. Obviously, the C-V curves for LON and LTO samples have the largest and smallest slopes in the depletion region, indicating the leastand most interfacial traps created in these two samples, respectively. The more interfacial traps of LTO sample than LO sample should be mainly associated with Ti incorporation, which could react with the Ge substrate, as mentioned above, thus generating excessive interfacial defects. The fewer interfacial traps of the LON sample than the LO sample could be explained by the fact that N incorporation could inhibit Ge out diffusion or La, O in diffusions, thus suppressing the generation of interfacial defects. Therefore, the interfacial traps created in the LTON sample are less than those in the LO and LTO samples, but more than that in the LON sample due to N-induced interfacial defects decreasing and Ti-induced interfacial defects increasing, as supported by the slope of the C-V curve for the LTON sample in Figure 2, which is larger than those for LO and LTO samples, but smaller than that for the LON sample The values of interface-state densities (Dit) near the midgap extracted from the HF C-V curves using Terman's method[19] of the samples are listed in Table 1. The Dit of the LTO sampleis larger than that of the LO sample, implying a worse interface quality. This should be mainly associated with the reaction between Ti and the Ge substrate. The smaller Dit of the LON sample than the LO sample indicates a better interface quality, which should be due to N incorporation suppressing Ge and La, O inter diffusions. As a result, the LTON sample exhibits a relatively smaller Dit of 3.1×1011 eV-1cm-2 (larger than that of the LON sample, but smaller than those of LTO and LO samples) because of simultaneously incorporating Ti and N, which is even smaller than the Dit (5.4×1011 eV-1cm-2) of HfTiON gate dielectric Ge MOS capacitor using TaON/GeON dual interlayer[20]. The LON and LTO samples exhibitthe smallest and largest Dit, respectively (1.2×1011 versus 7.1×1011 eV-1cm-2).

Figure  2.  High-frequency (1-MHz) C-V curves for the LO, LON, LTO and LTON samples.
DownLoad: Full-Size Img PowerPoint
Table  1.  Parameters of the Ge MOS capacitors extracted from HF (1-MHz) C-V curves, and tox is the physical thickness of gate dielectric measured by ellipsometry.
Sampletox (nm)Cox (pF)CET (nm)Vfb (V)Qox (cm-2) Dit (eV-1cm-2)k
LO7.511082.50.23-1.03×10123.3×101111.7
LON8.051292.10.19-8.5×10111.2×101114.9
LTO7.542091.30.47-6.15×10127.1×101122.7
LTON7.552271.20.34-4.3×1012 3.1×101124.6
DownLoad: CSV  | Show Table

The values of accumulation capacitance (Cox), k value and capacitance equivalent thickness (CET) are also listed in Table 1. The LTON sample shows the largest Cox, implying the largest k value (24.6) and thus the smallest CET (1.2 nm). This should be attributed to the extremely high k value of Ti-based oxide and suppressed formation of low-k LaGeO, because N incorporation could suppress Ge and La, O interdiffusions. The k values of LON and LTO samples (14.9 versus 22.7) are smaller than that of the LTON sample because these two samples are incorporated only by N or Ti. The negative equivalent oxide-charge density (Qox) of LO and LTO samples should mainly result from the large Dit plus Ge diffusion into the dielectric, while the negative Qox of LON and LTON samples should be mainly ascribed to the acceptor-like interface traps. The higher Qox of Ti-incorporated samples (LTO and LTON) than their no Ti-incorporated counterparts (LO and LON) should be mainly attributed to the higher interface trap charges and Ti-induced oxide charges near the interface. The lower Qox of N-incorporated samples (LON and LTON) than their no N-incorporated counterparts (LO and LTO) should be mainly due to N incorporation blocking Ge out diffusion.

The gate leakage properties of the samples are depicted in Figure 3. It can be seen that the N-incorporated samples (LON and LTON) have a smaller gate leakage current, which should be closely related to the smaller Dit and thus reduced trap assisted tunneling current. The larger gate leakage current of Ti-incorporated samples (LTO and LTON) than their no Ti-incorporated counterparts (LO and LON) should be due to the larger Dit, thus the enhanced trap assisted tunneling current. As a result, LON and LTO samples have the smallest and largest gate leakage current density (Jg) owing to the smallest and largest Dit, respectively (1.2×10-3 versus 2.0×10-2 A/cm2 at Vg= 1V+Vfb). The LTON sample exhibits an acceptably smaller Jg of 3.6×10-3 A/cm2 at Vg=1V+Vfb (larger than that of the LON sample, but smaller than those of LO and LTO samples) due to the relatively smaller Dit.

Figure  3.  Gate-leakage current density versus gate voltage for the LO, LON, LTO and LTON samples.
DownLoad: Full-Size Img PowerPoint

With the capacitors biased in accumulation, a high-field stress at 10 MV/cm for 3600 s is performed on the samples to examine the device reliability. The gate leakage currents and HF C-V curves before and after the stress are measured. The gate leakage current density increase (△Jg) at Vg=Vfb +1 V and the flat-band voltage shift (△Vfb) extracted from the HF C-V curves are shown in Figure 4. It can be seen that the LON sample has the smallest △Jg and △Vfb, which should be ascribed to the best interface quality associated with N incorporation suppressing Ge and La, O inter diffusions. The largest △Jg and △Vfb of the LTO sample should be attributed to the poor interface quality due to Ti-induced defects. The △Jg and △Vfb of the LTON sample are smaller than those of the LTO sample, but larger than those of LO and LON samples owing to the relatively better interface quality.

Figure  4.  Flat-band voltage shift (△Vfb) and gate leakage current density increase (△Jg) at Vg=Vfb + 1V for the LO, LON, LTO and LTON samples after a high-field stress (at 10 MV/cm for 3600 s).
DownLoad: Full-Size Img PowerPoint

The Ge MOS capacitors with LaON, LaTiO or LaTiON as the gate dielectric are prepared by incorporating N or/and Ti into La2O3 using the sputtering method and their electrical properties are carefully compared. Results indicate that the LaON MOS capacitor has the smallest interface-state densities and gate leakage current, the best high-field reliability, but a smaller k value (14.9). The LaTiO MOS capacitor has a higher k value (22.7), but the largest interface-state densities and gate leakage current with the worst high-field reliability. The LaTiON MOS capacitor has the highest k value (24.6), relatively smaller interface-state densities (3.1×1011 eV-1cm-2) and gate leakage current (3.6×10-3 A/cm2 at Vg=1V+Vfb), with a relatively better high-field reliability. Therefore, LaTiON is most suitable for high performance Ge MOS capacitors among the three materials. However, it is worth pointing out that the electrical properties of the LaTiON MOS capacitor strongly depend on Ti incorporation. So, the Ti content must be carefully optimized to achieve a good trade-off among the electrical properties of the devices.



[1]
Robertson J, Wallace R M. High-k materials and metal gates for CMOS applications. Mater Sci Eng R, 2015, 88:1
[2]
Oh I K, Kim M K, Lee J S, et al. The effect of La2O3-incorporation in HfO2 dielectrics on Ge substrate by atomic layer deposition. Appl Surf Sci, 2013, 287:349
[3]
Liu Chen, Zhang Yuming, Zhang Yimen, et al. Temperature dependent interfacial and electrical characteristics during atomic layer deposition and annealing of HfO2 films in p-GaAs metal-oxide-semiconductor capacitors. Journal of Semiconductors, 2015, 36:124003
[4]
Bethge O, Henkel C, Abermann S, et al. Stability of La2O3 and GeO2 passivated Ge surfaces during ALD of ZrO2 high-k dielectric. Appl Surf Sci, 2012, 258:3444
[5]
Bom N M, Soares G V, Krug C, et al. Evolution of the Al2O3/Ge (100) interface for reactively sputter-deposited films submitted to postdeposition anneals. Appl Surf Sci, 2012, 258:5707
[6]
Zhou Jiahui, Chang Hudong, Liu Honggang, et al. MIM capacitors with various Al2O3 thicknesses for GaAs RFIC application. Journal of Semiconductors, 2015, 36:054004
[7]
Xie Q, Deduytsche D, Schaekers M, et al. Implementing TiO2 as gate dielectric for Ge-channel complementary metal-oxide-semiconductor devices by using HfO2/GeO2 interlayer. Appl Phys Lett, 2010, 97:112905
[8]
Fu C H, Chang-Liao K S, Liu L J, et al. An ultralow EOT Ge MOS device with tetragonal HfO2 and high quality HfxGeyO interfacial layer. IEEE Trans Electron Devices, 2014, 61:2662
[9]
Sun Q Q, Shi Y, Dong L, et al. Impact of germanium related defects on electrical performance of hafnium oxide. Appl Phys Lett, 2008, 92:102908
[10]
Mirovic I Z, Althobaiti M, Weerakkody A, et al. Ge interface engineering using ultra-thin La2O3 and Y2O3 films:a study into the effect of deposition temperature. J Appl Phys, 2014, 115:114102
[11]
Lamagna L, Wiemer C, Perego M, et al. O3-based atomic layer deposition of hexagonal La2O3 films on Si (100) and Ge (100) substrates. J Appl Phys, 2010, 108:084108
[12]
Galata S F, Mavrou G, Tsipas P, et al. Metal-oxide-semiconductor devices on p-type Ge with La2O3 and ZrO2/La2O3 as gate dielectric and the effect of postmetallization anneal. J Vac Sci Technol B, 2009, 27:246
[13]
Xu H X, Xu J P, Li C X, et al. Impacts of Ti on electrical properties of Ge metal-oxide-semiconductor capacitors with ultrathin high-k LaTiON gate dielectric. Appl Phys A, 2010, 99:903
[14]
Cheng C L, Horng J H, Wu Y Z. Electrical and reliability characteristics of HfLaTiO-gated metal-oxide-semiconductor capacitors with various Ti concentrations. Device Mater Reliab, 2012, 12:399
[15]
Li C X, Zou X, Lai P T, et al. Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric. Microelectron Reliab, 2008, 48:526
[16]
He G, Sun Z Q, Liu M, et al. Nitrogen dependence of band alignment and electrical properties of HfTiON gate dielectrics metal-oxide-semiconductor capacitor. Appl Phys Lett, 2010, 97:192902
[17]
Kawada N, Ito M, Saito Y. Thermal stability of lanthanum oxynitride ultrathin films deposited on silicon substrates. Jpn J Appl Phys, 2006, 45:9197
[18]
He G, Liu J W, Chen H S, et al. Interface control and modification of band alignment and electrical properties of HfTiO/GaAs gate stacks by nitrogen incorporation. J Mater Chem C, 2014, 2:5299
[19]
Terman L M. An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes. Solid State Electron, 1962, 5:285
[20]
Ji F, Xu J P, Lai P T, et al. Improved interfacial properties of Ge MOS capacitor with high-k dielectric by using TaON/GeON dual interlayer. Electron Device Lett, 2011, 32:122
Fig. 1.  TEM pictures of (a) La2O3/Ge MOS, (b) LaON/Ge MOS and (c) LaTiON/Ge MOS.

DownLoad: Full-Size Img PowerPoint
Fig. 2.  High-frequency (1-MHz) C-V curves for the LO, LON, LTO and LTON samples.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  Gate-leakage current density versus gate voltage for the LO, LON, LTO and LTON samples.

DownLoad: Full-Size Img PowerPoint
Fig. 4.  Flat-band voltage shift (△Vfb) and gate leakage current density increase (△Jg) at Vg=Vfb + 1V for the LO, LON, LTO and LTON samples after a high-field stress (at 10 MV/cm for 3600 s).

DownLoad: Full-Size Img PowerPoint

Table 1.   Parameters of the Ge MOS capacitors extracted from HF (1-MHz) C-V curves, and tox is the physical thickness of gate dielectric measured by ellipsometry.

Sampletox (nm)Cox (pF)CET (nm)Vfb (V)Qox (cm-2) Dit (eV-1cm-2)k
LO7.511082.50.23-1.03×10123.3×101111.7
LON8.051292.10.19-8.5×10111.2×101114.9
LTO7.542091.30.47-6.15×10127.1×101122.7
LTON7.552271.20.34-4.3×1012 3.1×101124.6
DownLoad: CSV
[1]
Robertson J, Wallace R M. High-k materials and metal gates for CMOS applications. Mater Sci Eng R, 2015, 88:1
[2]
Oh I K, Kim M K, Lee J S, et al. The effect of La2O3-incorporation in HfO2 dielectrics on Ge substrate by atomic layer deposition. Appl Surf Sci, 2013, 287:349
[3]
Liu Chen, Zhang Yuming, Zhang Yimen, et al. Temperature dependent interfacial and electrical characteristics during atomic layer deposition and annealing of HfO2 films in p-GaAs metal-oxide-semiconductor capacitors. Journal of Semiconductors, 2015, 36:124003
[4]
Bethge O, Henkel C, Abermann S, et al. Stability of La2O3 and GeO2 passivated Ge surfaces during ALD of ZrO2 high-k dielectric. Appl Surf Sci, 2012, 258:3444
[5]
Bom N M, Soares G V, Krug C, et al. Evolution of the Al2O3/Ge (100) interface for reactively sputter-deposited films submitted to postdeposition anneals. Appl Surf Sci, 2012, 258:5707
[6]
Zhou Jiahui, Chang Hudong, Liu Honggang, et al. MIM capacitors with various Al2O3 thicknesses for GaAs RFIC application. Journal of Semiconductors, 2015, 36:054004
[7]
Xie Q, Deduytsche D, Schaekers M, et al. Implementing TiO2 as gate dielectric for Ge-channel complementary metal-oxide-semiconductor devices by using HfO2/GeO2 interlayer. Appl Phys Lett, 2010, 97:112905
[8]
Fu C H, Chang-Liao K S, Liu L J, et al. An ultralow EOT Ge MOS device with tetragonal HfO2 and high quality HfxGeyO interfacial layer. IEEE Trans Electron Devices, 2014, 61:2662
[9]
Sun Q Q, Shi Y, Dong L, et al. Impact of germanium related defects on electrical performance of hafnium oxide. Appl Phys Lett, 2008, 92:102908
[10]
Mirovic I Z, Althobaiti M, Weerakkody A, et al. Ge interface engineering using ultra-thin La2O3 and Y2O3 films:a study into the effect of deposition temperature. J Appl Phys, 2014, 115:114102
[11]
Lamagna L, Wiemer C, Perego M, et al. O3-based atomic layer deposition of hexagonal La2O3 films on Si (100) and Ge (100) substrates. J Appl Phys, 2010, 108:084108
[12]
Galata S F, Mavrou G, Tsipas P, et al. Metal-oxide-semiconductor devices on p-type Ge with La2O3 and ZrO2/La2O3 as gate dielectric and the effect of postmetallization anneal. J Vac Sci Technol B, 2009, 27:246
[13]
Xu H X, Xu J P, Li C X, et al. Impacts of Ti on electrical properties of Ge metal-oxide-semiconductor capacitors with ultrathin high-k LaTiON gate dielectric. Appl Phys A, 2010, 99:903
[14]
Cheng C L, Horng J H, Wu Y Z. Electrical and reliability characteristics of HfLaTiO-gated metal-oxide-semiconductor capacitors with various Ti concentrations. Device Mater Reliab, 2012, 12:399
[15]
Li C X, Zou X, Lai P T, et al. Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric. Microelectron Reliab, 2008, 48:526
[16]
He G, Sun Z Q, Liu M, et al. Nitrogen dependence of band alignment and electrical properties of HfTiON gate dielectrics metal-oxide-semiconductor capacitor. Appl Phys Lett, 2010, 97:192902
[17]
Kawada N, Ito M, Saito Y. Thermal stability of lanthanum oxynitride ultrathin films deposited on silicon substrates. Jpn J Appl Phys, 2006, 45:9197
[18]
He G, Liu J W, Chen H S, et al. Interface control and modification of band alignment and electrical properties of HfTiO/GaAs gate stacks by nitrogen incorporation. J Mater Chem C, 2014, 2:5299
[19]
Terman L M. An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes. Solid State Electron, 1962, 5:285
[20]
Ji F, Xu J P, Lai P T, et al. Improved interfacial properties of Ge MOS capacitor with high-k dielectric by using TaON/GeON dual interlayer. Electron Device Lett, 2011, 32:122
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    Huoxi Xu, Jingping Xu. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti[J]. Journal of Semiconductors, 2016, 37(6): 064006. doi: 10.1088/1674-4926/37/6/064006
    H X Xu, J P Xu. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti[J]. J. Semicond., 2016, 37(6): 064006. doi: 10.1088/1674-4926/37/6/064006.
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    Received: 23 November 2015 Revised: 23 February 2016 Online: Published: 01 June 2016

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      Article Navigation >  Journal of Semiconductors  > 2016  >  37(6): 064006
      Huoxi Xu, Jingping Xu. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti[J]. Journal of Semiconductors, 2016, 37(6): 064006. doi: 10.1088/1674-4926/37/6/064006 ****H X Xu, J P Xu. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti[J]. J. Semicond., 2016, 37(6): 064006. doi: 10.1088/1674-4926/37/6/064006.
      Citation:
      Huoxi Xu, Jingping Xu. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti[J]. Journal of Semiconductors, 2016, 37(6): 064006. doi: 10.1088/1674-4926/37/6/064006 ****
      H X Xu, J P Xu. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti[J]. J. Semicond., 2016, 37(6): 064006. doi: 10.1088/1674-4926/37/6/064006.
      shu

      Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

      DOI: 10.1088/1674-4926/37/6/064006
      • 1.

        Department of Electronic Information, Huanggang Normal University, Huangzhong 438000, China

      • 2.

        School of Optical & Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China

      Funds:

      the National Natural Science Foundation of China No. 61274112

      the Scientific Research Program of Huanggang Normal University No. 2012028803

      the Natural Science Foundation of Hubei Province No. 2011CDB165

      Project supported by the National Natural Science Foundation of China (No. 61274112), the Natural Science Foundation of Hubei Province (No. 2011CDB165), and the Scientific Research Program of Huanggang Normal University (No. 2012028803).

      More Information
      • Corresponding author: Email: 799904108@qq.com
      • Received Date: 2015-11-23
      • Revised Date: 2016-02-23
      • Published Date: 2016-06-01

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