1. Introduction

With the improvement of CMOS manufacture technologies,the average feature size and the supply voltage in the integrated circuits are downscaled while the working frequency is increased. The effect of low-frequency noise (1f noise) in the semiconductor devices becomes more important,especially in analog applications. These low-frequency noises may be up-converted to high frequencies which is a dominant contributor to phase noise,thus adversely affecting the operation of MOSFETs in wireless LAN and RF applications^{[1, 2]}. Further investigations on accurate modeling and parameter extraction of low-frequency noise for the CMOS transistor in nanometer technology node are essential for analog circuit design simulations.

In addition,low-frequency noise can be utilized in the estimation of device reliability and the diagnosis of defects and failures^{[3, 4]}. Built on the measurement of low-frequency noise,the concentration and distribution of interface state,border traps and oxide trapped charges can be extracted and analyzed. Therefore,dependence of manufacturing processes on the intrinsic electrical characteristics of semiconductor devices can be predicted while the degradation under external stresses also can be characterized. As a non-destructive estimation method,the measurement of low-frequency noise is widely used in the prediction of device reliability and failure,especially in bipolar transistors,MOSFETs,GaN HEMT,thin film transistors and semiconductor laser^[5-7].

Several models were proposed to describe noise behavior in MOSFETs^{[1, 8-10]}. Generally,there are two major existing theories to explain the origins of the low-frequency noise: McWhorter's and Hooge's model. For McWhorter's model,low-frequency noise is caused by carrier number fluctuations due to surface state effect which considers that the low-frequency noise is attributed to the random trapping and de-trapping processes of charges in the oxide traps near the Si-SiO₂ interface. For Hooge's experimental model,low-frequency noise is caused by bulk carrier mobility fluctuation which is induced by fluctuations in the phonon population through phonon scattering. By combining both number and correlated surface mobility fluctuation mechanisms,Hung KK proposed a unified model used in BSIM3^{[11, 12]}. By use of three fitting parameters (NOIA,NOIB and NOIC),the analytical description provides low-frequency noise simulation from weak to strong inversion in the larger MOSFETs. Thereby,it still has some room to investigate the low-frequency noise in the MOSFETs processed in nanometer technology node.

In this paper,low-frequency noises in the n-channel and p-channel MOSFETs processed in 65 nm technology are investigated. The variation of current noise power spectral density versus external voltage is analyzed,thus the density of defects near Si-SiO₂ interface and average Hooge's parameter are extracted. Based on BSIM model,two fitting parameters (NOIA and NOIB) are extracted and then used for the simulation of low-frequency noise characteristics in the nanometer MOSFETs.

2. Noise measurement system and device parameters

2.1 Noise measurement system

In order to measure the MOSFETs drain current noise power spectrum densities (PSD) under different bias conditions,the experimental setup is illustrated in Figure 1. The device under test (DUT) is voltage biased,and its current noises are analyzed by using an SR785 dynamic signal analyzer. The core of this system is the filter and amplifier unit which is also called a 9812B noise analyzer made by Proplus Design Solution,Inc. The unit contains a high-quality RC low-pass filter for removing the source-measure unit noise from B1500. Thus,the DUT bias voltages are very closed to the pure DC signals and free from noise.

2.2 Device parameters

The devices used in this experiment were n-channel and p-channel MOSFETs which were processed in a standard SMIC 65 nm complementary-MOS technology for low-leakage logic applications. This technology offers a dual-gate oxide process for input/output devices and a standard-gate oxide for typical MOSFETs. A leading edge 193 nm lithography process used on critical levels enables aggressive 0.7 × scaling while the direct design migrated from the previous technology node with design rule restriction. In addition,this technology utilizes an advanced low $k$ BEOL integration of eight levels with copper for both wirebond and flip chip package offerings. In this paper,the gate oxide thickness (t_ox) in the DUT is about 1.2 nm. The channel length is 65 nm while the W/L ratio is 100. The nominal operating voltage is 1.2 V. The calculated gate oxide capacitance per unit area (C_ox) is about 2.88 ×10^-6 F/cm².

The transfer characteristics of NMOS and PMOS are shown in Figures 2 and 3. Based on the measurement results,the extracted threshold voltages in the NMOS and PMOS are about 0.46 and -0.52 V,respectively.

The sub-threshold current can be expressed by^{[13, 14]}:

$I_{\rm ds}=I_{\rm D0}{\rm exp}\frac{q(V_{\rm gs}-V_{\rm th})}{\eta KT}\left[1-{\rm exp}\left(-\frac{qV_{\rm ds}}{KT}\right)\right] ,$

(1)

where V_gs is the gate-source voltage,V_ds is the drain-source voltage,I_D0 is the channel current when V_gs is equal to V_th,ηis:

$\eta =\frac{C_{\rm ox} +C_{\rm d} +C_{\rm it} }{C_{\rm ox}},$

(2)

where C_ox,C_d and C_it are gate oxide capacitance,depletion capacitance and interface trap capacitance per unit area,respectively.

The sub-threshold swing (S) can be expressed by:

$S=\frac{\text{d}{{V}_{\text{gs}}}}{\text{d}\lg {{I}_{\text{ds}}}}.$

(3)

By use of,Equation (3),the extracted sub-threshold swing in the NMOS and PMOS are about 89.04 mV/dec and 95.14 mV/dec,respectively. Based on Equations (1) and (3),the relationship between η and S can be expressed by:

$S\cong 2.3V_{\rm t} \left( {\frac{C_{\rm ox} +C_{\rm d} +C_{\rm it} }{C_{\rm ox} }} \right)=2.3V_{\rm t} \eta .$

(4)

By use of Equation (4),the extracted η in the NMOS and PMOS are about 1.48 and 1.59,respectively. Thus,the value of C_ox+C_d+C_it in the NMOS and PMOS can be calculated while it is about 4.26×10^-6 F/cm² and 4.58×10^-6 F/cm²,respectively.

In the deep linear region,the channel current can be expressed by^{[13, 14]}:

$I_{\rm ds,lin} =\mu _{\rm eff} C_{\rm ox} W/L\frac{\left( {V_{\rm gs} -V_{\rm th} } \right)V_{\rm ds} }{1+\left[{\theta +g_{\rm m} \left( {R_{\rm s} +R_{\rm d}} \right)} \right]\left( {V_{\rm gs} -V_{\rm th} } \right)}.$

(5)

By ignoring the parasitical resistance in the source and drain,the extracted effective electron mobility (ueff) is about 60.62 cm²/(V • s) in the NMOS when V_gs is equal to 1 V and V_ds is equal to 0.1 V,while the extracted effective hole mobility (ueff) is about 24.35 cm²/(V•s) in the PMOS when V _gs is equal to -1 V and V_ds is equal to -0.1 V. Low effective mobility extracted is due to carrier scattering effects in the interface near the gate oxide^[14]. When the vertical field exceeds the critical value which is about 5.5 × 10⁵ V/cm,the effective mobility in the devices processed in 65 nm technology node decrease significantly with increasing effective gate voltage.

3. Low-frequency noise characteristics

Low-frequency noise characteristics for NMOS and PMOS were measured in the frequency range of 1 Hz to 100 kHz. For impedance matching between DUT and internal low noise amplifiers during measurement,the R _G in Figure 1 is setting to short (0Ω) due to the high gate impedance while R _D is selected automatically by computer program according to the bias conditions which is 33 or 100 kΩ typically. Measured channel current noise spectral densities (SID) at different gate-source voltages for NMOS and PMOS are shown in Figures 4 and 5.

As shown in Figures 4 and 5,channel current noise power spectral density follows a 1/f^γ law which ascribes to fluctuations of the interfacial oxide charge due to the dynamic trapping and de-trapping of free carriers into slow oxide traps. The values of γ are 0.84 and 1 for NMOS and PMOS,respectively. The frequency exponent γ deviates from 1 if the trap density is not uniform in depth^[16]. γ ＜1 is expected when the trap density is higher close to the gate oxide/silicon interface than that in the interior of the gate oxide,and γ>1 for the opposite case. Based on the extracted results in Figures 4 and 5,the interfacial trap density in the NMOS is larger than that in the gate oxide,while the trap density is uniform in the PMOS.

Noise measurements were performed in the ohmic range as a function of the effective gate voltage at low V _DS biases. Therefore,the normalized channel current noise spectral density versus channel current in the NMOS and PMOS are shown in Figure 6. By considering the carrier number fluctuation mechanism,the normalized channel current noise power spectral density can be expressed by^{[13, 17]}:

$\label{eq6} \frac{S_{\rm ID} }{I_{\rm ds}^2 }=\left( {\frac{g_{\rm m} }{I_{\rm ds} }} \right)^2S_{\rm vfb},$

(6)

where S_vfb is the flat-band voltage noise power spectral density and gm is transconductance. Based on Figure 6,the extracted S_vfb are about 7.5 × 10^-12 V²/Hz and 6 × 10^-11 V²/Hz in the NMOS and PMOS,respectively. By using Equation(6),the fitting results of SID/I _DS² in the NMOS are shown in Figure 6 which shows good agreement with the measured results which also illustrate the main origin of noise in the NMOS is fluctuations of interfacial carrier number. The fitting results of SID/I_DS² in the PMOS also show good agreement with the measured results when the effective gate voltage is near the threshold voltage. However,for larger effective gate voltages,there was considerable diversity between fitting results and measured results when PMOS is operated in the strong inversion region. The above results show low frequency in the PMOS is dominated by carrier number fluctuation mechanism in the sub-threshold region while it is dominated by carrier mobility fluctuation mechanism in the strong inversion region.

The relationship between S_vfb and the trap density close to the SiO₂/Si interface can be expressed by^{[9, 18]}:

$N_{\rm t} =\frac{WL\left( {C_{\rm ox} +C_{\rm d} +C_{\rm it} } \right)^2f}{q^2KT\lambda }S_{V_{\rm fb} },$

(7)

where λ is the tunnel attenuation distance (about 0.1 nm in the gate oxide). Therefore,estimation of average trap density close to the SiO₂/Si interface is deduced from Equation (7) and gives N_t=3.94×10¹⁷ cm^-3eV^-1 for NMOS and N_t=3.56×10¹⁸cm^-3eV^-1 for PMOS.

In contrast to McWhorter's carrier number fluctuation theory,Hooge claimed the 1/f noise may originate from noise in lattice scattering,which in turn causes random mobility fluctuation. According to Hooge's empirical law^{[19, 20]},the normalized drain current noise power spectral density (SID/I_DS²) could be expressed by:

$S_{\rm ID} /I_{\rm D}^2 =\frac{\alpha _{\rm H} q}{fWLC_{\rm ox} \left( {V_{\rm gs} -V_{\rm th} } \right)},$

(8)

where a_H is an empirical dimensionless constant which is also called Hooge's parameter. The a_H is technology-/material-dependent and could be considered as a device/material quality indicator. From Equation (8),the values of a_H can be deduced which are about 2.45 × 10^-5 and 4 × 10^-4 for NMOS and PMOS.

As shown in Figure 7,the extracted values of a_H are similar in the PMOS when overdrive voltage is larger than 0.2 V which also illustrates noise in the PMOS is dominated by the mobility fluctuation mechanism. But for NMOS,the extracted values of a_H are decreased with the increment of overdrive voltage which also illustrates noise in the NMOS is dominated by the number fluctuation mechanism.

The Hooge's parameter a_H is frequently used as a figure of merit for the comparison for different device technologies and it is usually low for a higher electronic quality material. As reported by references,the modern IC-graded resistor has the lowest reported a_H (∼10^-6)^[20]. Depending more on sample quality and preparation,a_H for bulk silicon MOSFETs and resistors can have a wide distribution and be as high as 4 × 10^{-4 [21]}. In addition,a_H is about 3×10^-5 to 1 × 10^-2 in the SOI devices ^[22],10^-3 to 10^-2 for poly-Si thin film transistors^[23],10^-3 for indium zinc oxide thin film transistors,2 × 10^-2 to 10^-1 for amorphous silicon thin film transistors^[24] and 10^-2 for organic thin film transistors^[25]. The calculated results in Figure 7 illustrate the quality in these bulk silicon devices are much better than other types of semiconductor devices.

4. Parameter extraction and simulation of low-frequency noise

In the sub-threshold region,low-frequency noise in the MOSFET is dominated by carrier number fluctuation mechanism,thus channel current noise power spectral density S_ID can be expressed by^{[13, 21]}:

$S_{\rm ID} \left( f \right)=\frac{q^4\lambda N_{\rm t} }{KTWLf\left( {C_{\rm ox} +C_{\rm d} +C_{\rm it} } \right)^2}I_{\rm ds}^2.$

(9)

In the BSIM unified compact models,S_ID in the sub-threshold region can be modeled as:

$S_{\rm ID} \left( f \right)=\frac{\mbox{NOIA}\cdot KT}{WLf^{EF}N^{\ast 2}\cdot \left( {1/\lambda } \right)}I_{\rm ds}^2,$

(10)

where N^*=KT/q²(C_ox+C_d+C_it),NOIA and EF are fitting parameters. By use of Equations (9) and (10),NOIA can be deduced and gives NOIA ≈N_t^{[21, 26]}. Therefore,the extracted values of\,NOIA in the NMOS and PMOS are about 3.94 × 10¹⁷ and 3.56 × 10¹⁸ cm^-3eV^-1 respectively,which are similar to the reported values (2.5 × 10¹⁶ and 1.56 × 10¹⁸ cm^-3eV^-1) in the NMOS processed in the 0.8 and 0.25 um technology nodes. Based on Equation (10),noise characteristics in the sub-threshold region for NMOS and PMOS can be simulated by use of extracted NOIA values,which shows good agreement with the measured results.

In the strong inversion region,based on BSIM compact model,S_ID can be expressed by^{[10-13, 21]}:

$\begin{align} & {{S}_{\text{ID}}}=\frac{qKT{{\mu }_{\text{eff}}}{{I}_{\text{ds}}}}{{{C}_{\text{ox}}}{{L}^{2}}{{f}^{EF}}}[\text{NOIA}\cdot \lg \frac{{{N}_{0}}+{{N}^{*}}}{{{N}_{\text{L}}}+{{N}^{*}}}+\text{NOIB}\cdot \left( {{N}_{0}}-{{N}_{\text{L}}} \right) \\ & +\frac{\text{NOIC}}{2}N_{0}^{2}-N_{\text{L}}^{2}]+\Delta {{L}_{\text{clm}}}\frac{KT\cdot I_{\text{ds}}^{2}}{qW{{L}^{2}}{{f}^{EF}}} \\ & \times \frac{\text{NOIA}+\text{NOIB}\cdot {{N}_{\text{L}}}+\text{NOIC}\cdot N_{\text{L}}^{2}}{{{\left( {{N}_{\text{L}}}+{{N}^{*}} \right)}^{2}}},t \\ \end{align}$

(11)

where ΔL_clm is the channel length reduction due to channel length modulation effect,NOIB and NOIC are fitting parameters,N₀ and N_L are the charge densities at the source and drain side respectively which can be expressed by:

$qN_0 =C_{\rm ox} \left({V_{\rm gs} -V_{\rm th} } \right),$

(12)

$qN_{\rm L} =C_{\rm ox} \left[{V_{\rm gs} -V_{\rm th} -\min \left( {V_{\rm ds} ,V_{\rm ds,sat} } \right)} \right].$

(13)

In the deep linear region,low-frequency noises are mostly dominated by mobility fluctuation mechanism and then the fitting parameters NOIA and NOIB can be ignored. By use of Equations (11) and (8),NOIB can be deduced and gives NOIB =q_aH/KT. Thus,the extracted NOIB in the NMOS and PMOS are about 9.31 × 10^-4 and 1.53 × 10^-2 V^-1,respectively. Based on the above extracted NOIB values,low-frequency noise characteristics can be simulated,as shown in Figure 9. For PMOS,the simulated results show good agreement with measured results which illustrate noise measured in the deep linear region for PMOS is dominated by carrier mobility fluctuation mechanism. However,the simulated results for NMOS deviates from the measured results which illustrate noise measured in the deep linear region for NMOS is affected by carrier number fluctuation mechanism. Therefore,the extracted values of NOIB in the NMOS are decreased with the increment of overdrive voltage^[13].

5. Conclusion

Low-frequency noise behaviors in the NMOS and PMOS were investigated in the weak and strong inversion region. The measured results show noises in the NMOS were dominated by number fluctuation mechanism and noises in the sub-threshold region for PMOS were dominated by number fluctuation mechanism while noises in the strong inversion region for PMOS were dominated by mobility fluctuation mechanism. The flat-band voltage noise power spectral densities were extracted and then the trap densities near SiO₂/Si interface were calculated. The average Hooge's parameters were also calculated by considering mobility fluctuation mechanism. Based on BSIM compact model,the extracted values of NOIA and NOIB are constants for PMOS. For NMOS,NOIA is constant and NOIB is decreased with the increment of overdrive voltage. The simulated noise results show good agreement with the measured results by using extracted fitting parameters.