1. Introduction

With the rapid development of integrated circuit technology, the process geometries are shrinking and some new process even make it smaller, like c-CESL^[1]. It has been well recognized that reliability issues are important factors in determining the performance of small-geometry devices. Generally, BTI (bias temperature instability) is of greater practical concern for PMOSFET devices compared to NMOSFET. Some research focuses on PBTI (positive bias temperature instability) of NMOSFET with high-k/metal gate^[2]because the conventional SiO₂/poly-silicon gate has been replaced for 45 nm node and beyond. For 65 nm node, the lifetime of NMOSFET used in radiation environment is not only determined by reliability issues such as hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB), but also by TID effect, because the device suffers total ionizing dose (TID) effect and reliability issues simultaneously^{[3, 4]}. In order to predict the lifetime of a device used in a radiation environment accurately, total dose responses and reliability issues of the device should be considered simultaneously. However, little published literature is available on the combined effect of the above phenomena. In this paper, total dose responses and reliability issues of 65 nm NMOSFETs are studied, and the correlation between radiation damage and reliability issues of devices is analyzed.

This paper is divided into five parts. Section 2 is about samples and bias conditions for total dose irradiation and reliability issues experiments. The influence of radiation and reliability issues on device characteristics of 65 nm NMOSFETs are revealed in Section 3, and the brief mechanisms are discussed. In Section 4, we analyze the correlation between radiation damage and reliability issues of devices from physical mechanism in detail. The results derived from this paper will provide support for lifetime prediction of a nano device in a radiation environment.

2. Device and experimental details

The devices used in this paper were NMOSFETs manufactured by 65 nm CMOS process with different width (W)/length (L) ratios. Total dose irradiation experiments and reliability issues were conducted on these devices. Experimental details are listed in Table 1.

Total dose irradiation experiments were carried out on NMOSFETs by$^{\mathrm{60}}$Co$\gamma$-ray source in Xinjiang Technical Institute of Physics and Chemistry, China Academy of Science, with dose rates of 84 rad(Si)/s. During irradiation, the gate voltage was set to 1.32 V and all other pins grounded. We measured the electrical parameters of devices respectively at the intervals when the total dose accumulated to 100, 300, 500 and 1000 krad(Si).

NMOSFETs with short channel length (W/L=10 µm / 0.06 µm, 0.3 µm / 0.06 µm, and 0.12 µm / 0.085 µm) were selected to proceed to hot-carrier stress experiment, including irradiated and un-irradiated samples. The stress condition was set to channel hot carrier (CHC) stress, that is:$V_{\rm D}=$ 2 V (1.67 times operation voltage),$V_{\rm G}=$ 1 V, all other pins grounded. The stress was interrupted by measuring while accumulative time was 10, 500, 1000, 2000 and 3000 s. Stress duration was 3000 s in total.

According to the “weakest link” model of TDDB, the TDDB lifetime of gate oxide strongly depends on gate area^[5]. So we chose fresh wide channel (W/L= 10 µm / 0.3 µm) and narrow channel (W/L= 0.3 µm / 0.3 µm) NMOSFETs as the samples to TDDB experiment. Unlike traditional constant stress, we applied V-ramp stress to the samples^[6].

3. Results and analysis

3.1 Total ionizing dose effect (TID)

Figures 2 and 3 show the transfer curves of wide channel NMOSFET before and after 1 Mrad(Si) dose of irradiation. On account of the inconspicuous threshold voltage ($V_{\mathrm{th}})$ shift and off-state leakage increase, the impact of irradiation on transfer curve of device at$V_{\mathrm{DS}}=$ 0.1 V is negligible (Figure 2). As shown in Figure 3, the off-state leakage in the transfer curve of the device at$V_{\mathrm{DS}}=$ 1.15 V is increased to 1.6 times of initial value. Experimental results above reveal that radiation has a relatively weak impact on characteristics of 65 nm wide channel NMOSFETs, which is different from previous research at deep submicron scale. The off-state leakage of deep submicron NMOSFET is dramatically increased by irradiation, no matter whether it is a wide channel device or narrow channel device, seen in Figure 4 (data come from Reference ^[7]). Radiation-induced oxide charges trapped in shallow trench isolation (STI) turn on the parasitic transistor of NMOSFETs resulting in off-state leakage in transfer curves of devices^[8].

The difference of TID sensitivity between nano and deep submicron NMOSFETs can be explained by the following three points: (1) the operating voltage of deep submicron device is higher and that generates more oxide charges trapped in STI oxide. (2) Advanced process brings on higher background leakage. That makes off-state leakage more difficult to reveal itself in a nano device. (3) It is harder to make the body region inverse at the advanced process because of the higher doping concentrations.

Lots of research has reported radiation-induced narrow channel effect (RINCE) of deep sub-micron MOSFETs which mainly showed significant threshold shift in the narrow channel device compared with the wide one^[9]. That is considered a result of the charge sharing by radiation-induced oxide charges trapped in STI oxide. Our results are in accord with this phenomenon, as shown in Figure 4. Furthermore, radiation-induced$I_{\mathrm{Dlin}}$, subthreshold swing (S),$G_{\mathrm{m}}$,$I_{\mathrm{Dsat}}$ degradation in narrow channel device, seen in Figures 5-8, is far larger than the wide channel device which was not observed in deep sub-micron MOSFETs. These parameters are directly related to the mobility of channel carriers. The radiation-induced interface traps in STI scatter the carrier and reduce its mobility, and then impact on parameters above. The generation of interface traps usually lags behind the generation of oxide trapped charges in irradiation^[10]. For the deep sub-micron device, the impact of radiation-induced interface traps is suppressed by the oxide trapped charges due to its lower resistance to radiation.

3.2 Reliability issues

3.2.1   Hot carrier injection effect (HCI)

As shown in Figures 9 and 10, the threshold voltage of the wide channel NMOSFET shifts positively with large degradation of$I_{\mathrm{Dlin}}$,$I_{\mathrm{Dsat}}$ and$G_{\mathrm{m\thinspace }}$after 3000 s of CHC stress. With extensive study, the dominant damage type of hot carrier stress on NMOSFET is found to be the creation of interface traps^[11]. When the NMOSFET is ON, the silicon bands are bent, and that makes the energy level of interface traps below Fermi-level and interface traps negatively charged, resulting in positive shift of threshold voltage. Due to the inverse relationship between the mobility of carriers and density of interface traps, the mobility of channel electrons is degraded by hot carrier stress. Then the degradation of channel electron's mobility leads to the reduction of$I_{\mathrm{Dlin}}$,$I_{\mathrm{Dsat}}$ and$G_{\mathrm{m}}$. Furthermore, damage induced by CHC stress in the narrow channel NMOSFET is more serious than in the wide channel device, as shown in Figures 11 and 12, because the longitudinal electric field of the narrow channel NMOSFET is higher and enhances the degradation of parameters^[12].

3.2.2   Time-dependent dielectric breakdown（TDDB）

As shown in Figure 13, the stress started with an initial gate voltage of 2.5 V, each step lasted 100 seconds and then increased by 0.05 V until the gate current increased by two orders of magnitude. The gate oxide breakdown of wide channel NMOSFET took place when gate stress increased to 3.6 V, while delayed to 3.75 V in narrow channel device, as shown in Figures 14 and 15. According to “weakest link” model, the gate oxide can be split into small pieces where the same stochastic process of degradation is taking place in the individual cells^[5]. If one of them breaks, the whole gate oxide is identified as in breakdown. The important practical conclusion is concordant with our result that TDDB is more likely to occur in a device with large gate area. Moreover, the threshold shifts positively, and significant degradation of$I_{\mathrm{Dlin}}$,$G_{\mathrm{M}}$ and$I_{\mathrm{Dsat\thinspace }}$ is observed seen in Figures 14 and 15. We consider that degeneration of these parameters is relevant to negatively charged defects induced by tunneling electrons during TDDB stress.

4. Correlation of irradiation impact and reliability issues

4.1 TID and HCI

The generation mechanism of trapped charges has a marked difference between TID and HCI. Radiation can generate additional electron-hole pairs in oxide. Holes approach the interface, some fraction will be trapped, forming a positive oxide-trap charge^[13]. The whole process is always in oxide. Meanwhile during CHC stress, interface traps are caused by the scattering of channel hot carriers. This procedure is mainly confined to the body region. Another difference between TID and HCI is the function part of trapped charges. For TID, because of their opposite charge, there is a competition between oxide trapped charges and interface states generated by irradiation, although only interface states really count in HCI. Furthermore, the optimum condition for the generation of trapped charges in radiation is different from that in hot carrier effect. For the total dose irradiation, vertical electric field is beneficial to the generation of trapped charge, so the transistor has the largest parameter degradation under ON bias during irradiation. Hot carrier effect requires a large electric field in the channel. Under the large electric field, carriers can be accelerated along the channel and become hot carriers. Then，the most severe bias for HCI is when drain voltage is high and the gate voltage is half of drain voltage.

Irradiation and HCI exhibit consistency in degradation of electrical parameters, for instance, threshold drift towards the positive direction with accumulated dose or stress time. The lifetime of the device may be overestimated if the impact of irradiation and hot carrier stress on characteristics of the device are considered separately. Besides, TID and HCI have similar narrow channel effect. Therefore, the interaction may emerge easier in a small width device.

Figures 18-20 contracts the transfer curve of irradiated and un-irradiated devices before and after CHC stress. We found that previous irradiated NMOSFETs with small width are more serious. That is considered to be under the influence of impact ionization rate and charges at bulk-STI edges^[14].

4.2 TID and TDDB

The impact of radiation on parameters of NMOSFETs originates in radiation-induced trapped charges in STI, but the impact of HCI and TDDB comes from damage in gate oxide. In spite of the similar, most severe bias condition, the trapped charges in TDDB are caused by channel electrons tunneling from channel to gate, which is different from TID. Furthermore, theoretical analysis and test results demonstrate that, unlike aforementioned RINCE in TID, TDDB is more likely to occur with a wide channel.

It is reported that the gate leakage current was reduced during TDDB stress if the device was irradiated^[15]. The radiation-induced trapped charges were considered to be the culprit. It is well known that interface-traps can be positive, neutral, or negative. When the channel is opened, donor-like interface-traps are positively charged in PMOSFETs while other interface-traps are neutral. This portion of radiation-induced traps changes the net barrier height, reducing the gate current during subsequent stress. It can also be interpreted that positive charges impede tunneling of holes. Acceptor-like interface-traps in NMOSFETs have similar effects. The charge to breakdown ( $Q_{\mathrm{BD}}$) is the time integral of the gate current. If$Q_{\mathrm{BD}}$ is constant, lower gate current means longer time to failure, not to mention that irradiated devices display an increase in$Q_{\mathrm{BD }}$^[15]. The increase in the lifetime during stress after irradiation is clear for all of the devices, both PMOSFETs and NMOSFETs. For a nano device, interface-traps are going to have a more important role in parameter degradation.

5. Conclusion

In summary, total dose irradiation has little influence on electrical characteristics of wide channel NMOSFETs. The off-state leakage in transfer curves is only increased to 1.6 times the original value after 1 Mrad dose of irradiation.$V_{\rm th}$ of narrow channel NMOSFETs shift positively by irradiation, while the$V_{\mathrm{th}}$ of the wide channel device has ignored change after irradiation. Radiation-induced$I_{\mathrm{Dlin}}$,$G_{\mathrm{m}}$,$I_{\mathrm{Dsat}}$ degradation in a narrow channel device is far larger than in a wide channel device. Under channel hot carrier stress,$V_{\mathrm{th}}$ has a positive shift, and$I_{\mathrm{Dlin}}$,$G_{\mathrm{m}}$ and$I_{\mathrm{Dsat}}$ of devices are decreased. Narrow channel devices also have larger hot-carrier-induced degradation than wide channel devices, and more importantly, the hot-carrier lifetime is reduced more in a radiation environment. Meanwhile, narrow channel devices have higher breakdown voltage than wide channel devices, which agrees with “weakest link” theory of TDDB. The degradations from irradiation and reliability issues are similar in characteristics and correlate in mechanism. Therefore, simple linear superposition or separately considering these issues is the improper way to predict the service lifetime of a device used in a radiation environment.