Processing math: 100%
J. Semicond. > 2017, Volume 38 > Issue 12 > 123002

SEMICONDUCTOR MATERIALS

Fabrication and modeling of multi-layer metal–insulator-metal capacitors

R Karthik and A Akshaykranth

+ Author Affiliations

 Corresponding author: R Karthik, Email: rayam16@gmail.com

DOI: 10.1088/1674-4926/38/12/123002

PDF

Abstract: This paper presents the fabrication and modeling for capacitance–voltage characteristics of multi-layer metal–insulator–metal capacitors. It is observed that, due the applied electric field, the effective dielectric constant of the stack was increased due to the accumulation of charges at the interface of high-to-low conductance materials. It is observed that the Maxwell–Wagner polarization is dominant at low frequencies (<10 kHz). By introducing carrier tunneling probability of the dielectric stack, the model presented in this paper shows a good agreement with experimental results. The presented model indicates that the nonlinearity can be suppressed by choosing the similar permittivity dielectric materials for fabrication of multilayer metal insulator metal capacitors.

Key words: anodic oxidationdielectrichigh-kmulti-layercapacitance-voltageMaxwell-Wagnercapacitor

Metal–insulator–metal (MIM) capacitors are attractive passive elements for analog and mixed signal applications. Some sensitive circuits, such as A/D converter ICs, expect a very low variation of capacitance with voltage of less than 100 ppm/V2. In this regard, high-k dielectric stack MIM capacitors have been proposed by many authors recently[14]. It is observed that the voltage coefficient of capacitance (VCC) is higher at low frequencies than at high frequencies. This is due to migration and accumulation of charges at the interface of dielectrics. Such accumulated charges polarize for the applied field; such mechanism is referred as Maxwell–Wagner (MW) polarization[5].

Maxwell–Wagner polarization is observed in many ferroelectric mixtures or heterostructures[610]. The accumulation of charges at the interface of heterostructures for the applied field lead to enhancement of effective permittivity[8]. A giant dielectric constant of ~1000 was achieved with ALD TiO2/ Al2O3 nanolaminates by Wei Li et al.[11]. Because of MW polarization, each TiO2/Al2O3 interface accumulation yields a high dielectric constant of 750 times greater than that of Al2O3. Recently, MW effect was found in an MOS device by Jinesh et al.[12]. It is worth noting that the MW charge accumulation is observed in forward bias only, i. e., the charge injection from high conductive to low conductive high-k material[13]. The approach of imaginary permittivity ε" to ∞ in forward bias at low frequencies indicates the presence of MW polarization[12]. However, models developed in these reports have ignored the dependence of applied potential across the dielectric stack.

Many reports are available on the modeling of dependence of capacitance with voltage for single-layer dielectric MIM capacitors[13]. However, modeling of capacitance–voltage characteristics of bilayer or multilayer MIM capacitors are not reported yet as per our knowledge. In this paper, we have developed a model for voltage dependence of bilayer dielectrics MIM capacitor using MW polarization. This model accounts for the carrier tunneling probability of dielectric stack and MW relaxation time of accumulated interfacial charges. A good agreement was found between the model and the measured capacitance–voltage characteristics of TiO2/Al2O3 MIM capacitors. It is observed that the MW polarization is significant in low frequencies of <10 kHz.

A 100 nm SiO2 was grown by dry oxidation at a temperature of 1100 °C for about 30 min on Si substrate and thoroughly cleaned by deionized water. Over that, a bilayer of 15 nm Ti on 100 nm Al was deposited using an electron beam evaporator with tungsten filament at a pressure of 8 × 10−5 mBar. This Ti/Al film was anodized potentiostatically using non-aqueous solution of ammonium pentaborate dissolved in ethylene glycol (20 g/L) by the same size of platinum cathode. Oxidation was done for various anodization voltages of 25 V (Sample 1) and 30 V (Sample 2) till the anodization current density reduces to 1 μA/cm2. Only three-quarters of the sample area were dipped in the electrolyte to avoid etching for the bottom electrode. This forms a barrier type anodic bilayer TiO2/Al2O3 at lower and higher anodization voltages, respectively. After cleaning thoroughly by deionized water, a 50 nm thick Al top electrode was deposited on the samples using thermal evaporation with the shadow mask area of ~0.61 mm2. Samples 1 and 2 are bilayer TiO2/Al2O3 MIM capacitors. SEM cross-sections of the samples 1 and 2 are shown in Fig. 1. Due to the delamination of TiO2 from bottom Al2O3 at higher anodization voltages, the anodization voltage was restricted to 30 V (> 30 V, not shown).

Figure  1.  SEM cross section image of anodized region before top elec-trode deposition. (a) Sample 1 (AV = 25 V). (b) Sample 2 (AV = 30 V).

Fig. 2 shows the depth profile of the two samples using secondary ion mass spectrometry (SIMS) in positive mode with 1 kVCs. 30 kV gallium ion was used as the primary ion during the SIMS measurement. It shows ion distribution of Ti, Al, O, Si, Ti–O and Al–O. It is observed that the inward migration of oxygen ion increases, which forms a thin layer of Al2O3. It is also observed that outward migration of Al into TiO2 is increased, which increases the thickness of AlTiO composite layer. Fig. 3 shows the X-ray diffraction patterns of the anodized samples. It is observed that the crystalline phases of TiO2 anatase and rutile are present at all anodization voltages. Also, the crystalline Al2O3 (γ-Al2O3) emerges at 2θ = 65.5° for both the samples. The migration of oxygen and evolution of electrons into Al region increases and forms bilayer TiO2/Al2O3 with a thin layer of crystalline Al2O3 near TiO2/Al2O3 interface[13]. The capacitance and leakage current density were measured using semiconductor parameter analyzer (HP4155C). The measured leakage current density as a function of applied voltage for all the samples is reported in our earlier work[13].

Figure  2.  (Color online) SIMS depth profile of all samples. (a) Sample 1. (b) Sample 2.
Figure  3.  (Color online) X-ray diffraction spectra of anodized samples at various anodization voltages. (a) 25 V. (b) 30 V. (A: Anatase, R: Rutile)

It has been observed that most of the samples are showing a high degree of asymmetry at forward and reverse biases and leakage current of Sample 1 and Sample 2 drastically reduces. These are due to formation of AlTiO interfacial layer and TiO2/Al2O3 stack. A detailed discussion of leakage characteristics and conduction mechanism of this bilayer MIM capacitors are reported in Ref. [13].

Consider a bilayer MIM structure as shown in Fig. 4(a). The layers consist of two dielectric materials with distinct relative dielectric constant of εr1 and εr2 with thickness of d1 and d2 respectively. Each layer's conductivity and relaxation time are represented as σn and τn, respectively, for n = 1, 2. Fig. 4(b) shows the equivalent RC network of bilayer MIM structure. Here R1 & C1 and R2 & C2 are individual resistance & capacitance of layer-1 and layer-2 respectively. CMW is interfacial capacitance, also called “Maxwell–Wagner capacitance”, which is significant at low frequencies. To calculate the charge density of dielectric interface, Maxwell’s time varying accumulation process at pure insulator interface is considered. This charge density is used to calculate the interfacial capacitance, named CMW. The values of R1 and R2 are ignored to calculate the total capacitance value due to their high values. The total capacitance can be expressed as,

Figure  4.  Schematic of bilayer configuration. (a) Layer specification. (b) Equivalent circuit at low frequencies.

Ctotal(VB)=(1C1+1C2)1+CMW(VB),

(1)

where MW capacitance can be calculated by CMW = A q2NMW where q is charge of an electron and A is top electrode area of capacitor[14]. According to MW theory of double layer[14, 15], the accumulated charge density at the interface as a function of applied potential and time is expressed as[14],

NMW=ε0ε1σ2ε2σ1d1σ2+d2σ1Vstack(1et/τMW).

(2)

Here Vstack is voltage across the bilayer dielectric stack for the applied bias voltage VB; t is time of measurement and τMW is relaxation time of double layer. The accumulated interface charges and native traps build up potential, which opposes the applied field and reduces flow of charges, so the potential across the stack can be written as Vstack=|VBVbi| . Here Vbi is built in potential at interface due to accumulated interface charges. This MW time constant (τMW) of double layer can be expressed as,

τMW=ε2d1+ε1d2d1σ2+d2σ1.

(3)

If the measurement time t is greater than τMW, then the third term of Eq. (2) can be eliminated. Therefore, Eq. (2) can be rewritten as,

NMW=εoεr1σ2+εr2σ1d2σ1+d1σ2|VBVbi|.

(4)

We know τ1=ε1σ1 , τ2=ε2σ2 and G1=σ1d1 , G2=σ2d2 . By substituting these in Eq. (4),

NMW=G1G2G1+G2[τ1τ2]|VBVbi|.

(5)

G1, G2, τ1, τ2 are defined as the conductance and relaxation time of layer 1 and layer 2. Here G1G2G1+G2=G , where G is the total conductance of bilayer. Therefore, Eq. (5) can be reduced to,

NMW=G[τ1τ2]|VBVbi|.

(6)

The total conductance G is a frequency sensitive term. It is expressed as G=ωC0ε , where C0 is the capacitance at zero bias, ε" is imaginary part of dielectric permittivity. ε" of bilayer dielectric stack can be expressed as[5],

ε=1+ω2[τMWτ1+τMWτ2τ1τ2]ωC0(R1+R2)[1+ω2τ2MW],

(7)

thus Eq. (5) becomes,

NMW=1+ω2[τMWτ1+τMWτ2τ1τ2]R1+R2[1+ω2τ2MW][τ1τ2]|VBVbi|.

(8)

The compatibility of proposed model with measured capacitance for the applied voltages at various frequencies is shown in Figs. 5(a) and 5(b) for samples 1 and 2 respectively.

Figure  5.  MW C–V model (without tunneling probability) and measured C–V fitting compatibility for samples. (a) Sample 1. (b) Sample 2.
Table  1.  Fitting parameters of Maxwell–Wagner capacitance model.
Sample d1 (nm) d2 (nm) εr1 εr2 σ1 (pS/cm) σ2 (fS/cm) Φ1 (eV) Φ2 (eV) Vbi (eV)
Sample 1 15 7 90 9 15 2 3.3 2.3 1
Sample 2 15 10 90 9 15 4 3.3 2.3 1.2
DownLoad: CSV  | Show Table

Table 1 shows the parameters adopted for fitting this model with measured capacitance. Since the Eq. (8) has linear relationship of applied voltage with accumulated charge density, it has not got a good fit with measured C–V characteristics. This is due to the ignorance of charge migration between dielectric materials. According to Maxwell and Wagner, the dielectric layers are thick and pure insulators that do not conduct. But the fabricated bilayer nanostructured thin films have sufficiently large conductivity. The migration of charges for the applied potential can be incorporated into Eq. (8). To incorporate this realistic situation, tunneling probability has been added using trap-assisted tunneling model[17]. Therefore Eq. (8) can be rewritten as,

NMW(Vb)=q21+ω2τMWτ1+τMWτ2(τ1τ2)(R1+R2)(1+ω2τ2MW)(τ1τ2)×|(VbVbi){1exp[(qVstackϕ1+ϕ2+ϕtϕii)/kBT]}|,

(9)

where ϕ1, ϕ2, ϕii, ϕt, kB, and T are the barrier height at Al/TiO2 interface, barrier height at Al2O3/TiO2 interface, trap barrier height of insulator/insulator interface traps, barrier height of traps, Boltzmann constant and temperature respectively. Compatibility of the model is shown in Figs. 6(a) and 6(b) along with model with tunneling probability. The proposed model with tunneling probability is showing a better fit with measured data. MW effect of permittivity enhancement in bilayer MIM capacitors leads to increase in VCC at low frequencies. It is observed that the ratio of permittivity of both dielectric materials determines the MW capacitance. For instance, TiO2/Al2O3 shows a capacitance enhancement of twice compared to series capacitance of bilayer in our experiments. At the same time, sandwich of TiO2 and Al2O3 multilayer stack shows a giant dielectric constant of > 500 times of single layer MIM structure [11]. Therefore, the dependence of capacitance with voltage can be reduced by choosing the materials with less Rdi, such as ZrO2/HfO2 (29/25 = 1.6) and HfO2/Al2O3 (29/9 = 3.22).

Figure  6.  MW C–V model (with tunneling probability) and measured C–V fitting compatibility for samples. (a) Sample 1 (10 kHz). (b) Sample 2 (1 kHz).

Capacitance–voltage characteristics of bilayer MIM capacitors are deduced from Maxwell approach on accumulation of charges at dielectric interface. With Wagner equation on space charge polarization, the voltage dependence of dielectric enhancement is derived. The model shows good agreement with experiment. It was observed that the Maxwell– Wagner polarization occurs at low frequencies and largely depends on field direction. The charge built-up due to tunneling and accumulation has added more accuracy compared to the ideal case. Physics and modeling of capacitance–voltage characteristics of MIM capacitors are useful to analyze the origin of nonlinearities, formation of capacitance, and frequency dependence, and dielectric relaxation in MIM capacitors.

The authors would like to acknowledge the Science and Engineering Research Board, India for financial support.



[1]
He Z X, Daley D, Bolam R, et al. High and low density complimentary MIM capacitors fabricated simultaneously in advanced RFCMOS and BiCMOS technologies. IEEE Bipolar/BiCMOS Circuits Tech Meet, 2008: 212
[2]
Ding S J, Zhu C X, Li M F. Atomic-layer-deposited Al2O3-HfO2-Al2O3 dielectrics for metal-insulator-metal capacitor applications. Appl Phys Lett, 2005, 87: 053501 doi: 10.1063/1.2005397
[3]
Ding S J, Xu J, Zhang D W, et al. Electrical characteristics and conduction mechanisms of metal-insulator-metal capacitors with nanolaminated Al2O3-HfO2 dielectrics. Appl Phys Lett, 2008, 93: 092909 doi: 10.1063/1.2969399
[4]
Zhu B, Liu W J, Wei L, et al. Voltage-dependent capacitance behavior and underlying mechanisms in metal-insulator-metal capacitors with Al2O3-ZrO2-SiO2 nano-laminates. J Phys D, 2016, 49: 135106 doi: 10.1088/0022-3727/49/13/135106
[5]
Sillars R W. The properties of a dielectric containing semiconducting particles of various shapes. J Inst Elect Eng, 1937: 378
[6]
Ge S B, Shen M R, Ning Z Y. Dielectric enhancement and Maxwell Wagner effect in polycrystalline BaTiO3Ba0.2Sr0.8TiO3 multilayered thin films. Chin Phys Lett, 1996, 19(4): 563
[7]
Qu B D, Evstigneev M, Johnson D J, et al. Dielectric properties of BaTiO3/SrTiO3 multilayered thin films prepared by pulsed laser deposition. Appl Phy Lett, 1998, 1394
[8]
O'Neill D, Bowman R M, Gregg J M, et al. Dielectric enhancement and Maxwell-Wagner effects in ferroelectric superlattice structures. Appl Phy Lett, 2000, 77: 1520 doi: 10.1063/1.1290691
[9]
Catalan G, O'Neill D, et al. Relaxor features in ferroelectric superlattices: A Maxwell-Wagner approach. Appl Phys Lett, 2000, 77: 3078 doi: 10.1063/1.1324729
[10]
Shen M, Ge S, Cao W, et al. Dielectric enhancement and Maxwell-Wagner effects in polycrystalline ferroelectric multilayered thin films. J Phy D, 2001, 34 (19): 2935 doi: 10.1088/0022-3727/34/19/301
[11]
Li W, Auciello O, Premnath R N, et al. Giant dielectric constant dominated by Maxwell-Wagner relaxation in Al2O3/TiO2 nanolaminates synthesized by atomic layer deposition. Appl Phys Lett, 2010, 96: 162907 doi: 10.1063/1.3413961
[12]
Jinesh K B, Lamy Y, Klootwijk J H, et al. Maxwell-Wagner instability in bilayer dielectric stacks. Appl Phy Lett, 2009, 95: 122903 doi: 10.1063/1.3236532
[13]
Karthik R, Kannadassan D, Baghini M S, et al. Nanostructured Bilayer Anodic TiO2/Al2O3 Metal-Insulator-Metal capacitor. J Nanosci Nanotech, 2013, 13: 1 doi: 10.1166/jnn.2013.6733
[14]
Sze S M, Ng Kwok K. Physics of semiconductor devices. John Wiley & Sons, 2006
[15]
Maxwell J C. A treatise on electricity and magnetism. Oxford: Clarendon Press, 1873
[16]
Morshuis P H F, Bodega R, Fabiani D, et al. Dielectric interfaces in dc constructions: Space charge and polarization phenomena. IEEE International Conference on Solid Dielectrics, ICSD, 2007, 450
[17]
Houssa M, Tuominen M, Naili M, e t al. Trap-assisted tunneling in high permittivity gate dielectric stacks. J Appl Phys, 2000, 87(12): 8615 doi: 10.1063/1.373587
Fig. 1.  SEM cross section image of anodized region before top elec-trode deposition. (a) Sample 1 (AV = 25 V). (b) Sample 2 (AV = 30 V).

Fig. 2.  (Color online) SIMS depth profile of all samples. (a) Sample 1. (b) Sample 2.

Fig. 3.  (Color online) X-ray diffraction spectra of anodized samples at various anodization voltages. (a) 25 V. (b) 30 V. (A: Anatase, R: Rutile)

Fig. 4.  Schematic of bilayer configuration. (a) Layer specification. (b) Equivalent circuit at low frequencies.

Fig. 5.  MW C–V model (without tunneling probability) and measured C–V fitting compatibility for samples. (a) Sample 1. (b) Sample 2.

Fig. 6.  MW C–V model (with tunneling probability) and measured C–V fitting compatibility for samples. (a) Sample 1 (10 kHz). (b) Sample 2 (1 kHz).

Table 1.   Fitting parameters of Maxwell–Wagner capacitance model.

Sample d1 (nm) d2 (nm) εr1 εr2 σ1 (pS/cm) σ2 (fS/cm) Φ1 (eV) Φ2 (eV) Vbi (eV)
Sample 1 15 7 90 9 15 2 3.3 2.3 1
Sample 2 15 10 90 9 15 4 3.3 2.3 1.2
DownLoad: CSV
[1]
He Z X, Daley D, Bolam R, et al. High and low density complimentary MIM capacitors fabricated simultaneously in advanced RFCMOS and BiCMOS technologies. IEEE Bipolar/BiCMOS Circuits Tech Meet, 2008: 212
[2]
Ding S J, Zhu C X, Li M F. Atomic-layer-deposited Al2O3-HfO2-Al2O3 dielectrics for metal-insulator-metal capacitor applications. Appl Phys Lett, 2005, 87: 053501 doi: 10.1063/1.2005397
[3]
Ding S J, Xu J, Zhang D W, et al. Electrical characteristics and conduction mechanisms of metal-insulator-metal capacitors with nanolaminated Al2O3-HfO2 dielectrics. Appl Phys Lett, 2008, 93: 092909 doi: 10.1063/1.2969399
[4]
Zhu B, Liu W J, Wei L, et al. Voltage-dependent capacitance behavior and underlying mechanisms in metal-insulator-metal capacitors with Al2O3-ZrO2-SiO2 nano-laminates. J Phys D, 2016, 49: 135106 doi: 10.1088/0022-3727/49/13/135106
[5]
Sillars R W. The properties of a dielectric containing semiconducting particles of various shapes. J Inst Elect Eng, 1937: 378
[6]
Ge S B, Shen M R, Ning Z Y. Dielectric enhancement and Maxwell Wagner effect in polycrystalline BaTiO3Ba0.2Sr0.8TiO3 multilayered thin films. Chin Phys Lett, 1996, 19(4): 563
[7]
Qu B D, Evstigneev M, Johnson D J, et al. Dielectric properties of BaTiO3/SrTiO3 multilayered thin films prepared by pulsed laser deposition. Appl Phy Lett, 1998, 1394
[8]
O'Neill D, Bowman R M, Gregg J M, et al. Dielectric enhancement and Maxwell-Wagner effects in ferroelectric superlattice structures. Appl Phy Lett, 2000, 77: 1520 doi: 10.1063/1.1290691
[9]
Catalan G, O'Neill D, et al. Relaxor features in ferroelectric superlattices: A Maxwell-Wagner approach. Appl Phys Lett, 2000, 77: 3078 doi: 10.1063/1.1324729
[10]
Shen M, Ge S, Cao W, et al. Dielectric enhancement and Maxwell-Wagner effects in polycrystalline ferroelectric multilayered thin films. J Phy D, 2001, 34 (19): 2935 doi: 10.1088/0022-3727/34/19/301
[11]
Li W, Auciello O, Premnath R N, et al. Giant dielectric constant dominated by Maxwell-Wagner relaxation in Al2O3/TiO2 nanolaminates synthesized by atomic layer deposition. Appl Phys Lett, 2010, 96: 162907 doi: 10.1063/1.3413961
[12]
Jinesh K B, Lamy Y, Klootwijk J H, et al. Maxwell-Wagner instability in bilayer dielectric stacks. Appl Phy Lett, 2009, 95: 122903 doi: 10.1063/1.3236532
[13]
Karthik R, Kannadassan D, Baghini M S, et al. Nanostructured Bilayer Anodic TiO2/Al2O3 Metal-Insulator-Metal capacitor. J Nanosci Nanotech, 2013, 13: 1 doi: 10.1166/jnn.2013.6733
[14]
Sze S M, Ng Kwok K. Physics of semiconductor devices. John Wiley & Sons, 2006
[15]
Maxwell J C. A treatise on electricity and magnetism. Oxford: Clarendon Press, 1873
[16]
Morshuis P H F, Bodega R, Fabiani D, et al. Dielectric interfaces in dc constructions: Space charge and polarization phenomena. IEEE International Conference on Solid Dielectrics, ICSD, 2007, 450
[17]
Houssa M, Tuominen M, Naili M, e t al. Trap-assisted tunneling in high permittivity gate dielectric stacks. J Appl Phys, 2000, 87(12): 8615 doi: 10.1063/1.373587
1

Analytical model for the effects of the variation of ferrolectric material parameters on the minimum subthreshold swing in negative capacitance capacitor

Raheela Rasool, Najeeb-ud-Din, G. M. Rather

Journal of Semiconductors, 2019, 40(12): 122401. doi: 10.1088/1674-4926/40/12/122401

2

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

Neeraj Jain, Balwinder Raj

Journal of Semiconductors, 2017, 38(12): 122002. doi: 10.1088/1674-4926/38/12/122002

3

Performance analysis of silicon nanowire transistors considering effective oxide thickness of high-k gate dielectric

S. Theodore Chandra, N. B. Balamurugan

Journal of Semiconductors, 2014, 35(4): 044001. doi: 10.1088/1674-4926/35/4/044001

4

AC-electronic and dielectric properties of semiconducting phthalocyanine compounds:a comparative study

Safa'a M. Hraibat, Rushdi M-L. Kitaneh, Mohammad M. Abu-Samreh, Abdelkarim M. Saleh

Journal of Semiconductors, 2013, 34(11): 112001. doi: 10.1088/1674-4926/34/11/112001

5

Structural, morphological, dielectrical and magnetic properties of Mn substituted cobalt ferrite

S. P. Yadav, S. S. Shinde, A. A. Kadam, K. Y. Rajpure

Journal of Semiconductors, 2013, 34(9): 093002. doi: 10.1088/1674-4926/34/9/093002

6

MOS Capacitance–Voltage Characteristics: IV. Trapping Capacitance from 3-Charge-State Impurities

Jie Binbin, Sah Chihtang

Journal of Semiconductors, 2012, 33(1): 011001. doi: 10.1088/1674-4926/33/1/011001

7

MOS Capacitance-Voltage Characteristics: V. Methods to Enhance the Trapping Capacitance

Jie Binbin, Sah Chihtang

Journal of Semiconductors, 2012, 33(2): 021001. doi: 10.1088/1674-4926/33/2/021001

8

Capacitance-voltage analysis of a high-k dielectric on silicon

Davinder Rathee, Sandeep K. Arya, Mukesh Kumar

Journal of Semiconductors, 2012, 33(2): 022001. doi: 10.1088/1674-4926/33/2/022001

9

Accurate surface potential determination in Schottky diodes by the use of a correlated current and capacitance voltage measurements. Application to n-InP

Ali Ahaitouf, Abdelaziz Ahaitouf, Jean Paul Salvestrini, Hussein Srour

Journal of Semiconductors, 2011, 32(10): 104002. doi: 10.1088/1674-4926/32/10/104002

10

MOS Capacitance–Voltage Characteristics from Electron-Trapping at Dopant Donor Impurity

Jie Binbin, Sah Chihtang

Journal of Semiconductors, 2011, 32(4): 041001. doi: 10.1088/1674-4926/32/4/041001

11

Pb(Zr0.52Ti0.48)O3 memory capacitor on Si with a polycrystalline silicon/SiO2 stacked buffer layer

Cai Daolin, Li Ping, Zhai Yahong, Song Zhitang, Chen Houpeng, et al.

Journal of Semiconductors, 2011, 32(9): 094007. doi: 10.1088/1674-4926/32/9/094007

12

MOS Capacitance-Voltage Characteristics II. Sensitivity of Electronic Trapping at Dopant Impurity from Parameter Variations

Jie Binbin, Sah Chihtang

Journal of Semiconductors, 2011, 32(12): 121001. doi: 10.1088/1674-4926/32/12/121001

13

MOS Capacitance-Voltage Characteristics III. Trapping Capacitance from 2-Charge-State Impurities

Jie Binbin, Sah Chihtang

Journal of Semiconductors, 2011, 32(12): 121002. doi: 10.1088/1674-4926/32/12/121002

14

Multi-bias capacitance voltage characteristic of AlGaN/GaN HEMT

Pu Yan, Wang Liang, Yuan Tingting, Ouyang Sihua, Liu Guoguo, et al.

Journal of Semiconductors, 2010, 31(10): 104002. doi: 10.1088/1674-4926/31/10/104002

15

TDDB improvement by optimized processes on metal–insulator–silicon capacitors with atomic layer deposition of Al2O3 and multi layers of TiN film structure

Peng Kun, Wang Biao, Xiao Deyuan, Qiu Shengfen, Lin D C, et al.

Journal of Semiconductors, 2009, 30(8): 082005. doi: 10.1088/1674-4926/30/8/082005

16

Capacitance–voltage characterization of fully silicided gated MOS capacitor

Wang Baomin, Ru Guoping, Jiang Yulong, Qu Xinping, Li Bingzong, et al.

Journal of Semiconductors, 2009, 30(3): 034002. doi: 10.1088/1674-4926/30/3/034002

17

A Simulation of the Capacitance-Voltage Characteristics of a Ge/Si Quantum-Well Structure

Cheng Peihong, Huang Shihua

Journal of Semiconductors, 2008, 29(1): 110-115.

18

Synthesis and Characterization of SiCOF/a-C∶F Double-Layer Films with Low Dielectric Constant for Copper Interconnects

Zhang Wei, Zhu Lian, Sun Qingqing, Lu Hongliang, Ding Shijin, et al.

Chinese Journal of Semiconductors , 2006, 27(3): 429-433.

19

The Usage of Two Dielectric Function Models

Chen Hong, Shen Wenzhong

Chinese Journal of Semiconductors , 2006, 27(4): 583-590.

20

2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs

Ji Feng, Xu Jingping, Lai P T, Chen Weibing, Li Yanping, et al.

Chinese Journal of Semiconductors , 2006, 27(10): 1725-1731.

1. Caligiuri, V., Pianelli, A., Miscuglio, M. et al. Near- And Mid-Infrared Graphene-Based Photonic Architectures for Ultrafast and Low-Power Electro-Optical Switching and Ultra-High Resolution Imaging. ACS Applied Nano Materials, 2020, 3(12): 12218-12230. doi:10.1021/acsanm.0c02690
  • Search

    Advanced Search >>

    GET CITATION

    R Karthik, A Akshaykranth. Fabrication and modeling of multi-layer metal–insulator-metal capacitors[J]. Journal of Semiconductors, 2017, 38(12): 123002. doi: 10.1088/1674-4926/38/12/123002
    R Karthik, A Akshaykranth. Fabrication and modeling of multi-layer metal–insulator-metal capacitors[J]. J. Semicond., 2017, 38(12): 123002. doi: 10.1088/1674-4926/38/12/123002.
    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 3906 Times PDF downloads: 48 Times Cited by: 1 Times

    History

    Received: 24 March 2017 Revised: 05 May 2017 Online: Published: 01 December 2017

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      R Karthik, A Akshaykranth. Fabrication and modeling of multi-layer metal–insulator-metal capacitors[J]. Journal of Semiconductors, 2017, 38(12): 123002. doi: 10.1088/1674-4926/38/12/123002 ****R Karthik, A Akshaykranth. Fabrication and modeling of multi-layer metal–insulator-metal capacitors[J]. J. Semicond., 2017, 38(12): 123002. doi: 10.1088/1674-4926/38/12/123002.
      Citation:
      R Karthik, A Akshaykranth. Fabrication and modeling of multi-layer metal–insulator-metal capacitors[J]. Journal of Semiconductors, 2017, 38(12): 123002. doi: 10.1088/1674-4926/38/12/123002 ****
      R Karthik, A Akshaykranth. Fabrication and modeling of multi-layer metal–insulator-metal capacitors[J]. J. Semicond., 2017, 38(12): 123002. doi: 10.1088/1674-4926/38/12/123002.

      Fabrication and modeling of multi-layer metal–insulator-metal capacitors

      DOI: 10.1088/1674-4926/38/12/123002
      Funds:

      Project supported by the Science and Engineering Research Board (No. ECR/2016/001156).

      More Information
      • Corresponding author: Email: rayam16@gmail.com
      • Received Date: 2017-03-24
      • Revised Date: 2017-05-05
      • Published Date: 2017-11-01

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return