1. Introduction

Wireless communication systems and corresponding services are developing quickly over the whole world. The advanced 3G technology 3GPP-LTE has been applied in our lifetime. At present, the satellite navigation system BEIDOU developed by China can work successfully with other systems like GPS, GLONASS and GALILEO. It is already beginning to provide navigation services to China and near countries recently. Except short distance communication, the wireless sensor network based on IEEE 802.15.4 and the IOT (internet of things) have great value in industry, military and other fields^[1]. WLAN (wireless local area network) also has great prospects in high-speed wireless communication.

With the rapid development of wireless communication modes and communication terminals, integrating various communication modes in a mobile terminal has become the trend of the wireless communication technology^{[2, 3]}. Because of this, the multi-standard wireless transceiver is one of the hot spots in current research. As the key part, a frequency synthesizer determines the performance and integration level of the wireless transceiver. The frequency synthesizer can output multiple frequency signals with high precision by changing the frequency division of fractional-N frequency divider. So the fractional-N frequency divider is very important to the system.

A fractional-N frequency divider is composed of a programmable frequency divider and a Δ–Σ modulator. As a very important factor, phase noise influences the performance of the whole transceiver. The technology to restrain phase noise is being used in lots of structures. Compared with conventional structure, reducing the division ratio interval is a good way to decrease the phase noise. This thesis uses phase switching technology and a chain of divider-by-2/3 to realize a programmable frequency divider with 0.5 step which reduces the phase noise of the whole loop. A high-speed divider-by-2 with traditional source-coupled-logic is designed for very wide band usage. Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step. The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider. Δ–Σ modulator is achieved by an improved MASH 1-1-1 structure.

The whole fractional-N frequency divider is implemented in TSMC 0.18 μm RF CMOS process, occupying a chip area of 1130 × 510 μm². With 1.8 V supply voltage and 29 mA current consumption, the measurement results show that it can correctly divide within the frequency range of 0.8–9 GHz and its division ratio ranges from 62.5 to 254.

2. Phase switching technique

In the Δ-Σ fractional-N frequency synthesizer, the output phase noise generated by quantization noise of Δ-Σ modulator can be described as follows^[4]:

${{S}_{\Delta -{\scriptscriptstyle\sum} }}(f)={{f}_{\text{ref}}}|{{H}_{\Delta -{\scriptscriptstyle\sum} }}(f){{|}^{2}}\cdot |{{H}_{\text{div}}}(f){{|}^{2}}\frac{{{\Delta }^{2}}}{12},$

In this formula, f_ref is the reference frequency, ${H_{\Delta - {\scriptscriptstyle\sum} }}(f)$ is the quantization noise transfer function of Δ-Σ modulator, ${H_{\rm div}}(f)$ is the phase noise transfer function of divider and ∆ is division ratio interval, ${S_{\Delta - {\scriptscriptstyle\sum} }}(f)$ is the power spectral density of phase noise generated by quantization noise.

Quantization noise is the main spur in Δ–Σ fractional-N frequency synthesizer. It affects the whole performance of the frequency synthesizer. From formula (2.1), lower f_ref and lower loop-bandwidth can decrease the influence of quantization noise, but 1/f flicker noise and phase noise of VCO will increase at the same time. Reducing the division ratio interval $\varDelta$ is a good way to decrease the quantization noise without affecting other modules. The output phase noise will have 6 dB improvement when $\varDelta$ interval reduces 0.5. This design uses a programmable frequency divider with 0.5 step.

The most important thing to design a programmable frequency divider with 0.5 step is to design an N/N+0.5 dual-module pre-scaler. Two structures will be considered to complete an N/N+0.5 dual-module pre-scaler. The first is bilateral trigger structure and the other is phase switching structure^[4].

Bilateral flip-flop can work well at low frequency, but it does not adapt to high frequency due to its sensitivity to circuit delay. Phase switching structure has low power consumption and excellent reliability. What is more, it can work well at a high frequency. This paper uses phase switching architecture to design a programmable frequency divider with 0.5 step.

The phase switching waveform is shown in Fig. 1. The first line is clock signal and the next four signals are orthogonal signals whose frequency is half of the clock signal. They are generated by high-speed divider-by-two and are indicated as 00 (0°), 01 (90°), 11 (180°), 10 (270°). Just one of them will be selected at any time. In Fig. 1, the waveform of output signal is switched from 10 to 11 at time t and the output signal swallows 1/4 period. In other words, it swallows 1/2 period of the clock signal. Controlling the times of switching can achieve 1 and 1.5 step.

Phase switching is a good method but there is an obvious shortcoming. Glitch is a serious weakness in phase switching technology. In Fig. 2, no glitch appears when switching happens at time t₂, but when switching happens at time t₁, the glitch cannot be ignored. It generates an extra rising edge.

Lots of methods can be used to eliminate the influence of glitch and forward-switching is the most efficient and simplest method^[5]. Output signal is switched from 10 forward to 11 in Fig. 3. Different from Fig. 2, no glitch appears when switching happens at time t₁ or t₂. The most important thing of forward-switching is that the target signal must be high level ‘1’ when the rising edge of current signal comes. Because level ‘1’ changed to level ‘1’ or level ‘0’ changed to level ‘0’ will not generate extra edges. Similarly, level ‘0’ changed to level ‘1’ just forwards of the rising edge. But level ‘1’ changed to level ‘0’ is not a safe change. An extra edge will be generated when the rising edge of the target signal is a little behind the switching time. Forward-switching technique can faultlessly solve this problem.

3. Structure

The multi-standard fractional-N frequency divider designed by this thesis is applied for wireless communications, satellite navigation, wireless sensor network and other applications. It will face lots of challenges compared to the common ones. The biggest difficulty of this thesis is to realize almost all communication standards and the frequency synthesizer need to make output frequency range 0.7–3.8 GHz. If the frequency synthesizer is designed in double structure (it generates two times the frequency of the local signal), the voltage control oscillator (VCO) must let output frequency range be 1.4–7.6 GHz. It is very difficult to design such a VCO because this frequency synthesizer is fabricated in TSMC 0.18μm RF CMOS process. This thesis uses two VCOs to achieve 1.4–7.6 GHz output frequency range. The higher VCO covers 4–7.6 GHz and the lower one covers 1.4–4 GHz.Fig. 4 presents the structure diagram of the fractional-N frequency synthesizer.

The whole structure of the fractional-N frequency divider is displayed in Fig. 5. It consists of a high-speed divider-by-2, a programmable frequency divider with 0.5 step and a Δ–Σ modulator. The output signal of VCO goes through the first high-speed divider-by-2 and becomes four quadrature signals. These four quadrature signals are the output of frequency synthesizer and then they will be provided into the later mixer. Furthermore, the programmable frequency divider with 0.5 step is composed of a high-speed divider-by-2 which follows the first one, a phase switching circuit, an integer-N programmable frequency divider and a logic control module. Δ–Σ modulator is achieved by an improved MASH 1-1-1 structure. It changes the control words P0-P8 to make the real-time division ratio random.

4. Circuit design

4.1 High speed divider-by-two

A divider-by-2 can be simply completed by a D flip-flop that is made up of a master and a slave digital latch. SCL (source coupled logic) latch has very high working frequency, bandwidth and satisfactory quadrature performance. Therefore it is suitable for high-speed divider-by-2. The schematic of divider-by-2 with SCL logic is shown in Fig. 6. The trail-transistor provides constant current to hold the output swing and positive feedback is formed by connecting its output ports back to its input ports.

A clock divider can be best characterized by its sensitivity curve, which gives the requested minimum amplitude V_min of the input signal^[6]. A typical sensitivity curve is presented in Fig. 7.

In region I, the divider is locked to the half-rate frequency. This function is the intended operation of the circuit. Self-oscillation frequency (f_so) is also an important parameter. Requirement for the amplitude of input signal will be the least when its frequency equals to double self-oscillation frequency. The amplitude requirement will be higher when the input frequency is farther from 2f_so because the slope after 2f_so is higher than the prior one. Thus, making 2f_so be slightly lower than f_{in, max} is a common robust design method. In fact, the IC process and temperature will bring significant influence on f_so. These effects should be considered by circuit designers.

In this design, the structure of tail current transistor with resistance load is used for constant current and invariant output swing. Compared with the MOS load, the area of resistance load is larger and temperature always influences it. But the parasitic capacitance of resistance load is small, which is quite necessary to improve the working frequency of the divider-by-2. Layout technique and adding dummy are two considerable methods to decrease the impact of temperature.

With the resistance load, the maximum and minimum output voltage is VDD and VDD-I_ssR, I_ss in this equation indicates the bias current of trail-transistor. Generally speaking, the average output voltage equals to (1/2)I_ssR. Basic circuit theory indicates that the conversion rate of a circuit must be larger than V₀W₀ if it amplifies a signal V₀ sin(w₀t + θ) so that following equation can be easily acquired^[7]:

$\frac{I_{\rm ss}}{C_{\rm L}} \ge {V_0}{\omega _0} = \frac{1}{2}{I_{\rm ss}}R \times 2\pi {f_0},$

(2)

$R \le \frac{1}{{\pi {f_0}{C_{\rm L}}}},$

(3)

C_L in Eq. (2) is the load capacitance at the output port and f₀ represents the frequency of output signal. The load resistance R is generally set as the maximum value for the lowest power consumption. I_ss can be easily obtained according to the request of output swing. The constraint formula of positive feedback is shown as follows:

${g_{\rm m5/m6}} R \ge 1.$

(4)

Similarly, the g_m5 and g_m6 are usually set as the minimum value for the lowest power consumption so that the current of latch branch is:

${I_2} = \frac{1}{2}{g_{\rm m5}}{V_{\rm on}} + \frac{1}{2}{g_{\rm m6}}{V_{\rm on}} = {g_{\rm m5/m6}}{V_{\rm on}}.$

(5)

The current of sample branch is:

${I_1} = {I_{\rm ss}} - {I_2}.$

(6)

From the above analysis, the parameters of each transistor can be calculated in theory^[8].

4.2 Programmable frequency divider

The circuit for phase switching is shown in Fig. 8. The input of divider-by-2 is equal to the output of PLL and its frequency ranges from 0.5 to 4 GHz. The input signal goes through divider-by-2 and turns into four quadrature signals. The phase switching circuit is made up of two common source amplifiers and a 4-1 transfer-gate multiplexer. The selected signal goes through a common source buffer to the later circuits. The common source amplifier is suited for dealing with differential signals and it can compensate the attenuation of transfer-gate.

The difficulty of this design is setting the parameters of transistors. The output of divider-by-2 will be selected after a common source amplifier. Theoretically speaking, the highest frequency in phase switching circuit is 2 GHz. In fact, the waveform after switching is not a 2 GHz sine wave, but a complex wave within 2 GHz sine wave and harmonic wave. The common source buffer needs to reshape this irregular wave to the later circuit. The bandwidth of system will have a large drop due to the influence of parasitic effect in post-simulation. Therefore, the common source amplifier should be good at dealing with a wide band harmonic wave. Because of the contradiction of gain and bandwidth, it is important to take both of them into account.

The integer-N programmable frequency divider is based on a chain of divider-by-2/3. The divider-by-2/3 cell as shown in Fig. 10 will be divided by 3 when the control signals P and mod_in are both high. In the other case, it will be divided by 2.

The integer-N programmable frequency divider operates as follows: the enable control signal mod_in(n) on the last cell will be set as effective all the time and mod_in(n-1) is the output signal of the last cell. For the divider-by-2/3, division by 3 will increase an extra period to the corresponding cell^[9]. So the division ratio of the programmable frequency divider can be described by the following:

$M = {P_0} + 2{P_1} + {2^2}{P_2} + ... + {2^{n - 1}}{P_{n - 1}} + {2^n}.$

(7)

Eq. (6) makes the division ratio of integer-N programmable divider range from 2ⁿ (ALL P_n = 0) to 2ⁿ⁺¹−1 (ALL P_n = 1). It is not wide enough for the multi-standard application so that extending the division ratio range is necessary. Adding some logic gates in the chain is an appropriate way to make this improvement come true. The block diagram is displayed in Fig. 9.

The logic OR gate is invisible to the whole system when the control port P₆ = 1 and the division ratio ranges from 2⁶ to 2⁷−1. When P₆ = 0, the last divider will be disabled and the division ratio range is changed to 2⁵−2⁶−1. In a word, the whole division ratio range has been extended to 2⁵−2⁷−1 by controlling P₆.

The first divider still uses SCL structure to deal with high frequency and the circuit diagram is described in depth in Fig. 10. It consists of a pre-scaler logic, an end-of-cycle logic and several AND gates^[10]. Generally speaking, AND gate is always achieved by CMOS combination. CMOS combination cannot deal with high frequency smoothly due to its high gate delay. More transistors of traditional CMOS combination result in the increase of layout area^[11]. Integrating AND gates into the SCL structure is an ideal way to solve the problems above. Fig. 11 gives the specific circuit diagram.

The frequency will get down to 1GHz after the first divider-by-2/3 and traditional digital flip-flops can work at this frequency. Therefore, TSPC structure is used except the first divider-by-2/3. As in Fig. 11, logic gates can be integrated into TSPC structure to reduce area consumption. The boundary between analog and digital signals is after the first divider-by-2/3. There is a trans-conductance amplifier (OTA) which is used to change the weak differential signals to a single-ended rail-to-rail signal^[7].

The logic control module is used to select phase switching times. As shown in Fig. 12, the input signal of logic control module is from integer-N programmable divider. The trans-conductance amplifier in integer-N programmable divider provides the clock signal. A new period begins when the drop edge comes. Then the pulse generator produces a short pulse as a clean signal to make the counter be ‘0’ state. The counter and gray state machine will work once when a rise edge of CLK signal comes. The counter will work continually until its output equals to P₀P₁. EN signal makes the logic control module static until a new period comes.

4.3 Digital Δ-Σ modulator

The digital Δ–Σ modulator (DDSM) is the key part of this circuit. Three important factors of DDSM are listed as follows^[12]. The first one is the accuracy of the output sequence. It is requested that the average of the output sequence must equal to the input signal accurately. The second one is the length of the output sequence. It must be long enough to decrease the influence of fractional-N spur in PLL. The last one is dynamic input range. From the target requirement, the input signal of DDSM must be set as any integer between 0 to 2^N−1, N is the bit length of input.

The structure of improved MASH 1-1-1 DDSM is presented in Fig. 13. Compared to conventional DDSM, its EFM (error feedback modulator) has two inputs. Except previous quantization error signal e_i[n], the output signal of previous circuit will be sent to later blocks simultaneously^[13]. When the input signal is constant, the length of the output of improved DDSM equals to N₁M₂ regardless of the initial value. In this equation, N₁ is the output signal’s length of the first EFM and M is the bit length of EFM^[14].

5. Measurement results

The fractional-N frequency divider with phase switching technique for multi-standard wireless transceiver is fabricated in TSMC 0.18 μm RF CMOS process. It occupies a chip area of 1130 × 510 μm² and Fig. 14 provides the chip photo of this frequency divider.

Independent simulation and combined simulation are both necessary due to the wideband working frequency. It is also important to make adjustment with circuit and layout according to the post-simulation results. Self-oscillation frequency and input sensitivity are important parameters of the high speed divider-by-two. Both of them represent the least power needed by the system under the working frequency range. The measurement results of self-oscillation frequency and input sensitivity are shown in Figs. 15 and 16. Through Fig. 15, the self-oscillation frequency of high-speed divider-by-two is 3.647 GHz. Fig. 16 indicates that the input power needed is least near 7.5 GHz, which equals to double self-oscillation frequency of high-speed divider-by-two. Furthermore, the circuit can work correctly at 1–8 GHz only when the power of input signal is bigger than −12 dBm.

Make the Δ–Σ modulator free and set the input signal to the highest working frequency as 8 GHz sine signal. Then make the control words 1101_0000_1 and its theoretical division ratio is 130.5. The spectrum of the measurement result is indicated in Fig. 17. It is easy to get the correct division ratio from Fig. 17 and the measurement result shows that the whole system works correctly. In a similar testing way, Fig. 18 is the spectrum generated by division ratio 67.

Because of the changing division ratio, the spectrum of output signal is changing ceaselessly. The average function of spectrum analyzer can be used to test the spectrum when the Δ-Σ modulator is working. Set the input signal as 8 GHz sine signal and make the division ratio of programmable frequency divider with 0.5 step to 67.5. The input of Δ-Σ modulator is set as 20b’1000_0000_0000_0000_0000 for easy testing. The theoretical division ratio of the whole circuit is 67.75. From the average spectrum of the fractional-N frequency divider in Fig. 19, the entire system with Δ-Σ modulator works correctly.

Table 1 presents the comparison between simulation results, measurement results and design index. The measured performance of this fractional-N frequency divider and other recently published wideband frequency dividers are summarized in Table 2. Compared with other designs, this work has a very wide band to realize multi-standard for almost all communication modes. Obviously, its wide band is at the expense of relatively high power consumption.

The phase noise of the frequency synthesizer is an important point of this design and the whole system has been finished recently. Fig. 20 shows that the phase noise is about −107 dBc/Hz at output frequency 5.68 GHz (@ 1 MHz). The measurement results meet the design target. Regrettably, digital power brings some bad influences to analog circuits, but post-simulation cannot indicate these changes accurately. Better isolation technique should be used for next design.

6. Conclusions

This paper presents a fractional-N frequency divider for multi-standard wireless transceiver. Phase switching technique is used to decrease the interval of Δ-Σ modulator for low phase noise. The whole fractional-N frequency divider is fabricated in TSMC 0.18 μm RF CMOS process, occupying a chip area of 1130 × 510 μm². This chip can correctly divide within the frequency range of 0.8–9 GHz with 1.8 V supply voltage. The total current consumption is 29 mA and its division ratio ranges from 62.5 to 254. The wideband working frequency makes it comfortable for GPS, GSM, Galileo and other communication modes.