1. Introduction

Advanced technology nowadays insist on high performance as well as reliability. With continuous device scaling, performance increases, but at the cost of leakage power and reliability etc. High-performance processors use SRAM as one of the essential building blocks because of its compatibility with the logic. The main uses of SRAM include storing and modifying the data. But, for conservation of data, SRAM in its standby mode is used. The leakage power is very large in the standby mode due to the reduced supply and threshold voltage in deep sub-micron technologies. As most of the area in the modern technology processors are reserved for SRAM, so leakage of SRAM in standby mode becomes an important concern. The leakage power of a single transistor is not an issue to be concerned about. But jointly for billions of transistors, which are used in SRAM array, it becomes a crucial source for the total power dissipation. Thus, in ultra low power designs, it is essential to deal with this leakage of SRAM. Substrate biasing, sleep mode, and stacking are some of the low power techniques to reduce this leakage power. But, supply voltage reduction is one very proficient way to reduce the power dissipation. The minimum standby supply may be defined as DRV, which is the minimum voltage in SRAM, for which data can be stored safely and reliably.

For the last few years, researchers worked a lot for this DRV of SRAM. For the estimation of the DRV, an analytical model was proposed by Qin et al.^[1]. Further, for the nano-scale technologies, sensitivity to variation increases. A number of methods are given by the researchers to study and reduce these variations in the SRAM cell. Mohammad et al.^[2] proposed the dynamic stability criteria which furnish different bounds for the SNM. Vasudha et al.^[3] proposed a statistical method, which accounts for manufacturing variability in transistor dimension. Ref. [4] presents the SNM sensitivity analyses of the 6T SRAM cell for variations of the doping concentration at different locations inside the cell. A variability aware SRAM cell is proposed by Islam et al.^[5], in which access transistors are replaced by the transmission gates.

In this paper, 6T SRAM cell is simulated using 45 nm technology GPDK file and the DRV for the cell is found. Then from the analytical model of Qin^[1], for the same cell, the DRV is calculated. It has been observed that the simulated DRV and the obtained DRV from the analytical model are very close to each other. The sensitivity analysis is carried out with variations in aspect ratio and temperature for the DRV of 6T SRAM cell.

In the case of dense arrays the measurement of read and write stability is very difficult to find in terms of RSNM and WSNM because of the metal spacing constraint for routing out internal storage nodes and the significant area overhead associated with the switch array^{[9, 12]}. Also, we know that the stability of the SRAM array depends upon the bitlines, word-line and the supply voltage^[8]. To take advantage of this fact, the read stability can be discovered in terms of bit-line measurement while adjusting the bit line, word-line and supply voltage^[14]. Thus the read stability in functional SRAM arrays can be defined in terms of read retention voltage, i.e. lowest cell supply voltage for data retention during a read cycle, which is equivalent to finding the SRRV (supply read retention voltage). Also, the read stability of an SRAM cell can be estimated by the largest word-line voltage without upsetting cell data retention and this is defined as WRRV i.e. wordline read retention voltage. In other words, we can define SRRV as the difference between nominal supply voltage and a minimum supply voltage at which the data can be retained in the SRAM cell during read cycle and WRRV, as the difference between the boosted value of wordline voltage, for which the data can be retained during read and the nominal supply voltage. SRRV and WRRV are computed for 45 nm SRAM cell and then analyzed with different cell ratios (CR).

Section 2 explains the DRV calculation from the analytical model and its comparison with the simulated value for 6T SRAM cell. In Section 3, the results of sensitivity analysis of DRV variations are given with brief discussion. The calculations of SRRV and WRRV are discussed in Section 4. Finally, Section 5 concludes the paper.

2. DRV estimation

The DRV i.e. data retention voltage is defined as the minimum standby supply voltage required for the data retention. DRV for 6T SRAM can be predicted from the butterfly curve. The butterfly curve is drawn from the VTC (voltage transfer characteristic) curves and VTC (inverse) of its internal inverters^[1].

The first step for finding the DRV, is to draw the butterfly curve for HSNM (hold static noise margin) for different supply voltage and then find that minimum voltage, for which the area within the curve is non-zero. Further, reduction in supply voltage can cause the deterioration in the inverter VTC curves. This minimum voltage defines the data retention voltage^[1]. The basic circuit for 6T SRAM cell is as shown in Fig. 1. This 6T SRAM cell with its minimum size transistors ( $L=45$ nm and $W=120$ nm) are simulated in Cadence. The DRV here is found from the simulation and then it is compared with the result obtained from the analytical model of Ref. [1]. The butterfly curve, which has been drawn, is as shown in Fig. 2

All of the simulations are carried out using Cadence Virtuoso version IC6.1.5-64b. GPDK 45 nm technology file is used for the simulations. The Virtuoso Analog Design Environment L is used as schematic editor for the schematics of 6T SRAM and simulations are performed using Spectre Simulator. The DRV observed from the simulation is 62 mV. The DRV calculated from the subthreshold equations of the model^[1] is 46 mV which is very close to the simulated value of 62 mV.

Post layout simulation is performed using UMC 130 nm technology files in cadence. The schematic remains the same as shown in Fig. 1. The transistors used are of the same dimension with $L=120$ nm and $W =160$ nm. The layout is as shown in Fig. 3.

The DC analysis is used for the DRV estimation. Therefore the values of DRV obtained from pre layout simulation and post layout simulation is the same. The DRV obtained with 130 nm technology file is 68 mV prior and after layout simulations.

3. Sensitivity analysis

Due to continued scaling, the circuit becomes more sensitive to the process variation and the reliability of the circuit decreases in the presence of variability. Because of this reliability issue, it is essential to deal with these variations and find out how the circuit performs while working in the presence of these variations. The sensitivity analysis of DRV in this paper is divided into two parts. The first part deals with the temperature analysis of the DRV for 6T SRAM while another part takes care of the sizing variation analysis.

The simulation is carried out at two technology nodes using 45 nm GPDK files and 180 nm GPDK files. The 6T SRAM cell has been used for the simulation.

For the temperature analysis, the temperature has been varied from 0 to 150 $℃$ and the DRV for 6T SRAM cell is discovered at both the technology nodes i.e. at 45 nm as well as at 180 nm. The minimum size transistors are used for the temperature analysis. For 45 nm technology, all of the six transistors are used with $L=45$ nm and $W=120$ nm, whereas for 180 nm technology the transistors used are of $L=180$ nm and $W=2$ $\mu$ m. Fig. 4 shows the variation of DRV with temperature at both the technology nodes.

From Fig. 4 it is clear that the 6T SRAM cell tolerates the temperature increase up to 100 $℃$ but increases abruptly for 150 $℃$ . For 180 nm technology node this increase is very large compared to the 6T SRAM cell at 45 nm technology. Also, it can be clearly observed that the DRV remains almost constant for 180 nm technology node up to 100 $℃$ while it shows an increase for the 100 $℃$ at the 45 nm technology node. This is due to the strength of the transistors. The transistors are of larger size and stronger in 180 nm technology compared to a transistor in 45 nm technology node. Due to which DRV varies in 45 nm technology, but remains constant in 180 nm technology for 100 $℃$ temperature. Table 1 shows the DRV variation with temperature.

Further, with increase in temperature the mobility of the transistors decreases, due to which transistors become unable to hold the data for long and DRV shows an increase at 150 $℃$ for both the technology nodes.

The second part of the sensitivity analysis deals with the analysis of DRV with variation in sizing of the transistors. As the WL (wordline) is in non-active condition, the access transistors are considered to be in off condition. So, for the DRV analysis, the width of the pull down transistors is varied initially while the width of the pull up transistors remains constant and then the DRV is found with this sizing variation. Then the DRV is found out by varying the width of the pull up transistors while the width of the pull down transistors remains constant. The variation of DRV with $W_{\rm n}$ and $W_{\rm p}$ variation is given in Table 2.

The simulation for the sizing variations are performed for different values of NMOS and PMOS widths. The width of the transistor with minimum size is considered as 1 whereas 1.75, 2.5 and 3.375 represents the multiples to get the corresponding widths for the variations. The NMOS and PMOS transistors are varied according to these multiples. Table 3 gives the sizes of the transistors according to these variables.

According to Table 3, the sizes of the pull down transistors (pull up transistors) are varied while fixing the width of the pull up transistor (pull down transistor) at its minimum width. The DRV variation with the variation in the pull down transistors is shown in Fig. 5 while Fig. 6 gives the variation of DRV with PMOS sizing variation.

From Figs. 5 and 6, it is observed that the DRV remains almost constant with variation in sizing at the 45 nm technology node. But at 180 nm technology, the DRV increases with the increase in the width of the pull down transistor and decreases with an increase in the width of the pull up transistor. This is due to the difference in the current driving capability of PMOS and NMOS transistors. To hold the data, there should be a balance between the current carrying capabilities of the pull up and the pull down transistors. Also, we know that the current carrying capability of NMOS is more due to high electron mobility than the hole mobility, which increases the strength of the NMOS than the same sized PMOS. For NMOS with an increased width, it becomes stronger in terms of current carrying capabilities than the minimum size PMOS. Due to this imbalance, the DRV shows an increase with the increase in the width of the pull down transistors. But, for an increase in PMOS transistor width, the imbalance decreases due to the increase in the current carrying capability of PMOS which is now approaching the current carrying capability of the minimum size NMOS. So, the DRV shows a decrease with an increase in the width of the pull up transistors.

The circuit stability and the sensitivity are related terms when we are dealing with the scaled devices. As the sizes of the transistors scale down, their sensitivity to variation increases, enhancing the related stability and reliability issues. In this paper, we are discussing the hold and read stability issues for the 6T SRAM related to the sizing variations. The hold stability has already been discussed in the present section. The next section deals with the read stability in terms of supply read retention voltage and wordline read retention voltage.

4. SRRV and WRRV computation

The read stability and write stability can be estimated from SRAM cells by accessing its internal storage nodes conventionally i.e. by finding the RSNM and WSNM, but the disadvantage of this method is the large area overhead due to the associated switch network and limited data volume delivered^[9]. To overcome these difficulties, the read stability can be computed from the functional SRAM arrays by directly accessing the bitlines instead of the internal storage nodes. The large scale performance of the SRAM cells can be characterized through the direct correlation between the distribution of the per cell read current and per cell minimum supply voltage. But this correlation is very difficult to establish through the conventional methods (by RSNM and WSNM) and this direct correlation is possible through computation of SRRV (supply read retention voltage) and WRRV (wordline read retention voltage).

The characterization parameter, i.e. WRRV, can be further used to find the dynamic variability induced by the BTI stress^{[13, 15]} which is not possible with the conventional RSNM and WSNM methods. The read margin of the cell can be estimated by the supply read retention voltage. In addition, SRRV and WRRV can be used to find the read retention voltage during read i.e. to find the minimum supply voltage to retain the data during read. The methods for the estimation of SRRV and WRRV are given in the section below.

4.1 Supply read retention voltage (SRRV)

SRRV deals with the estimation of minimum supply voltage for which the data can be preserved during a read cycle. The difference between the nominal supply voltage and the minimum supply voltage for which data can be retained during read is SRRV. Fig. 7 shows the setup for estimation of SRRV of 6T SRAM cell.

The first step here is the initialization phase, during which the SRAM cell is initialized to a known state. In the present case, there is `0' at the BL node and ‘1' at the BLB node. During the next step, both the bit lines are precharged to $V_{\mathrm{DD}}$ and also $V_{\mathrm{DD}}$ is applied to the word line, so that SRAM cell is in read state. Now, the $I_{\mathrm{BL}}$ (the current of the corresponding node which is at `0' state) is monitored, while decreasing the cell supply voltage ( $V_{\mathrm{CELL}})$ in steps.

The supply voltage is connected to the voltage source here with the specified step sizes. The initialization step of the supply voltage is about 0 to 700 ns for which the voltage is 450 mV. After this initialization step, the time is increased in steps of 6.50 $\mu$ s and the voltage is decreasing in steps of 45 mV, so that at the end of 65 $\mu$ s the voltage applied is 0 V.

In between these steps, at a particular value of the reduced cell supply voltage $V_{\mathrm{CELL}}$ , the $I_{\mathrm{BL}}$ is reduced drastically. At this point, the cell state has flipped and the read upset has occurred. This particular voltage is known as $V_{\mathrm{FLIP}}$ . The difference $V_{\mathrm{DD}}-V_{\mathrm{FLIP}}$ is SRRV. This means that for SRRV $=$ 0, the SRAM cell is biased in the normal read operation, whereas SRRV $>$ 0 gives the minimum voltage that can be applied during read without disturbing its state. The decrease in $V_{\mathrm{DD}}$ means the decrease in the $V_{\mathrm{GS}}$ (gate-to-source voltage)^[12] of the pull-down transistor. Thus SRRV is a measure of the maximum tolerable reduction in the $\beta$ -ratio while maintaining the preserved data during read cycle. This can be achieved here through changing (reducing) the pull-down $V_{\mathrm{GS}}$ associated with unchanged operating conditions of the access transistor before the deterioration of cell state during read.

4.2 Wordline read retention voltage (WRRV)

The read stability can also be measured by the largest word-line voltage that can be applied without disturbing cell data retention during read. This can be achieved by the wordline read retention voltage (WRRV). WRRV deals with the estimation of boosting the wordline above nominal supply voltage and finding the highest voltage for which the data can be preserved during a read cycle. The difference between this boosted wordline voltage, for which data can be retained during read, and the nominal supply voltage is WRRV.

Fig. 8 shows the setup for estimation of WRRV of 6T SRAM cell. The method of estimating the WRRV is the same as that of the SRRV except the wordline voltage is not fixed here at $V_{\mathrm{DD}}$ .

After initializing the SRAM cell to a known state (in our case BL is at `0' and BLB is at `1'), both the bit lines are precharged at $V_{\mathrm{DD}}$ and WL is also activated so as to have read operation. Also, the cell supply voltage $V_{\mathrm{CELL}}$ here is fixed at $V_{\mathrm{DD}}$ . The WL voltage is then ramped above $V_{\mathrm{DD}}$ and current across the bit-line (which is initially at `0' state) $I_{\mathrm{BL}}$ (BL in our case) is monitored.

The WL voltage is connected to the voltage source here with the specified step sizes. The initialization step of the WL supply voltage is about 0 to 700 ns for which the voltage is 450 mV. After this initialization step, the time is increased in steps of 6.50 $\mu$ s and the voltage is also increasing in steps of 45 mV. So that at the end of 60 $\mu$ s the voltage applied is 750 mV.

At a sufficiently high voltage (WL), there is a sudden drop in the value of $I_{\mathrm{BL}}$ . This is the point, where the SRAM cell loses its preserved state during read operation. The reason for this read failure is the exacerbated read stress as access transistor M5 dominates M2 and the cell state has flipped. Thus, the WRRV of an SRAM cell is defined as the difference between WL voltage causing $I_{\mathrm{BL}}$ to drop abruptly and $V_{\mathrm{DD}}$ . Similar to SRRV, when WRRV $=$ 0, the SRAM cell is in normal read operation with WL, BL, BLB and $V_{\mathrm{CELL}}$ all biased at $V_{\mathrm{DD}}$ . While WRRV > 0, implies the boosted WL value that can be given to SRAM cell without disturbing the read preserved state. Thus, WRRV can be used to measure the maximum tolerable reduction in the $\beta$ -ratio, but here it is through the use of increased $V_{\mathrm{GS}}$ of the pass-gate transistor before flipping the cell state during read^[12].

4.3 Analysis of SRRV and WRRV with sizing ratio

In the present work, the SRRV and WRRV, both are measured in the 6T SRAM cell at 45 nm technology. The nominal supply voltage here is 450 mV.

For SRRV, the read disturbance has been observed at 360 mV. So, the SRRV here in this case is $450-360=$ 90 mV. The process is repeated for SRAM cell with different CR (cell ratio) ratios. The plots of $I_{\mathrm{BL}}$ with $V_{\mathrm{CELL}}$ is given in Fig. 9. The peak current is achieved at about 400 mV in each case. For CR $=$ 6, the peak current is six times more than the peak current for CR $=$ 1. From the plot it is clear that the amount of current rise and fall with respect to supply voltage decreases as the cell ratio decreases. This means that CR $=$ 1 is the limit for which the decreased supply voltage can be 360 mV without read failure. From this, it is clear that SRRV can effectively track the SRAM $V_{\mathrm{min, RD }}$ and are therefore suitable for $V_{\mathrm{min, RD}}$ estimation.

For WRRV, the read disturbance has been observed at 650 mV. So, the WRRV here in this case is 200 mV. The process is repeated for SRAM cell with different CR (cell ratio) ratios. The plots of $I_{\mathrm{BL}}$ with boosted WL is given in Fig. 10.

The peak current is achieved at about 600 mV in each case. For CR $=$ 6, the peak current is six times more than the peak current for CR $=$ 1. So, the cell has to deal with higher current at higher CR for the read stability of the cell.

From the plot it is clear that the amount of current rise and fall with respect to supply voltage increases as the cell ratio increases. Here, CR $=$ 6 is the limit for which the increased supply voltage can be 650 mV without a read failure. At this point, the bit line current drops at 625 mV means the WRRV is 175 at this CR ratio. It means that the wordline read retention voltage for higher CR has been decreased from 200 to 175 mV i.e. now the bitcell is unable to tolerate the stress at higher voltage and bitline current declines at an early voltage of 625 mV for CR $=$ 6. This can be clearly observed from this plot that WRRV reduces with increase in the CR ratios.

4.4 Discussion

SRRV is a measure of the maximum tolerable reduction in the $\beta$ -ratio while maintaining the preserved data during a read cycle. As the supply voltage is reduced for the estimation of SRRV, the $V_{\mathrm{GS}}$ of the pull down decreases. Due to this the current driving capability of the pull down device decreases. So, at a particular reduced supply voltage the pull down device becomes unable to hold the data and the SRAM cell loses its capability to preserve the data. We know that CR is defined as the ratio of the aspect ratios of pull down device to that of an access device and for the read stability of the SRAM cell CR plays an important role. The CR should be larger for better read stability. Here, SRRV and WRRV analysis with CR has been performed to find out the limit of minimum CR that can be used for the read stability of SRAM. Further, when we consider the cell ratios, the reduction of CR means reduction of the aspect ratio of pull down compared to that of the aspect ratio of the access transistor. Due to this, the driving capability of the pull down device decreases. So, CR $=$ 1 here, is the limit for further reduction of the cell ratio for the SRRV of 90 mV.

The comparison of the SRRV plot with reported results^[20] is shown in Fig. 11. This can be clearly observed that the results obtained are closely matched with the reported result. The SRRV here is plotted for the CR $=$ 1 and PR $=$ 1, i.e. the worst case, amongst all the cases as discussed before, for the SRRV measurement. The simulation result is in fact 0.69% better than the reported results for the worst case. The voltage, at which the $I_{\mathrm{BL}}$ (Bitline current) shows a drop, is found to be lesser for the simulated SRRV when compared with the reported data^{[20, 12]}.

WRRV can be used to measure the maximum tolerable reduction in the $\beta$ -ratio, but here it is through the use of increased $V_{\mathrm{GS}}$ of the pass-gate transistor before flipping the cell state during read. As WL increases, the driving capability of access transistor increases while the driving capability of the pull down device remains the same. For the successful read operation, the pull down transistor must be stronger than the access transistor. So at higher wordline voltage the pull down device becomes so weak compared to the access transistor and is unable to preserve the data and the SRAM cell loses its retention capability.

The WRRV obtained from the simulations are compared in Fig. 12 with the reported results^[20]. As can be clearly seen from the plot the WRRV obtained here is even better than the reported results. The WRRV value obtained from simulation is 10.3% better when compared with the published data^[20]. It has been found from the simulation that SRAM cell can accommodate 10.3% more read stress without read failure when compared with the published data for WRRV.

5. Conclusion

The DRV for 6T SRAM cell is obtained and compared with the analytical model. Both the values come out equal. Then the sensitivity analysis for DRV is performed. The variation of DRV with temperature and aspect ratio variations is analyzed. Further, the simulations are performed to find the read stability in terms of read retention voltage. Supply read retention voltage here is found out by computing the minimum supply voltage that can be applied while retaining the cell's data without failure during a read cycle. Further, for the wordline read retention voltage, the highest value of the applied word-line voltage is found out, that can be given to wordline, as an exacerbated read stress without read failure. SRRV and WRRV are then analyzed for different CR. The values of SRRV and WRRV in the present case come out equal to 90 and 200 mV, respectively. For the validation of accuracy, the results are also compared with the published results. The comparison shows the results obtained are closely matched and even better than the existing results.