1. Introduction

Recently, flash memories have been widely used in the rapidly increasing portable electronic equipment market as nonvolatile storage of data and code for high speed and low power consumption^{[1, 2]}. With the development of the microelectronic technology, the long battery life of these portable electronic systems becomes a key design aspect, which needs low power consumption. Reducing the power supply voltage^[3-8] is a conventional way to resolve the low-power requirement in the portable electronic systems. Thus, to accommodate the present voltage reduction trends, a low-voltage flash memory is needed.

The read path consisting of address decoder, sense amplifier and output buffer determines the read speed of flash which is significantly affected by the sense amplifier's speed performance^[9]. As a result, the real design challenge is to design a low-voltage and high-performance sense amplifier as the power supply is lowered further.

Current-mode sense amplifiers read the information stored in the selected cell by comparing the selected cell current with the reference current under the read operation condition, which has many advantages over voltage-mode sense amplifiers. Consequently, low-voltage, current-mode, sense amplifiers^{[10, 11]} are among the most widely used circuits in flash memories. The proposed solutions in Refs. [10, 11] use an inverter as the output stage. However, the threshold voltage of the current mirror transistor is accumulated to the drain of the reference cell, which results in that these sense amplifiers are not suitable for low power supply voltage systems. The solutions presented in Refs. [12, 13] make use of a folded-cascode scheme to cause the read operation to be carried out under low voltage. The drawbacks to this scheme are that the precision of these circuits is low due to more current subtraction operations and current mirrors (especially for work in Ref. [13]). Obviously, the power consumption is also high. The solution presented in Ref. [14] implements low-voltage operation by separating the drain and gate of the current mirror transistor to eliminate the threshold voltage limitation. However, there also exist many current mirrors in this scheme, which cause the performance to be low in terms of precision and speed. In Ref. [15], a resistor mirror is used to substitute for the conventional transistor mirror to eliminate the threshold voltage limitation. The circuit scheme can work well under low voltage with high speed. However, the area consumed by the scheme is large, which increases cost of the product applied by the scheme.

This paper focuses on a novel low-voltage sense amplifier for flash memory. This sense amplifier uses clamp technique based on a two-stage operational amplifier to avoid the effect of threshold voltage of the transistor mirror, capable of operating at a voltage as low as 1 V. Simultaneously, a dummy bit-line structure without pull-down current is used to generate a reference voltage having low power consumption and high precision.

2. Conventional sense amplifier

Fig. 1 is the conventional sense amplifier structure. The split-gate cell is used as memory cell in this paper. Every memory cell is connected to a bit-line by its drain. As is known, an erased cell has a low threshold voltage, giving a high-level current under the bias condition, and a programmed cell has a high threshold voltage, giving a low-level current. So, the reading operation of a flash memory is performed by sensing the current of the selected cell. In reality the specific method achieving the read operation is usually to compare the selected cell current with a reference current generally provided by another cell in another sector. The clamp transistors (M1 and M2 in Fig. 1) and feedback inverters make up the clamp loop, which respectively clamps $V_{\rm DR}$ and $V_{\rm DA}$ to the target value. The current mirror M3-M4 is used to mirror the reference cell current in proportion to the drain of transistor M4, whose aspect ratio is set to be lower than one. Since the pre-charge operation plays a fundamental role in any sensing scheme for flash memories, usually this task is triggered by the PREB signal. After pre-charge, the sense amplifier enters the sensing stage. The SO is sensing node and the voltage $V_{\rm SO}$ is pulled down to around the clamp voltage $V_{\rm DA}$ (selected cell is erased cell) or pulled up to around $V_{\rm DD}$ (selected cell is programmed cell). The comparator COM compares the sensed voltage $V_{\rm SO}$ and reference voltage $V_{\rm REF}$ and then issues the comparison result by the output voltage $S_{\rm OUT}$.

However, one limitation for this method lies in that the sensing amplifier cannot normally function with progressively lowered supply voltage due to the threshold limitation of the current mirror transistor M3. When read operation is performed, the $V_{\rm SO}$ approaches $V_{\rm DD}$ (programmed cell) or $V_{\rm DR}$ (erased cell) during sensing and then is compared with $V_{\rm REF}$ (usually set as the medium value of $V_{\rm SO}$ and $V_{\rm DR}$) to generate $S_{\rm OUT}$. But as the $V_{\rm SO}$ is uncertain after pre-charge in this sensing amplifier, so the aptitude of variation on $V_{\rm SO}$ may be $V_{\rm DD}$-$V_{\rm DR}$, which delays the sensing time further, reducing read speed.

The proposed sense amplifier (Fig. 2) is to remove the threshold voltage limitation of current mirror transistor by employing reference current generation circuit using two-stage operational amplifier clamp, to speed up the sensing speed by ensuring the sensing node voltage is equal to reference voltage after pre-charge end and to improve power consumption and read precision by reference voltage generation circuit using dummy bit-line without pull-down current.

3. Proposed sense amplifier circuit

To satisfy the requirement of low-voltage and low-power application, the conventional structure is modified by introducing a new reference current generating approach based on two-stage operational amplifier clamping scheme, and a reference-voltage-generating scheme without pull-down current making use of bit-line capacitance. Fig. 2 is the proposed sense amplifier in the paper. The section below will describe the design of the low-voltage sense amplifier from two parts mentioned above.

3.1 Low-voltage reference current generation circuit

To remove the threshold limitation of the current mirror transistor, a reference current generation circuit consisting of two-stage operation amplifier is proposed in this paper (in Fig. 2). The two-stage operational amplifier made up of error amplifier OP1 and PMOS transistor M7, clamps the drain side of the reference cell to a target voltage value. The PMOS transistor M7 is used as the output stage in the two-stage operational amplifier with full feedback, which not only makes up a current mirror with PMOS M8 by connecting their gate, but also lowers the minimum supply voltage through the low dropout of PMOS transistor. The relation between $V_{\rm DR}$ and $V_{\rm REF}$ is shown in Eq. (1).

$V_{\rm DR} =V_{\rm REF} {\frac{1}{1 / A+1}} .$

(1)

The A is the open loop gain of two-stage operational amplifier. Obviously, when the A is large enough, the Eq. (1) can be represented by Eq. (2) below. What is more, the larger the A is, the higher the precision.

$V_{\rm DR} \approx V_{\rm REF} .$

(2)

As is well known, instability exists in a loop system when the number of the poles is larger than or equal to two. The small signal model of the two-stage operational amplifier (in Fig. 2) is shown in Fig. 3. In Fig. 3, $g_{\rm m}$ is the equivalent trans-conductance of the OP1 and $R_{\rm o1}$, $C_{\rm o1}$ are respectively the equivalent resistor and capacitance in the output of OP1. $g_{\rm m7}$ is the trans-conductance of the transistor M7. $R_{\rm o2}$ and $C_{\rm o2}$ are respectively the equivalent resistor and capacitance in the output of the two-stage operational amplifier. Obviously, there are two poles in the two-stage operational amplifier clamp. They are P$_{\rm O1}$ and P$_{\rm O2}$, lying in the output of OP1 and PMOS M7 and illustrated in Eqs. (3) and (4). However, the two poles will cause the instability problem of the two-stage operational amplifier in closed loop. So, the capacitor $C_{\rm m}$ (included in $C_{\rm o1})$ is added into the circuit in the design. A significant role played by the capacitor $C_{\rm m}$ is to split two poles of two-stage operational amplifier. Consequently, the output pole of the OP1 is located within the unit gain frequency. Another role played by the capacitor $C_{\rm m}$ is to eliminate noise caused by power supply instability and read operation. Fig. 4 shows the Bode plot of the two-stage operational amplifier. Obviously, the loop is stable.

$P_{\rm o1} =\frac{1}{R_{\rm o1} C_{\rm o1} },$

(3)

$P_{\rm o2} =\frac{1}{R_{\rm o2} C_{\rm o2} }.$

(4)

3.2 The reference voltage generation circuit without pull-down current

The simplified waveforms of reading data-0 and reading data-1 for the sense amplifier shown in Fig. 2 are shown in Fig. 5 respectively. In the pre-charge phase, node SO and node DUM are pre-charged to basically have the same voltage level, namely $V_{\rm DD}$-$V_{\rm T (MN1, 2).}$ After pre-charge, the voltage on node DUM is kept constant by the bit-line capacitor. Node SO is continually pre-charged, and finally the voltage level is close to $V_{\rm DD}$ level for the case of reading data-0 during the real sensing phase. For the case of reading data-1, the node SO is discharged by the sensed cell current, and finally is nearly pulled down to approach the voltage level of node DA which is about $V_{\rm REF}$. Obviously, the sensing margin for reading data-0, $\Delta V_{0}$, is as follows:

$\Delta V_0\approx V_{\rm DD} -( {V_{\rm DD} -V_{\rm T(MN1, 2)} })=V_{\rm T(MN1, 2)} .$

(5)

The sensing margin for reading data-1 is as follows:

$\Delta V_1\approx ( {V_{\rm DD} -V_{\rm T(MN1, 2)} })-V_{\rm DA} =V_{\rm DD} -V_{\rm T(MN1, 2)} -V_{\rm REF}.$

(6)

$\Delta V_{0}$ and $\Delta V_{1}$ is large enough to avoid incorrect sensing case and improve bits sensing speed. In the paper, the sensing margin is designed to be about 200 mV. The clamped voltage of the bit-line is around 500 mV. This sense amplifier can work at voltage level as low as 0.9 V.

The largest advantage of the reference voltage generation circuit in the paper, compared with conventional one, is that no pull-down current is needed, which improves the power consumption of the sense amplifier. The reference voltage $V_{\rm DUM}$ is kept constant by the bit-line capacitor after pre-charge, which is used to be compared with the voltage of node SO for issuing the reading result during sensing.

The critical point of the sense amplifier design is that the voltage $V_{\rm SO}$ is equal to the voltage $V_{\rm DUM}$ after pre-charge, which makes the maximum voltage variation of the sensing node SO to be $\Delta V_{0}$ or $\Delta V_{1}$. In the conventional circuit, the maximum variation of the sensing node is usually $\Delta V_{0}+\Delta V_{1}$, which delays the sensing time of the conventional sense amplifier.

4. Experimental results

The low-voltage sense amplifier presented in the previous section was integrated in a flash fabricated in 90 nm flash technology for validating the performance of the proposed structure, and some simulation results and experimental results are illustrated in this paper. Fig. 6 illustrates the simulated transient results of the proposed sense amplifier. In the simulation, the power supply is set to be 1.08 V (target for 1.2 V with design margin of about 10%) for illustrating the capability of the proposed sense amplifier. Obviously, there are three parts of time existing in the read time taken by a sense amplifier. They are pre-charge time, sensing time and comparing time. Among them, the sensing time is longer than the other two parts. Table 1 gives the summary of reference current generating circuits in Refs. [3, 13-15] and this work. As can be seen, the active current of this work is very low (about 10 $\mu$A), but startup speed is slower than other publications. So the circuit needs to always be on when it is used in high-speed sense amplifier.

Fig. 7 illustrates the summary of simulation results of the works of Refs. [13, 14] and this work, for showing the performance improvement of the sense amplifier in terms of the read time. The relative simulation conditions are: slow corner, $T=125$ ℃, and bit-line parasitic capacitance $C_{\rm BL}=0.3$ pF. In addition, taking into account the cell current spread due to process variation and cycling operation, the erased cell current is set to 16 $\mu$A, and the programmed cell current is set to 2 $\mu$A. From Fig. 6, it can be seen that the performance of the proposed solution in the paper is significantly improved, compared with other literal works according to read speed. In addition, it is also seen that the read time is sensitive to the power supply for all works illustrated. What is more, the read time decreases with rising of power supply.

The chip microphotograph of the flash with the proposed sense amplifier is shown in Fig. 8 (at the top of the next page), and the sense amplifier takes up an area of about 390 $\mu$m². Relative experimental results are plotted in Fig. 9 called a Shmoo plot. The Shmoo plot shows the access time over a range of voltages. The test is operated in the die from slow wafer at 125℃. it can be seen that the access time at voltage of 1.2 V is $64 \times (148-125)/101=14.7$ ns, and the access time at voltage of 1.5 V is $54 \times (148-125)/101=12.3$ ns. These test results are very close to the simulation results.

5. Conclusion

A new low-voltage sense amplifier for flash memory has been presented in this paper. The low-voltage reference current generator based on two-stage amplifier and the dummy bit-line without pull-down current for global reference voltage, are employed to realize low-voltage and low-power performance. Obviously, the read time is enhanced much in accordance with the simulation results.