1. Introduction

As a promising candidate for the next-generation power electronic device, AlGaN/GaN HEMT shows strong potential for high-power and high-frequency applications with its unique properties ^[1-3]. The conventional GaN HEMT is a depletion mode device and an enhancement mode device is highly desirable in the application due to the fail-safe operation and its simplified circuit design. Several approaches have been proposed to realize the E-mode GaN HEMT, such as gate recess ^[4-6], fluorine ion implantation ^[7-9], p-GaN cap ^[10] etc. Among them, the gate recess and fluorine ion implantation MIS-HEMTs are considered as promising candidates because they allow low gate leakage current as well as large gate swing. However, it still remains challenging to obtain stable E-mode MIS-HEMT. For gate recess structure, the high-density traps with short and long emission time constants $\tau_{\mathrm{it}}$ at the dielectric/(Al)GaN interface were caused by gate recessing, and the dynamic charging/discharging processes of these interface states' traps can lead to the threshold voltage instability issue when a high off-state $V_{\rm DS}$ stress is applied to the device ^[11]. For fluorine ion implantation MIS-HEMT, one important issue to address is the stability and reliability of the fluorine ions, and consequently the threshold voltage stability during the device operation, especially under high electric-field electrical stress or high temperature stress application ^{[11, 12]}.

In this study, a novel dual-gate E-mode MIS-HEMT device that is based on a cascode connection of an E-mode and a D-mode gate is proposed and analyzed using Atlas simulation toolbox by Silvaco. The on-state as well as off-state electrical performances are investigated. In comparison with that of conventional E-mode HEMT, the electric field concentration under the E-mode HEMT gate is effectively suppressed, which is transferred to the area under the D-mode HEMT gate during the off-state stress period. Thus, the proposed dual-gate structure can highly improve the electric field under the gate-related reliability, such as, threshold voltage stability. In order to better understand the dynamic charging/discharging processes, a specific example of acceptor-like traps is introduced at the interface of AlGaN/Si $_3$ N $_4$ to simulate and discuss the interface states trap-induced $V_{\rm th}$ instability issue. The results show that the proposed structure can effectively decrease variation of ionized traps, and consequently improve the threshold voltage's stability.

2. Simulation and analysis

Fig. 1(a) illustrates the equivalent circuit of the proposed novel E-mode MISHEMT. Implementations of the device are illustrated in Figs. 1(b)-1(d). The hybrid E-mode MISHEMT presented in Fig. 1(b) is formed of an E-mode and a D-mode MISHEMT. The source electrode of the E-mode and the gate electrode of the D-mode MISHEMT are electrically connected. The source electrode of the D-mode MISHEMT is electrically connected to the drain electrode of the E-mode MISHEMT, leading to the conductive current being controlled by the gate of E-mode MISHEMT. Compared to the device of Fig. 1(b), the stack configuration shown in Fig. 1(c) has lower parasitic inductance and can also reduce the cost of fabrication and packaging. Moreover, considering that the contacts that form the drain of E-mode and the source of D-mode MISHEMT are not used for any functional purpose during device operation, these contacts are omitted in Fig. 1(d), showing the proposed E-mode MISHEMT structure.

2.1 The structures of the conventional and the proposed E-mode MIS-HEMT

The schematics cross-section and key parameters of the optimized novel E-mode MIS-HEMT and conventional gate recessed MIS-HEMT are shown in Figs. 2(a) and 2(b) respectively. The proposed dual-gate structure consists of a 20 nm Al $_{\mathrm{0.2}}$ Ga $_{\mathrm{0.8}}$ N barrier layer, a 180 nm GaN buffer layer and a Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ passivation layer on the top. The lengths of the E-mode and D-mode gates are 300 nm. The source-to-gate and drain-to-gate spaces are 1 $\mu$ m ( $L_{\mathrm{GS}}=1$ $\mu$ m) and 4.2 $\mu$ m ( $L_{\mathrm{GD}}=4.2$ $\mu$ m), respectively. It features a distance between two gates of 600 nm ( $L_{\mathrm{G1G2}}=600$ nm). To achieve the positive threshold voltage, a recess depth of 18 nm with 2 nm AlGaN left is performed under the gate. The gate dielectric for both gates is set to be 8 nm Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ . The conventional gate recess structure shares all structural parameters with the proposed E-mode MIS-HEMT, except for the existence of the D-mode gate.

The Shockley-Read-Hall recombination model ^{[13, 14]} and the Caughey and Thomas field-dependent mobility model ^[15] are included in all simulations. Material parameters of GaN and AlN used in the Atlas simulations and calculated in Poisson's equation, continuity equations for electrons and holes, and transport equations using the drift-diffusion model are extracted from Ref. [16]. The spontaneous and piezoelectric polarizations of the wurtzite polarization model are taken into account using the built-in self-consistent polarization model of the Atlas toolbox by Silvaco ^[17]. To model the mechanism of traps, electrons that are emitted or captured are considered to maintain charge self-consistency, modifying the recombination rate in the carrier continuity equations of Shockley-Read-Hall recombination model ^[18].

2.2 Basic electrical characteristics

Fig. 3 shows the comparisons of DC characteristics of the conventional gate recess device and proposed E-mode device. The threshold voltages of 0.3 V for both devices were obtained by linear extraction The maximum $G_{\mathrm{m}}$ values are 325 mS/mm at $V_{\mathrm{GS}} =24$ V and 321 mS/mm at $V_{\mathrm{GS}} = 22$ V for conventional gate recess device and proposed E-mode device respectively The conventional gate recess device exhibits a maximum drain current of 860 mA/mm while the proposed device's maximum drain current is 793 mA/mm at $V_{\mathrm{GS}} = 10$ V and $V_{\mathrm{DS}} = 5$ V, as shown in Fig. 3(a); the slight difference (67 mA/mm) can be explained with the Schottky barrier altitude of the D-mode gate contact. The output characteristics of two devices are shown in Fig. 3(b). The on-state resistance of 4.06 $Ω \cdot$ cm $^{\mathrm{2}}$ and 4.78 $Ω \cdot$ cm $^{\mathrm{2}}$ are both obtained at $V_{\mathrm{GS}} =5$ V for conventional device and proposed device, respectively. All these results show almost no degradation compared with that observed in the conventional E-mode MIS-HEMT, except a slight decrease on maximum drain current due to the introduction of the D-mode gate.

2.3 Distribution of the off-state electric field

Considering no obvious degradation is observed in basic electrical performance, the off-state characteristic is investigated. Fig. 4 presents the distribution of off-state electric field at $V_{\mathrm{DS}} =100$ V and $V_{\mathrm{GS}} =0$ V for both structures. The electric field concentration under the gate is effectively suppressed for the proposed device. The highest electric field intensity of the entire device (5.5 MV/cm) locates underneath the drain edge of the gate for conventional structure, and it is transferred to the edge of D-mode gate in the proposed structure with a value of 3.0 MV/cm. As shown in Fig. 5(a), the maximum electric field at Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ /AlGaN interface under the gate are 2.83 MV/cm and 0.83 MV/cm for conventional gate recess device and proposed E-mode device, respectively. Fig. 5(b) gives the distributions of electric field at Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ /AlGaN interface for both structures, and it is obvious that the peak electric field (2.83 MV/cm) at the gate edge is weakened to 2.49 MV/cm and moved to the area under the D-mode gate during the off-state stress period. It should be noted that the recess gate determining the device's $V_{\mathrm{th }}$ of the proposed device is shielded from the high electric field, even under high drain voltage.

2.4 Discussion of the electric field suppression

For verification and to better understand the suppression effect for the electric field under gate, more simulation and discussion are performed. Considering Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ thickness under the D-mode gate and distance between two gates are two important design parameters, relative simulations are carried out and analyzed. The electric field distribution at Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ /AlGaN interface as a function of the Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ thickness is simulated and given in Fig. 6(a) The peak electric field under E-mode gate of 1.15, 1.70, and 1.91 MV/cm was extracted from Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ thickness of 20, 100, and 300 nm, respectively. The electric field at edge of the D-mode gate is decreased from 2.41 to 1.54 MV/cm and continues to fall to 1.06 MV/cm For comparison, the electric field intensities are 2.85 and 0.62 MV/cm at the corresponding area for conventional gate recess device. According to this result suppression effect for the electric field is discovered with different Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ thickness, but there is a tradeoff between these two electric field distributions. With the increase of the Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ film thickness, the electric field under E-mode gate increases whereas electric field concentration under the D-mode gate is reduced. When the Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ thickness reaches to 300 nm or more than 300 nm, the suppression effect is similar to the device with source field plate, and more detailed discussion will be conducted in Section 2.6.

Fig. 6(b) presents the relationship between the distance between two gates and electric field distribution. Distinguishable electric field transfer effect is found with the variety of $L_{\mathrm{G1G2}}$ , and the electric field concentration moved to the edge of the D-mode gate along with the change of distance between two gates. Moreover, good suppression effects for electric field under the E-mode gates are achieved for all structures (less than 0.82 MV/cm). Therefore, the proposed structure is believed to transfer the electric field concentration at the gate edge and have an effective suppression effect for the electric field under the gate.

2.5 Improvement of threshold voltage stability

It has been proven that the charging/discharging behavior of dielectric/(Al)GaN interface states is related to the electric field intensity at the interface ^[19]. In order to better understand this process, a specific example of acceptor-like traps is introduced at the interface of Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ /AlGaN to measure the interface states-induced $V_{\mathrm{th}}$ shift, the acceptor level is set at 0.35 eV below the conduction band, and the density is fixed at a typical value of 1 $×$ 10 $^{\mathrm{13}}$ cm $^{\mathrm{-2}}$ based on the work of Refs. [19, 20]. The Si $_{\mathrm{3}}$ N $_{\mathrm{4}}$ thickness under the D-mode gate and distance between two gates are set to be 8 and 600 nm for consistence and convergence. Both of the structures are first biased with $V_{\mathrm{GS}} = 0$ V and $V_{\mathrm{DS}}= 0$ V for original state, then voltage stress with $V_{\mathrm{DS}} =100$ V and $V_{\mathrm{GS}} = 0$ V is applied to devices for 1 ms, finally returning to the original state. Besides, a longer stress time of 10 ms is performed to verify the effectiveness of the proposed structure on a longer timescale.

Fig. 7 shows the distribution of the ionized traps for both structures at original state, after the 1 ms off-state stress and after the 10 ms off-state stress. It is clearly observed that the variation of ionized traps' density before and after the off-state stress is effectively decreased in the proposed structure due to its suppression of the electric field under the gate. As shown in Fig. 8(a), for conventional E-mode HEMT, the densities of ionized traps at the gate edge ( $x=0.3$ $\mu$ m) are 1 $×$ 10 $^{\mathrm{13}}$ , 8 $×$ 10 $^{\mathrm{5}}$ and 2 cm $^{\mathrm{-2 }}$ for original state, after the 1 ms off-state stress and after the 10 ms off-state stress, respectively, meanwhile the ionized state density shows an overall decrease for the entire space under the gate. It is believed that the variation of ionized traps' density accounts for the change of the charge density under the gate, which causes $V_{\mathrm{th}}$ instability ^[21]. For comparison, Fig. 8(b) gives the density of the ionized traps under the gate of the proposed structure for three states. A slight difference was observed before and after off-state stress, suggesting that the proposed structure is effective for suppressing the variation of ionized traps density. So the proposed structure can prevent the shift in $V_{\mathrm{th}}$ and improve reliability by shielding the gate with D-mode gate from high electric-field.

2.6 Comparison with device with source field plate

To better understand the difference between the device with source field plate and the proposed dual-gate device, the simulation of the device with source field plate was performed. Fig. 9(a) shows the schematic cross-section of conventional gate recess device with source field plate, which shares the same structural parameters and the introduction of acceptor-like traps of conventional gate recess device except for the source field plate. The thickness of Si $_3$ N $_4$ under the field plate is 400 nm, based on Ref. [22]. The source field plate extension at the drain 2.2 $\mu$ m. Other parameters and simulation settings are the same as that of the proposed structure.

Fig. 9(b) presents simulated electric field distribution and density of ionized traps under the gate of conventional gate recess device with source field plate, showing a good agreement with expected modulation effect on the electric field of the source field plate ^[22]. However, an electric field peak of 1.95 MV/cm at the edge of the gate and an obvious decrease in the density of ionized traps are observed. After comparison with the proposed structure, the proposed novel E-mode MIS-HEMT exhibits a more effective suppression of electric field under the gate and a simplified fabrication process with a single step of gate metal photolithography.

3. Conclusion

A novel AlGaN/GaN E-mode HEMT with a dual-gate structure was proposed and simulated by Silvaco Atlas. The dual-gate device is based on a cascode connection of an E-mode and a D-mode gate. The electric field under the gate is effectively suppressed, which is transferred to the area under the D-mode HEMT gate during the off-state stress period. As a result, the proposed structure can effectively decrease variation of ionized traps, and consequently improve the threshold voltage's stability by shielding the E-mode gate with a D-mode gate from high electric field.

Acknowledgments: We thank the Suzhou nanofabrication facility of SINANO, CAS, for the fabrication, characterization and testing of the AlGaN/GaN MIS-HEMT.