Fig. 1.
Proposed SAR ADC architecture.
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| Citation: |
Jihai Duan, Zhiyong Zhu, Jinli Deng, Weilin Xu. An 8 bit 1 MS/s SAR ADC with 7.72-ENOB[J]. Journal of Semiconductors, 2017, 38(8): 085005. doi: 10.1088/1674-4926/38/8/085005
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J H Duan, Z Y Zhu, J L Deng, W L Xu. An 8 bit 1 MS/s SAR ADC with 7.72-ENOB[J]. J. Semicond., 2017, 38(8): 085005. doi: 10.1088/1674-4926/38/8/085005.
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Abstract
This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply. -
References
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