Citation: |
Jiaqi Yang, Ting Li, Mingyuan Yu, Shuangshuang Zhang, Fujiang Lin, Lin He. On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs[J]. Journal of Semiconductors, 2017, 38(8): 085007. doi: 10.1088/1674-4926/38/8/085007
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J Q Yang, T Li, M Y Yu, S S Zhang, F J Lin, L He. On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs[J]. J. Semicond., 2017, 38(8): 085007. doi: 10.1088/1674-4926/38/8/085007.
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On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs
DOI: 10.1088/1674-4926/38/8/085007
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Abstract
This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μ W, while the digital part consumes only 203 μ W. -
References
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