Fig. 1.
(a) Charge redistribution S/H circuit. (b) Capacitor flip-around S/H circuit. (c) Timing diagram.
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| Citation: |
Yutong Zhang, Bei Chen, Heping Ma. A sample and hold circuit for pipelined ADC[J]. Journal of Semiconductors, 2018, 39(11): 115002. doi: 10.1088/1674-4926/39/11/115002
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Y T Zhang, B Chen, H P Ma, A sample and hold circuit for pipelined ADC[J]. J. Semicond., 2018, 39(11): 115002. doi: 10.1088/1674-4926/39/11/115002.
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Abstract
A high performance sample-and-hold (S/H) circuit used in a pipelined analog-to-digital converter (ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit. A gain-boosted folded cascode operational transconductance amplifier (OTA) with a DC gain of 90 dB and a GBW of 738 MHz was designed. A low supply voltage bootstrapped switch was used to improve the linearity of the S/H circuit. With these techniques, the designed S/H circuit can reach 94 dB SFDR for a 48.9 MHz input frequency with 100 MS/s sampling rate. Measurement results of a 14-bit 100-MS/s pipeline ADC with designed S/H circuit are presented.-
Keywords:
- S/H circuit,
- bootstrapped switch,
- gain-boosted OTA
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References
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