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J. Semicond. > 2020, Volume 41 > Issue 11 > 112401

ARTICLES

A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

Xiangxin Pan, Xiong Zhou, Sheng Chang, Zhaoming Ding and Qiang Li

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 Corresponding author: Qiang Li, qli@uestc.edu.cn

DOI: 10.1088/1674-4926/41/11/112401

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Abstract: This paper proposes a technique that uses the number of oscillation cycles (NOC) of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The analysis of the number of bit cycles, power and static performance shows that three adaptive bypass windows reduce power consumption, and decrease DNL and have similar INL, compared with the SAR ADC without bypass windows. In addition, a 1-bit split-and-recombination redundancy technique and a general bypass logic digital error correction method are proposed to address the settling issues and optimize the size of the bypass window. This design is implemented in 40 nm CMOS technology. The conversion frequency of the ADC reaches up to 30 MS/s. The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input, consuming 380 μW, down from 427 μW without multiple adaptive bypass windows, at a 1.1 V supply, resulting in a figure of merit (FoM) of 5.69 fJ/conversion-step.

Key words: adaptive bypass windownumber of oscillation cycles (NOC)offsetsplit-and-recombination redundancySAR ADCVCO-based comparator

Low power and high resolution analog-to-digital converters (ADCs) are widely used in mobile, wearable and implantable devices, the internet of things (IoT) and so on. Successive approximation register (SAR) ADC exhibits excellent energy efficiency and has attracted much attention due to its digital-like nature and adaptability to advanced CMOS technology. Much work is occuring to reduce the logic power consumption, such as a variety of switching schemes to save part of the energy of CDAC[1-6]. From a systematic perspective, the bypass logic shown in Fig. 1, can not only save energy from CDAC but also greatly reduce the energy from the comparator and digital logic[7]. When the input voltage is within the range called the bypass window, the intermediate bit cycles can be skipped completely and does not influence the correct output. However, the bypass window comes at the cost of two additional coarse comparators and an external reference, which increases design complexity and makes the precision partially dependent on the reference voltage.

Figure  1.  Conversion process of 6-bit SAR ADC. (a) Conventional SAR ADC. (b) SAR ADC with bypass window.

The comparator is a fundamental consideration in SAR ADC, which is an indispensable but power-hungry block. The input-referred noise constrains the power consumed by the comparator. For a voltage-domain comparator such as a double-tail comparator or strong-arm comparator, whose noise reduction relies on brute-force analog scaling, it requires four times the power to halve the input-referred noise[8]. Alternatively, time-domain comparators, which show good potential in power efficiency and scalability, attract attention due to their digital nature and more choices for lower noise such as VTC-based[9], VCDL-based[10], oscillator collapse-based[11] and VCO-based[12, 13]. The last type gains much favor under its noise-adaptive characteristic. It can generate output signal without oscillation if the input voltage is large. When the input voltage is small enough, it will oscillate until the decision is made. In other words, there is a relationship between the input voltage and the oscillation number, which shows that the oscillation number indicates an inherent coarse quantization.

Apart from making decisions and employing the decisions to reduce the comparator noise[14-16], a VCO-based comparator offers extra information, known as the number of oscillation cycles (NOC)[17], to detect whether the input signal of the comparator is in the vicinity of common-mode voltage. This information can be utilized to trigger bypass logic, which avoids the use of additional comparators and reference. It can be triggered at any bit as long as NOC reaches a specific number. Furthermore, multiple bypass windows can be constructed by NOC, which provide more power reduction and static performance improvement. The windows size can be adaptively adjusted to PVT variations on the basis of the NOC and window detection logic.

This design takes full advantage of the potential of a VCO-based comparator as a bypass detector served, which can be used for higher resolution (12 bit) and higher speed (30 MS/s) SAR ADC[18]. The structure of the VCO-based comparator and the consideration of the offset caused by different NOC are presented. The design of core digital circuits is described thoroughly. The benefits of bit cycles decrease, power reduction and static linearity improvement from adaptive multiple bypass windows are analyzed. For compensating the settling error from DAC and reference because of high resolution and speed, a 1-bit split-and-recombination redundancy[19] and a general method to correct digital errors for bypass logic are proposed, which circumvents the use of complex or off-chip calibration circuits.

This paper is organized as follows. Section 2 describes the overall ADC architecture, operation principle and building blocks. Section 3 analyzes the bit cycle decrease, power reduction and static performances with multiple adaptive bypass windows, and derives the maximum DNL and INL of it, while section 4 explains split-and-recombination based redundancy and a general digital error correction method for bypass logic. Section 5 presents simulation results and comparison with the state-of-the-arts, and section 6 draws the conclusions.

The architecture of the proposed SAR ADC is shown in Fig. 2 including two bootstrapped sampling switches[20], a differential capacitive DAC (with 1-bit redundancy), VCO-based comparator, NOC counter, SAR logic, bypass logic, window detection logic (three adaptive bypass windows), window update logic, and digital error correction logic.

Figure  2.  Architecture of the proposed SAR ADC.

During the sampling phase, the input differential voltage is sampled onto the top plates of CDAC by two bootstrapped switches. If the input signal is large enough, the comparator makes the decision directly without oscillation. Otherwise, if the input signal is relatively small (within several LSBs), VCO will oscillate several times to increase the delay until the time difference between two VCO loops exceeds the dead zone of the phase detector. To take advantage of the oscillation information, three bypass windows W2, W3 and W4 are used for the standing of the oscillation numbers of 2, 3 and 4, respectively. For example, if the NOC is 4, the bypass window W4 is triggered for the first time and bit cycles will move to the LSB cycle. Due to the impact of noise and PVT variation, even if the same voltage inputs into the comparator, the oscillation number might be different. The signal must be detected to determine whether it can be digitized with the remaining capacitor weights in case the result is not convergent.

Window update logic, shown in Fig. 3, can implement the window-size detection. $ V_{\rm{x}} $ and $ V_{\rm{y}} $ are the differential inputs. $ V_{\rm{B}} $ stands for the current bypass window size of W4, and its initial value is 1 LSB. If differential signals cannot cross zero (common-mode voltage), the bypass window is too small and this process of the bypass is wrong[17]. The cycle must be back to where the bypass begins and W4 is updated. The next time when the NOC is 4, the conversion process will be bypassed to the cycle of LSB + 1 and $ V_{\rm{B}} $ will become the voltage of 2 LSB. This update process also applies to W2 and W3. It is worth noting that the size of the bypass window is updated following the weights of CDAC and carried out in the background. So smaller low-weight capacitors achieves more precision bypass window sizes and the adaptive bypass windows are PVT-robust. Bypass logic cannot be triggered for more than one time in one conversion period under the consideration of conversion speed and complexity of the logic design.

Figure  3.  Window update logic. (a) Not cross zero. (b) Cross zero.

Compared with voltage-domain comparator, whose input-referred noise is often dominated by sizes of input and tail transistors[21], designing a low-noise VCO-based comparator is more flexible[17]. The more stages it uses, the lower input referred noise but lower speed for the large input voltage it possesses. For delay cells, the topologies, the sizes of transistors, the threshold voltages of transistors and filtering capacitors all influence the noise and speed[22]. It is a hard trade-off that influences the bypass window sizes. Two common different delay cells are shown in Fig. 4. When input voltage is low, the pulling down of cell II will be slow. Compared with the delay cell II[12], the inserted inverter in delay cell I increases the reset speed. The option is that four stages of the delay cell I are to be used in the proposed scheme for quicker comparison.

Figure  4.  Schematic of two common delay cells.

Some works[23, 24] utilized multiple comparators to achieve lower power consumption or higher speed[25, 26]. All these designs have the matching problem of different input-referred offset voltages, which can be solved well by the calibration method[27] or introducing redundant capacitors into the DAC[28]. Actually, a VCO-based comparator operates like multiple comparators as it oscillates for a different number of cycles while it does not need extra calibration circuit or redundant cycle. The offset problem must be analyzed very carefully.

The delay time of the unit delay stage is given by

td=CLVdd2IDS, (1)

where $ C_{\rm{L}} $ and $ I_{\rm{DS}} $ are the load capacitance and average current of the current-starving stage, respectively. And the differential voltage-to-time gain of the VCO for one oscillation cycle is given by

GVCO_1=2CLVdifgmI2DS, (2)

where $ g_{\rm{m}} $ is the trans-conductance of the tail NMOS, and $ V_{\rm{dif}} $ is the differential input voltage of the VCO comparator.

The dead zone of the PD ($ t_{\rm{dz}} $) represents the minimum detectable delay difference. The difference input voltage has the following relationship with the number of oscillations $ n $[17],

|(n1)GVCO_1Vdif|tdz<|nGVCO_1Vdif|. (3)

According to Eq. (2), Eq. (3) can be rewritten as

tdzI2DS2ngmCLVDD<|Vdif|tdzI2DS2(n1)gmCLVDD. (4)

Eq. (4) means that the number of oscillaitons is the coarse quantization of the input signal, i.e., each NOC value corresponds to an input range.

Since the current of the unbiased circuit is much larger than that of the biased transistor, the offset voltage caused by the unbiased circuit can be ignored. For one oscillation cycle, the VCO in Fig. 5 can be considered as a four-stage VCDL. Hence, according to Ref. [10], the standard deviation of the offset time due to one oscillation cycle can be written as

Figure  5.  Schematic of VCO-based comparator and phase detector.
ΔtdVCO_1=gmΔVosCLVddI2DS, (5)

where $ \Delta V_{\rm{os}} $ is the standard deviation of the input-referred offset voltage of one delay stage. And the standard deviation of the input-referred offset voltage induced by single oscillation becomes

ΔVosVCO_1=ΔtdVCO_1GVCO_1=ΔVos2. (6)

No matter how many cycles are needed in the oscillation loop, signals oscillate in the same circuit paths. The offset delay time of a fabricated chip remains unchanged for each oscillation cycle. Hence, the standard deviation of the offset time caused by n oscillation cycles is $ n\cdot \Delta V_{{{\rm{osVCO}}}\_n} $. So the input-referred offset voltage for n oscillation cycles is

ΔVosVCO_n=nΔtdVCO_1GVCO_n=ΔVos2. (7)

Eqs. (6) and (7) show that the input-referred offset voltage of the VCO-based comparator for one oscillation cycle is the same as that of n oscillation cycles.

The NAND-based phase detector (PD) is shown in Fig. 5. Compared with the DFF-based PD in Ref. [12], it needn't wait for a slower edge. Therefore, it increases the speed of the comparator. The size of the dead zone and bypass window can be tuned via load capacitors.

The dead zone of the PD can be derived as

tdz=(C3C2)Vdd2INAND, (8)

where $ C_{2} $ and $ C_{3} $ are the load capacitors at the output terminals in PD, $ V_{\rm{dd}} $ is the supply voltage and $ I_{\rm{NAND}} $ is the average switching current of NAND. The simulated results of the dead zone of PD are shown in Fig. 6, which is accorded with Eq. (8).

Figure  6.  Comparison of simulated result and Eq. (6) of the dead zone of PD.

This work employs a split capacitor switching scheme[29] from MSB to LSB + 1. Compared with many other switching schemes, it not only keeps the input common-mode voltage of comparator stable, which avoids the deterioration of linearity of ADC, but also eliminates the need of extra common-mode voltage. For the LSB, the design uses the monotonic switching procedure[30]. It can halve the total capacitance with a fixed unit capacitor. Moreover, the change of common-mode voltage caused by it is negligible. To meet the requirements of KT/C noise and matching, this design chooses the unit capacitor as 1fF. The weight of the capacitor is shown in Fig. 1.

In this design, the order of bit cycles is controlled by NOC. Bit cycles are not executed in the order of the conventional SAR ADC because of the bypass and window update logic. Registers should record the current cycle number, cycle number after bypass and the window size after window updating.

Fig. 7(a) shows the schematic and timing diagram of bit cycle control logic. It employs three window registers to record the sizes of three predefined bypass windows. Because of the relatively small size of the window, a 5-bit register can implement every window. CLR is the reset signal to reset window registers at power-up. The signal $ W\_{\rm{flag}} $ consists of $ W_{2}\_{\rm{flag}} $, $ W_{3}\_{\rm{flag}} $, and $ W_{4}\_{\rm{flag}} $. The rising edges of them mean that differential input voltage $ V_{\rm{dif}} $ triggers the corresponding window. The bypass cycle register is utilized to record the bit cycle after the process of the bypass. The decision of the comparator is indicated by the signal $ {\rm{ready}} $, and $ {\rm{ready\_d}} $ is the delay signal of $ {\rm{ready}} $. The normal cycle register is used to record the current bit cycle in the normal SA process. Enabling the bypass cycle register or normal cycle register is selected by the signal SEL. And $ \rm{Samp\_n} $ is the inverted sampling signal and $ \rm{ en}<12:1> $ is used to control the state of CDAC.

Figure  7.  Bit cycle control circuits. (a) Schematic. (b) Timing diagram.

Fig. 7(b) shows the timing diagram of the bit cycle control logic for two conversion periods. Initial CLR is low to reset the window registers. When $ {\rm{samp}}\_{\rm{n}} $ is low, both the bypass cycle register and the normal cycle register are reset. A low $ {\rm{SEL}} $ means that normal cycle register is enabled. $ {\rm{Cycle}}<12> $ is set high when the next $ {\rm{ready}}\_{\rm{d}} $ rises meaning that the 12th bit is being converted. If the bypass logic is not triggered, the SA cycle will convert the 11th cycle. However, the rising edge of $ W_{4}\_{\rm{flag}} $ means that the bypass window $ W_4 $ is triggered. A high $ {\rm{SEL}} $ enables the bypass cycle register and disables the normal cycle register. At the same time, the high $ {\rm{SEL}} $ makes $ {\rm{cycle}}<6:1> $ connect to $ {\rm{byps}}<6:1> $, and it is set to high. $ {\rm{Cycle}}<1> $ becomes high on the next rising edge, meaning that the conversion from the 11th to the 2nd bit cycle is skipped and the conversion of the 1st bit starts. The rising edge of $ \rm{error} $ indicates that $ V_{\rm{dif}} $ is outside the bypass window $ i.g. $ and the window $ W_4 $ is too small. So the value of the window register increases by one. Then $ {\rm{SEL}} $ is set to low to disable the bypass cycle register and enable the normal cycle register. At the same time, $ {\rm{cycle}}<12:1> $ is reconnected to $ \rm{ norm}<12:1> $. Therefore, the bit cycles previously bypassed is reconverted, and the 11th bit will be converted in the next cycle.

At the beginning of next sampling period, SEL is low and it is a conventional SA process. The rising edge of $ W_{4}\_{\rm{flag}} $ triggers the bypass logic. Since $ W_4<5:1> $ has increased from $ '00000' $ to $ '00001' $. Then the cycles from the 11th to the 3rd are bypassed. Missing the window size error detection during this cycle, $ {\rm{cycle}}<1> $ is set to high on the next rising edge of $ {\rm{ready\_d}} $.

In this design, the CDAC needs to be recovered after the detection of the wrong window size sometimes. The driving circuits of CDAC are shown in Fig. 8. $ {\rm{Data}}\_{\rm{d}} $ and $ {\rm{Datan}}\_{\rm{d}} $ are delay signals of the comparator output. $ \overline{\rm{Dp}} $ and $ \overline{\rm{Dn}} $ are inverted signals of $ {\rm{Dp}} $ and $ {\rm{Dn}} $, respectively. When $ \rm{rst} $ is low, $ {\rm{Dn}} $ is set to high and $ {\rm{Dp}} $ is set to low. If $ \rm{en} $ is high, high $ \rm{data\_d} $ can set $ {\rm{Dp}} $ to high and low $ \overline{\rm{Dp}} $ can lock all outputs until the next effective $ \rm{rst} $. Similarly, if $ \rm{en} $ is high, high $ {\rm{data}}\_{\rm{d}}$ can set $ {\rm{Dn}} $ to high and low $ \overline{\rm{Dn}} $ can lock all outputs until the next effective $ {\rm{rst}}$.

Figure  8.  CDAC driving circuits. (a) Blocks. (b) Schematic. (c) Timing diagram.

In the upper block in Fig. 8(a), $ {\rm{samp}}\_{\rm{n}} $ can be used as a reset signal to reset this block in the sampling phase. $ {\rm{Cycle}}<6:1> $ can work as the reset signal in the lower block to recover the wrong switches due to the wrong bypass window size. For example, in Fig. 7, in the first sampling period, after the rising edge of $ W_{4}\_{\rm{flag}} $, the output of the comparator is locked in $ {\rm{Dp}}<1> $ and $ {\rm{Dn}}<1> $. At this moment, the window size is wrong. So the rising edge of $ {\rm{error}} $ set $ {\rm{cycle}}<1> $ to low, so $ {\rm{Dp}}<1> $ and $ {\rm{Dn}}<1> $ are reset directly. Therefore, these circuits do not need extra blocks to complete the recovery from the wrong switches in CDAC.

The NOC of the VCO-based comparator can be used to construct multiple bypass windows without additional references and comparators. The power reduction and static performances with multiple bypass windows are discussed in detail.

Fig. 9 shows two conversion periods of a 6-bit SAR ADC without and with different bypass windows, respectively. In Fig. 9(a), 6 SA cycles are needed in every conversion period for conventional SAR ADC no matter how much the input signal is. For the SAR ADC with a wide bypass window, shown in Fig. 9(b), the differential signal is likely located in the range of the bypass window. But the bypass logic can only bypass a few SA cycles, and hence the power efficiency improvement is limited. For the SAR ADC with a narrow bypass window, shown in Fig. 9(c), $ V_{\rm{dif}} $ has fewer opportunities to be detected within the bypass window. However, the bypass logic can bypass more numbers of SA cycles for the detected signal. The conversion process in Fig. 9(d) shows that the SAR ADC with multiple adaptive bypass windows will improve conversion efficiency extremely.

Figure  9.  Conversion processes of 6-b SAR ADCs. (a) Without bypass window. (b) Wide bypass window. (c) Narrow bypass window. (d) Multiple adaptive bypass windows.

For general signals with uniform input, Fig. 10 shows the number of SA cycles per sample of a 12-bit SAR ADC with different bypass windows. The voltage range of a single wide or narrow bypass windows is $ \pm 16 $ LSB or $ \pm 2 $ LSB, respectively. For the wide bypass window, the bypass logic can reduce the number of SA cycles within a large input signal range, which achieves 11.06 SA cycles per sample on average. For the narrow bypass window, though the bypass logic can be employed to deal with the smaller input signal range, it can reduce more SA cycles for the signal meeting the size of the bypass window (indicated by the red line in Fig. 10), leading to 11.69 SA cycles per sample on average.

Figure  10.  (Color online) SA cycles per sample. (a) Wide bypass window. (b) Narrow bypass window. (c) Multiple adaptive bypass windows.

For the SAR ADC with multiple adaptive bypass windows, this design uses three bypass windows. The simulation result shows that the SAR ADC with multiple adaptive bypass windows responds to large input signal range. Additionally, for small input voltage, the bypass logic can save more SA cycles. In other words, the SAR ADC with multiple adaptive bypass windows takes advantage of both the wide and narrow bypass windows. The size of the three bypass windows is initialized to 1 LSB, when the circuit starts to work. The window size has a correction process, and the three windows corresponding to NOC = 2, 3 and 4 will eventually stabilize on a certain size[17]. The convergence results are related to the design of the VCO comparator. In this design, the sizes of the three windows converge to $ \pm 16 $ LSB, $ \pm 4 $ LSB and $ \pm 2 $ LSB. And the SAR ADC with three bypass windows achieves 10.75 cycles per sample on average. The power consumption of the SAR ADC mainly consists of the power of DAC, comparator and control logic. Reducing the SA cycle can reduce the power of the DAC, comparator and control logic at the same time. There is a case worth mentioning: where the clock cycles should be beyond 12 when the size of bypass window is wrong. However, because the change of window size is mainly caused by PVT change, the correct bypass window can be used in subsequent ADC conversion, without the need to detect the wrong bypass window every cycle and waste power. Consequently, the SAR ADC with multiple adaptive bypass windows can save more power than that with a single bypass window.

When three bypass windows sizes are assumed as $ \pm 16 $ LSB, $ \pm 4 $ LSB and $ \pm 2 $ LSB respectively, and the probability density function of the output code is assumed as a uniform distribution, Fig. 11 shows the power consumption by switching with and without bypass logic. The average switching energy with bypass logic is 602.92 $ CV_{\rm{ref}}^{2} $, which is 11.62% lower than the switching energy without bypass logic (682.17 $ CV_{\rm{ref}}^{2} $). If there is only one bypass window used, the switching energy is 605.89, 654.89 and 666.63 $ CV_{\rm{ref}}^{2} $ for $ W_2 $, $ W_3 $, and $ W_4 $, respectively.

Figure  11.  Switching power consumption with/without bypass logic.

It is worth noting that the narrow window like W4 failing to decrease too much bit cycles and switching power comes as no surprise. This is because the input signal is assumed as uniform here and the power efficiency of bypass logic is tied to the characteristics of signals. For many biomedical signals concentrating on the adjacent of common-mode voltage, this shows small variations in magnitude can save much power with bypass logic[7, 31]. In contrast with the single bypass window of prior works, the technique of multiple adaptive bypass windows is more versatile for different characteristics of input signals.

The state of capacitors in a split capacitor array is illustrated in Fig. 12. When the control code is changed from $ 'X' $ to $ '1' $, $ C_{\rm{up}} $ is switched; when the control code is changed from $ 'X' $ to $ '0' $, $ C_{\rm{dn}} $ is switched. Considering the mismatch of capacitors, different error voltages are introduced into the system by $ C_{\rm{up}} $ and $ C_{\rm{dn}} $ if the control codes are different.

Figure  12.  The state of capacitors in split capacitor array.

The output voltage of the proposed SAR ADC is given by

V(S)=N1i=1(Cup_ibup_iCdn_ibdn_i)+C0bup_0CtotalVref, (9)
DNL=[Cdn_N1N2i=M+1Cup_i(Cup_M+Cdn_M)+(Cup_M1+Ccn_M1)M2i=i(Cup_i+Cdn_i)C0]VrefCtotal. (10)

If the control code of the DAC $ S $[$ i $] = 1, $ b_{{\rm{up}}\_i} $ = 1 and $ b_{{\rm{dn}}\_i} $ = 0; if $ S[i] $ = 0, $ b_{{\rm{up}}\_i} $ = 0 and $ b_{{\rm{dn}}\_i} $ = 1; if $ S[i] = X $, $ b_{{\rm{up}}\_i} $ = 0 and $ b_{{\rm{dn}}\_i} $ = 0. $ C_{{\rm{up}}\_i} $ and $ C_{{\rm{dn}}\_i} $ are the actual values (with mismatch errors) of the corresponding capacitors. $ C_0 $ is the unit capacitance. Since the mismatch errors of high-weighted capacitors influence the conversion results, much more greatly than that of the low-weighted capacitors, the maximum DNL occurs at the minimum code with the largest bypass window. Assuming the maximum bypass window $ W_2 = 5\; (\pm 16 $ LSB), the maximum DNL will occurs at $S =\; 'XXXXXX010000'$, which can be decoded into the standard binary code as Dout = $ '011111110000' $ by the state of capacitor array. The control code for Dout = $ '011111110000' - '1'$ is $S =\; '011111101111'$. So the voltage difference can be written as

DNL=V(XXXXXX010000)V(011111101111). (11)

Assuming $ \sigma _0 $ is the standard deviation of the random error of a unit capacitor, from Eqs. (9) and (11), the DNL can be written in LSB as $ \sqrt{1040}\sigma _0/C_0 $. If $ W_2 = M $ and the resolution is N-bit, Eq. (10) can be derived. So the maximum DNL can be calculated in LSB as

DNLmaxσ02N2+2M1C0. (12)

Fig. 13 illustrates the DNL performance of a conventional SAR ADC with split capacitor array and the proposed ADC with multiple adaptive bypass windows. The DNL curves are the root-mean-square (RMS) value of 10 000 simulations and each unit capacitor cell has a Gaussian random error with a standard deviation of 1%. The simulation shows the ADC with multiple adaptive bypass windows achieves a better DNL performance than the conventional one.

Figure  13.  (Color online) DNL performances of SAR ADC without bypass window and with multiple adaptive bypass windows.

The definition of INL at bin k is often defined as $ {\rm{INL}}(k) = V(k)-V_{\rm{ideal}}(k) $. However, in actual applications, $ V(0) $ is used as the starting point of INL to eliminate the error caused by offset. So the formula of INL is

INL(k)=V(k)V(0)Videal(k). (13)

If the minimum bypass window $W_4 = 2\, (\pm 2$ LSB), the control code at Dout = $ '011111111111' $ is S = $ 'XXXXXXXXX011' $. The INL at Dout = $ '011111111111' $ is

INL=V(XXXXXXXXX011)V(000000000000)Videal. (14)

So the INL at Dout = $ '011111111111' $ can be calculated in LSB as $ 32\sigma _0/C_0 $. Similarly, if the minimum bypass window $ W_4 = K $, the INL at Dout = $ '011111111111' $ is

INL=[N1i=K+1Cdn_i+K1i=1(Cup_i+Cdn_i)+C0]VrefCtotalVideal. (15)

Since $ C_{{\rm{up}}\_i} $ and $ C_{{\rm{dn}}\_i} $ are different in split capacitor array because of mismatch, Eq. (14) cannot be simplified. So the maximum INL can be calculated in LSB as

INLmaxσ02N2C0, (16)

which shows that the maximum INL is independent of the bypass window parameter K. The INL performance of the SAR ADC with multiple bypass windows (the standard deviation of the Gaussian error of the unit capacitor is 1%) is shown in Fig. 14, and it is the same with the INL performance of a conventional SAR ADC with the split capacitor array[29].

Figure  14.  INL performance of SAR ADC with multiple adaptive bypass windows.

In a high-resolution ADC with relatively high speed, variations on reference voltage lead to wrong decisions. The design avoids the large-area on-chip decoupling capacitor for stabilizing the reference by redundancy. The solution corrects the errors, and it is also favorable for the speed because the requirement for DAC settling is relaxed. Although the bypass logic offers redundancy since there are multiple output presentations for one identical input voltage[7], it is not enough for a 12-bit 30 M/s SAR ADC.

Compared with the binary-scaled error compensation redundancy[32], the split-and-recombination redundancy[19] does not need extra compensation capacitors and the sampling capacitance and input range remains unchanged. The main idea of split-and-recombination redundancy is to split MSB into two groups and make the smaller group recombine with LSB capacitors. The most critical point is that each capacitor is not larger than the sum of capacitors smaller than it so that multiple output codes are assigned to one same input signal. A split-and-recombination method (1-bit) shown in Fig. 15 is chosen under the consideration of speed. For designing the digital error correction circuit, it is necessary to derive the expression of Dout first.

Figure  15.  Split-and-recombination method.

If the bypass logic is not applied, the Dout can be written as Fig. 16. And Dout also can be expressed as Fig. 17. The digital error correction logic can be designed according to this expression similar to the implementation in Ref. [19].

Figure  16.  Expression of Dout without bypass logic.
Figure  17.  Expression of Dout without bypass logic.

The proposed bypass logic requires us to know the weights of the bypassed cycles. For example, it needs to search four times without bypass logic for $ V_{\rm{in}} = 8 $ as shown in Fig. 18. The weight of every bit is 8, 4, 2 and 1, respectively. So the output is obtained by $8\times 1+4\times 0+2\times0+ 1\times 0 = 8 $. For $ V_{\rm{in}} = 8 $ with bypass logic, the first and second cycles are bypassed. So $ V_{\rm{in}} $ must be located in areas I and II. The third and fourth comparison results are 1 and 0, respectively. So the output is $ XX10 $ ($ X $ stands for the bit bypassed). In this way, the output can be expressed as $ 4\times 1+2\times 1+2\times 1+1\times 0 = 8 $.

Figure  18.  (Color online) Binary search with and without bypass logic.

In short, bypassing one bit requires the addition of half weight of this bit to the output regardless of binary or non-binary weight. In accordance with this general conclusion for bypass logic, the Dout can be expressed as shown in Fig. 19 and red $ b_n $ represents the nth bypassed cycle. According to the expression of Dout, digital error correction as shown in Fig. 20 rather than ROM[33] or off-chip correction can be implemented by full adders, DFFs and XORs.

Figure  19.  Expression of Dout with bypass logic.
Figure  20.  Part of implementation of digital error correction logic.

Adding the redundancy decreases weights of LSBs as well, e.g., the weights of $ C_6 $ and $ C_5 $ change from 16 and 8 to 10 and 6. Because the window sizes are updated along with capacitors, smaller weights of LSBs refine the step size of the update, which makes the bypass logic more power-efficient.

The proposed 12-bit SAR ADC is designed in 40 nm CMOS technology. Fig. 21 shows the FFT plot of the ADC output at transistor-level simulation with a pad model. At a sampling rate of 30 MS/s, the ADC achieves an ENOB of 11.12-bit with 14.30 MHz input. The SNDR and SFDR are 68.72 and 85.35 dB, respectively. Fig. 22 shows the stable SNDR and SFDR versus different input frequency.

Figure  21.  (Color online) FFT plot with Nyquist input at 30 MS/s.
Figure  22.  Dynamic performance versus input frequency.

The total power consumption at Nyquist frequency is 380 $ \mu $W. It can be broken down as shown in Fig. 23: 63% from capacitor switching and DAC buffers; 26% from digital logic; 9% from comparator and 2% from bootstrapped switches. According to the Walden FoM equation

Figure  23.  (Color online) Power breakdown at Nyquist frequency.
FoM=Power2ENOB×fs, (17)

the resultant FoM of the ADC is 5.69 fJ/conversion-step. If the bypass logic is shut down, the total power consumption increases 12.4% to 427 $ \mu $W.

Table 1 summarizes the simulated performance with a comparison to state-of-the-art SAR ADCs with time-domain comparators. This design achieves a competitive position, suggesting that the performance of SAR ADCs assisted with NOC of the VCO-based comparator can be significantly enhanced with the proposed techniques.

Table  1.  Performance comparison of SAR ADCS with time-domain comparators.
Parameter JSSC 2011[10] TCAS-I 2013[33] JSSC 2014[34] ESSCIRC 2014[12] JSSC 2016[24] JSSC 2017[11] JSSC 2019[17] This Work
Technology (nm) 180 130 180 65 90 65 40 40
Comparator type VCDL VCDL VCDL hybrid VCO TDC hybrid Edge-pursuit VCO VCO
Calibration No Yes No Yes Yes Yes No No
Supply voltage (V) 0.6 0.5 0.6 0.85 0.7 N/A 1.1 1.1
Conversion rate (MS/s) 0.1 0.01 0.1 1.024 4 0.02 10 30
Resolution (bit) 10 11 10 13 10 15 10 12
SFDR (dB) 64 78 64.2 85.2 71.5 95.1 68.84 85.35
SNDR (dB) 57.5 61.6 56.5 66.4 54.8 74.12 58.57 68.72
ENOB (bit) 9.3 9.93 9.2 10.4 8.81 12.02 9.44 11.12
Powe ($\mu$W) 1.3 0.73 0.39 45.2 9.25 1.17 47.6 380
FoM
(fJ/Conv.-step)
21 74.8 6.7 33 5.16 14.06 6.85 5.69
DownLoad: CSV  | Show Table

This paper proposes a technique to set multiple adaptive bypass windows by using the number of oscillation cycles (NOC) of the VCO-based comparator, which is applied in a 30 MS/s 12-bit SAR ADC. The decrease of bit cycles, power consumption and improvement of the static performance with multiple adaptive bypass windows are analyzed in detail respectively. Enabling multiple adaptive bypass windows saves power by 12.4%. Besides, a 1-bit split-and-recombination redundancy and a general digital error correction method in bypass logic for correcting settling errors are proposed. The redundancy contributes to the overall speed and refines bypass windows as well. The proposed ADC achieves an ENOB of 11.12-bit and 85.35 SFDR at transistor level simulation, achieving a FoM of 5.69 fJ/conversion-step at 1.1 V supply with Nyquist input.

This work was supported by the National Natural Science Foundation of China under Grant 61534002 and Grant 61761136015.



[1]
Zhu Y, Chan C, Chio U, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE J Solid-State Circuits, 2010, 45(6), 1111 doi: 10.1109/JSSC.2010.2048498
[2]
Lin J, Hsieh C. A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS. IEEE Trans Circuits Syst I, 2015, 62(1), 70 doi: 10.1109/TCSI.2014.2349571
[3]
Sun L, Li B, Wong A K Y, et al. A charge recycling SAR ADC with a LSB-down switching scheme. IEEE Trans Circuits Syst I, 2015, 62(2), 356 doi: 10.1109/TCSI.2014.2363517
[4]
Lin J, Hsieh C. A 0.3 V 10-bit SAR ADC with first 2-bit guess in 90-nm CMOS. IEEE Trans Circuits Syst I, 2017, 64(3), 562 doi: 10.1109/TCSI.2016.2613505
[5]
Pang W, Wang C, Chang Y, et al. A 10-bit 500-kS/s low power SAR ADC with splitting comparator for bio-medical applications. 2009 IEEE Asian Solid-State Circuits Conference, 2009, 149
[6]
Zhu Z, Liang Y. A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-μm CMOS for medical implant devices. IEEE Trans Circuits Syst I, 2015, 62(9), 2167 doi: 10.1109/TCSI.2015.2451812
[7]
Huang G, Chang S, Liu C, et al. A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications. IEEE J Solid-State Circuits, 2012, 47(11), 2783 doi: 10.1109/JSSC.2012.2217635
[8]
Nuzzo P, De Bernardinis F, Terreni P, et al. Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Trans Circuits Syst I, 2008, 55(6), 1441 doi: 10.1109/TCSI.2008.917991
[9]
Agnes A, Bonizzoni E, Malcovati P, et al. A 9.4-ENOB 1 V 3.8-µW 100 kS/s SAR ADC with time-domain comparator. 2008 IEEE International Solid-State Circuits Conference, 2018, 246
[10]
Lee S, Park S, Park H, et al. A 21 fJ/conversion-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface. IEEE J Solid-State Circuits, 2011, 46(3), 651 doi: 10.1109/JSSC.2010.2102590
[11]
Shim M, Jeong S, Myers P D, et al. Edge-pursuit comparator: An energy-scalable oscillator collapse-based comparator with application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC. IEEE J Solid-State Circuits, 2017, 52(4), 1077 doi: 10.1109/JSSC.2016.2631299
[12]
Yoshioka K, Ishikuro H. A 13b SAR ADC with eye-opening VCO based comparator. ESSCIRC 2014: 40th European Solid State Circuits Conference (ESSCIRC), 2014, 411
[13]
Kao C, Hsieh S, Hsieh C. A 0.5 V 12-bit AR ADC using adaptive timedomain comparator with noise optimization. 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2017, 213
[14]
Harpe P, Cantatore E, van Roermund A. A 10b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10.1b ENOB at 2.2 fJ/conversion-step. IEEE J Solid-State Circuits, 2013, 48(12), 3011 doi: 10.1109/JSSC.2013.2278471
[15]
Ahmadi M, Namgoong W. A 3.3fJ/conversion-step 250 kS/s 10b SAR ADC using optimized vote allocation. Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013, 1
[16]
Chen L, Tang X, Sanyal A, et al. A 0.7-V 0.6-μW 100-kS/s low-power SAR ADC with statistical estimation-based noise reduction. IEEE J Solid-State Circuits, 2017, 52(5), 1388 doi: 10.1109/JSSC.2017.2656138
[17]
Ding Z, Zhou X, Li Q. A 0.5–1.1-V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator. IEEE J Solid-State Circuits, 2019, 54(4), 968 doi: 10.1109/JSSC.2018.2885554
[18]
Chang S, Zhou X, Ding Z, et al. A 12-bit 30 MS/s SAR ADC with VCO-based comparator and split-and-recombination redundancy for bypass logic. 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, 1
[19]
Liu C, Kuo C, Lin Y. A 10 bit 320 MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20 nm CMOS. IEEE J Solid-State Circuits, 2015, 50(11), 2645 doi: 10.1109/JSSC.2015.2466475
[20]
Abo A M, Gray P R. A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter. 1998 Symposium on VLSI Circuits, 1998, 166
[21]
Kim J, Leibowitz B S, Ren J, et al. Simulation and analysis of random decision errors in clocked comparators. IEEE Trans Circuits Syst I, 2009, 56(8), 1844 doi: 10.1109/TCSI.2009.2028449
[22]
Abidi A A. Phase noise and jitter in CMOS ring oscillators. IEEE J Solid-State Circuits, 2006, 41(8), 1803 doi: 10.1109/JSSC.2006.876206
[23]
Tai H, Hu Y, Chen H, et al. 11.2 A 0.85fJ/conversion-step 10b 200 kS/s subranging SAR ADC in 40 nm CMOS. 2014 IEEE International Solid-State Circuits Conference, 2014, 196
[24]
Chen Y, Chang K, Hsieh C. A 2.02–5.16 fJ/conversion step 10 bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS. IEEE J Solid-State Circuits, 2016, 51(2), 357 doi: 10.1109/JSSC.2015.2492781
[25]
Chan C, Zhu Y, Ho I, et al. 16.4 a 5 mW 7b 2.4 GS/s 1-then-2b/cycle SAR ADC with background offset calibration. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, 282
[26]
Yoshioka K, Shikata A, Sekimoto R, et al. An 8 bit 0.35 –0.8 V 0.5–30 MS/s 2 bit/step SAR ADC with wide range threshold configuring comparator. 2012 Proceedings of the ESSCIRC (ESSCIRC), 2012, 381
[27]
Ragab K, Sun N. A 1.4 mW 8b 350 MS/s loop-unrolled SAR ADC with background offset calibration in 40 nm CMOS. ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, 417
[28]
Chang A H, Lee H, Boning D. A 12b 50 MS/s 2.1 mw SAR ADC with redundancy and digital background calibration. 2013 Proceedings of the ESSCIRC (ESSCIRC), 2013, 109
[29]
Ginsburg B P, Chandrakasan A P. 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC. IEEE J Solid-State Circuits, 2007, 42(4), 739 doi: 10.1109/JSSC.2007.892169
[30]
Liu C, Chang S, Huang G, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J Solid-State Circuits, 2010, 45(4), 731 doi: 10.1109/JSSC.2010.2042254
[31]
Wang T, Li H, Ma Z, et al. A bypass-switching SAR ADC with a dynamic proximity comparator for biomedical applications. IEEE J Solid-State Circuits, 2018, 53(6), 1743 doi: 10.1109/JSSC.2018.2819164
[32]
Liu C, Chang S, Huang G, et al. A 10b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation. 2010 IEEE International Solid-State Circuits Conference (ISSCC), 2010, 386
[33]
Um J, Kim Y, Song E, et al. A digital-domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits. IEEE Trans Circuits Syst I, 2013, 60(11), 2845 doi: 10.1109/TCSI.2013.2252475
[34]
Jin J, Gao Y, Sánchez-Sinencio E. An energy-efficient time-domain asynchronous 2 b/step SAR ADC with a hybrid r-2r/c-3c DAC structure. IEEE J Solid-State Circuits, 2014, 49(6), 1383 doi: 10.1109/JSSC.2014.2317139
Fig. 1.  Conversion process of 6-bit SAR ADC. (a) Conventional SAR ADC. (b) SAR ADC with bypass window.

Fig. 2.  Architecture of the proposed SAR ADC.

Fig. 3.  Window update logic. (a) Not cross zero. (b) Cross zero.

Fig. 4.  Schematic of two common delay cells.

Fig. 5.  Schematic of VCO-based comparator and phase detector.

Fig. 6.  Comparison of simulated result and Eq. (6) of the dead zone of PD.

Fig. 7.  Bit cycle control circuits. (a) Schematic. (b) Timing diagram.

Fig. 8.  CDAC driving circuits. (a) Blocks. (b) Schematic. (c) Timing diagram.

Fig. 9.  Conversion processes of 6-b SAR ADCs. (a) Without bypass window. (b) Wide bypass window. (c) Narrow bypass window. (d) Multiple adaptive bypass windows.

Fig. 10.  (Color online) SA cycles per sample. (a) Wide bypass window. (b) Narrow bypass window. (c) Multiple adaptive bypass windows.

Fig. 11.  Switching power consumption with/without bypass logic.

Fig. 12.  The state of capacitors in split capacitor array.

Fig. 13.  (Color online) DNL performances of SAR ADC without bypass window and with multiple adaptive bypass windows.

Fig. 14.  INL performance of SAR ADC with multiple adaptive bypass windows.

Fig. 15.  Split-and-recombination method.

Fig. 16.  Expression of Dout without bypass logic.

Fig. 17.  Expression of Dout without bypass logic.

Fig. 18.  (Color online) Binary search with and without bypass logic.

Fig. 19.  Expression of Dout with bypass logic.

Fig. 20.  Part of implementation of digital error correction logic.

Fig. 21.  (Color online) FFT plot with Nyquist input at 30 MS/s.

Fig. 22.  Dynamic performance versus input frequency.

Fig. 23.  (Color online) Power breakdown at Nyquist frequency.

Table 1.   Performance comparison of SAR ADCS with time-domain comparators.

Parameter JSSC 2011[10] TCAS-I 2013[33] JSSC 2014[34] ESSCIRC 2014[12] JSSC 2016[24] JSSC 2017[11] JSSC 2019[17] This Work
Technology (nm) 180 130 180 65 90 65 40 40
Comparator type VCDL VCDL VCDL hybrid VCO TDC hybrid Edge-pursuit VCO VCO
Calibration No Yes No Yes Yes Yes No No
Supply voltage (V) 0.6 0.5 0.6 0.85 0.7 N/A 1.1 1.1
Conversion rate (MS/s) 0.1 0.01 0.1 1.024 4 0.02 10 30
Resolution (bit) 10 11 10 13 10 15 10 12
SFDR (dB) 64 78 64.2 85.2 71.5 95.1 68.84 85.35
SNDR (dB) 57.5 61.6 56.5 66.4 54.8 74.12 58.57 68.72
ENOB (bit) 9.3 9.93 9.2 10.4 8.81 12.02 9.44 11.12
Powe ($\mu$W) 1.3 0.73 0.39 45.2 9.25 1.17 47.6 380
FoM
(fJ/Conv.-step)
21 74.8 6.7 33 5.16 14.06 6.85 5.69
DownLoad: CSV
[1]
Zhu Y, Chan C, Chio U, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE J Solid-State Circuits, 2010, 45(6), 1111 doi: 10.1109/JSSC.2010.2048498
[2]
Lin J, Hsieh C. A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS. IEEE Trans Circuits Syst I, 2015, 62(1), 70 doi: 10.1109/TCSI.2014.2349571
[3]
Sun L, Li B, Wong A K Y, et al. A charge recycling SAR ADC with a LSB-down switching scheme. IEEE Trans Circuits Syst I, 2015, 62(2), 356 doi: 10.1109/TCSI.2014.2363517
[4]
Lin J, Hsieh C. A 0.3 V 10-bit SAR ADC with first 2-bit guess in 90-nm CMOS. IEEE Trans Circuits Syst I, 2017, 64(3), 562 doi: 10.1109/TCSI.2016.2613505
[5]
Pang W, Wang C, Chang Y, et al. A 10-bit 500-kS/s low power SAR ADC with splitting comparator for bio-medical applications. 2009 IEEE Asian Solid-State Circuits Conference, 2009, 149
[6]
Zhu Z, Liang Y. A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-μm CMOS for medical implant devices. IEEE Trans Circuits Syst I, 2015, 62(9), 2167 doi: 10.1109/TCSI.2015.2451812
[7]
Huang G, Chang S, Liu C, et al. A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications. IEEE J Solid-State Circuits, 2012, 47(11), 2783 doi: 10.1109/JSSC.2012.2217635
[8]
Nuzzo P, De Bernardinis F, Terreni P, et al. Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Trans Circuits Syst I, 2008, 55(6), 1441 doi: 10.1109/TCSI.2008.917991
[9]
Agnes A, Bonizzoni E, Malcovati P, et al. A 9.4-ENOB 1 V 3.8-µW 100 kS/s SAR ADC with time-domain comparator. 2008 IEEE International Solid-State Circuits Conference, 2018, 246
[10]
Lee S, Park S, Park H, et al. A 21 fJ/conversion-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface. IEEE J Solid-State Circuits, 2011, 46(3), 651 doi: 10.1109/JSSC.2010.2102590
[11]
Shim M, Jeong S, Myers P D, et al. Edge-pursuit comparator: An energy-scalable oscillator collapse-based comparator with application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC. IEEE J Solid-State Circuits, 2017, 52(4), 1077 doi: 10.1109/JSSC.2016.2631299
[12]
Yoshioka K, Ishikuro H. A 13b SAR ADC with eye-opening VCO based comparator. ESSCIRC 2014: 40th European Solid State Circuits Conference (ESSCIRC), 2014, 411
[13]
Kao C, Hsieh S, Hsieh C. A 0.5 V 12-bit AR ADC using adaptive timedomain comparator with noise optimization. 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2017, 213
[14]
Harpe P, Cantatore E, van Roermund A. A 10b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10.1b ENOB at 2.2 fJ/conversion-step. IEEE J Solid-State Circuits, 2013, 48(12), 3011 doi: 10.1109/JSSC.2013.2278471
[15]
Ahmadi M, Namgoong W. A 3.3fJ/conversion-step 250 kS/s 10b SAR ADC using optimized vote allocation. Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013, 1
[16]
Chen L, Tang X, Sanyal A, et al. A 0.7-V 0.6-μW 100-kS/s low-power SAR ADC with statistical estimation-based noise reduction. IEEE J Solid-State Circuits, 2017, 52(5), 1388 doi: 10.1109/JSSC.2017.2656138
[17]
Ding Z, Zhou X, Li Q. A 0.5–1.1-V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator. IEEE J Solid-State Circuits, 2019, 54(4), 968 doi: 10.1109/JSSC.2018.2885554
[18]
Chang S, Zhou X, Ding Z, et al. A 12-bit 30 MS/s SAR ADC with VCO-based comparator and split-and-recombination redundancy for bypass logic. 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, 1
[19]
Liu C, Kuo C, Lin Y. A 10 bit 320 MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20 nm CMOS. IEEE J Solid-State Circuits, 2015, 50(11), 2645 doi: 10.1109/JSSC.2015.2466475
[20]
Abo A M, Gray P R. A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter. 1998 Symposium on VLSI Circuits, 1998, 166
[21]
Kim J, Leibowitz B S, Ren J, et al. Simulation and analysis of random decision errors in clocked comparators. IEEE Trans Circuits Syst I, 2009, 56(8), 1844 doi: 10.1109/TCSI.2009.2028449
[22]
Abidi A A. Phase noise and jitter in CMOS ring oscillators. IEEE J Solid-State Circuits, 2006, 41(8), 1803 doi: 10.1109/JSSC.2006.876206
[23]
Tai H, Hu Y, Chen H, et al. 11.2 A 0.85fJ/conversion-step 10b 200 kS/s subranging SAR ADC in 40 nm CMOS. 2014 IEEE International Solid-State Circuits Conference, 2014, 196
[24]
Chen Y, Chang K, Hsieh C. A 2.02–5.16 fJ/conversion step 10 bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS. IEEE J Solid-State Circuits, 2016, 51(2), 357 doi: 10.1109/JSSC.2015.2492781
[25]
Chan C, Zhu Y, Ho I, et al. 16.4 a 5 mW 7b 2.4 GS/s 1-then-2b/cycle SAR ADC with background offset calibration. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, 282
[26]
Yoshioka K, Shikata A, Sekimoto R, et al. An 8 bit 0.35 –0.8 V 0.5–30 MS/s 2 bit/step SAR ADC with wide range threshold configuring comparator. 2012 Proceedings of the ESSCIRC (ESSCIRC), 2012, 381
[27]
Ragab K, Sun N. A 1.4 mW 8b 350 MS/s loop-unrolled SAR ADC with background offset calibration in 40 nm CMOS. ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, 417
[28]
Chang A H, Lee H, Boning D. A 12b 50 MS/s 2.1 mw SAR ADC with redundancy and digital background calibration. 2013 Proceedings of the ESSCIRC (ESSCIRC), 2013, 109
[29]
Ginsburg B P, Chandrakasan A P. 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC. IEEE J Solid-State Circuits, 2007, 42(4), 739 doi: 10.1109/JSSC.2007.892169
[30]
Liu C, Chang S, Huang G, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J Solid-State Circuits, 2010, 45(4), 731 doi: 10.1109/JSSC.2010.2042254
[31]
Wang T, Li H, Ma Z, et al. A bypass-switching SAR ADC with a dynamic proximity comparator for biomedical applications. IEEE J Solid-State Circuits, 2018, 53(6), 1743 doi: 10.1109/JSSC.2018.2819164
[32]
Liu C, Chang S, Huang G, et al. A 10b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation. 2010 IEEE International Solid-State Circuits Conference (ISSCC), 2010, 386
[33]
Um J, Kim Y, Song E, et al. A digital-domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits. IEEE Trans Circuits Syst I, 2013, 60(11), 2845 doi: 10.1109/TCSI.2013.2252475
[34]
Jin J, Gao Y, Sánchez-Sinencio E. An energy-efficient time-domain asynchronous 2 b/step SAR ADC with a hybrid r-2r/c-3c DAC structure. IEEE J Solid-State Circuits, 2014, 49(6), 1383 doi: 10.1109/JSSC.2014.2317139
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2. Sridevi, G.M., Ashoka, D.V., Ajay Prakash, B.V. Partial Pseudo-Random Hashing for Transactional Memory Read/Write Data Processing and Validation. Karbala International Journal of Modern Science, 2022, 8(2): 196-205. doi:10.33640/2405-609X.3223
3. Yoshioka, K.. VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29(12): 2143-2152. doi:10.1109/TVLSI.2021.3119691
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    Xiangxin Pan, Xiong Zhou, Sheng Chang, Zhaoming Ding, Qiang Li. A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows[J]. Journal of Semiconductors, 2020, 41(11): 112401. doi: 10.1088/1674-4926/41/11/112401
    X X Pan, X Zhou, S Chang, Z M Ding, Q Li, A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows[J]. J. Semicond., 2020, 41(11): 112401. doi: 10.1088/1674-4926/41/11/112401.
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    Received: 22 June 2020 Revised: 15 July 2020 Online: Accepted Manuscript: 18 September 2020Uncorrected proof: 24 September 2020Published: 03 November 2020

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      Xiangxin Pan, Xiong Zhou, Sheng Chang, Zhaoming Ding, Qiang Li. A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows[J]. Journal of Semiconductors, 2020, 41(11): 112401. doi: 10.1088/1674-4926/41/11/112401 ****X X Pan, X Zhou, S Chang, Z M Ding, Q Li, A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows[J]. J. Semicond., 2020, 41(11): 112401. doi: 10.1088/1674-4926/41/11/112401.
      Citation:
      Xiangxin Pan, Xiong Zhou, Sheng Chang, Zhaoming Ding, Qiang Li. A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows[J]. Journal of Semiconductors, 2020, 41(11): 112401. doi: 10.1088/1674-4926/41/11/112401 ****
      X X Pan, X Zhou, S Chang, Z M Ding, Q Li, A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows[J]. J. Semicond., 2020, 41(11): 112401. doi: 10.1088/1674-4926/41/11/112401.

      A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

      DOI: 10.1088/1674-4926/41/11/112401
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      • Corresponding author: Qiang Li, qli@uestc.edu.cn
      • Received Date: 2020-06-22
      • Revised Date: 2020-07-15
      • Published Date: 2020-11-10

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