Fig. 1.
(Color online) the structure of NC-FinFET.
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Yaqian Qian, Shushan Qiao, Rongqiang Yang. Variation tolerance for high-speed negative capacitance FinFET SRAM bit cell[J]. Journal of Semiconductors, 2020, 41(6): 062403. doi: 10.1088/1674-4926/41/6/062403
Y Q Qian, S S Qiao, R Q Yang, Variation tolerance for high-speed negative capacitance FinFET SRAM bit cell[J]. J. Semicond., 2020, 41(6): 062403. doi: 10.1088/1674-4926/41/6/062403.
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Variation tolerance for high-speed negative capacitance FinFET SRAM bit cell
doi: 10.1088/1674-4926/41/6/062403
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Abstract
Negative capacitance FinFET (NC-FinFET) has a promising developmental prospect due to its superior performance in SS < 60 mV/dec (subthreshold swing), especially in SRAM. Noise margin is an important metric to evaluate the performance for SRAM, together with static leakage, read speed, etc. In this paper, we study the effects of the variation of ferroelectric material (thickness, polarization), FinFET critical physical parameters (fin number, channel length) and some ambient factors (working temperature, supply voltage) on the performance of NC-FinFET SRAM within the reasonable fluctuation tolerance range. The SRAM bit cell is analyzed with a basic 6T structure. The impact of fin number and channel length for NC-FinFET SRAM is different from that of conventional FinFETs. Additionally, the ferroelectric material and some other factors are assessed in detail. -
References
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