Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

Xu Yong , Wang Zhigong , Qiu Yinghua , Li Zhiqun , Hu Qingsheng and and Min Rui

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Key words: PLL, frequency synthesizer, dual-modulus prescaler, programmable & pulse swallow divider

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Received: 18 August 2015 Revised: Online: Published: 01 September 2005

Article Navigation > Journal of Semiconductors > 2005 > 26(9): 1711-1715

Xu Yong, Wang Zhigong, Qiu Yinghua, Li Zhiqun, Hu Qingsheng, and Min Rui. Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer[J]. 半导体学报(英文版), 2005, 26(9): 1711-1715.

Citation:

Xu Yong, Wang Zhigong, Qiu Yinghua, Li Zhiqun, Hu Qingsheng, and Min Rui. Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer[J]. 半导体学报(英文版), 2005, 26(9): 1711-1715.

Xu Yong, Wang Zhigong, Qiu Yinghua, Li Zhiqun, Hu Qingsheng, and Min Rui. Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer[J]. 半导体学报(英文版), 2005, 26(9): 1711-1715.

Citation:

Xu Yong, Wang Zhigong, Qiu Yinghua, Li Zhiqun, Hu Qingsheng, and Min Rui. Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer[J]. 半导体学报(英文版), 2005, 26(9): 1711-1715.

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