Abstract: Based on the 65nm CMOS process,a novel parallel RLC coupling interconnect analytical model is presented synthetically considering parasitical capacitive and parasitical inductive effects.Applying function approximation and model order-reduction to the model,we derive a closed-form and time-domain waveform for the far-end crosstalk of a victim line under ramp input transition.For various interconnect coupling sizes,the proposed RLC coupling analytical model enables the estimation of the crosstalk voltage within 2.50% error compared with Hspice simulation in a 65nm CMOS process.This model can be used in computer-aided-design of nanometer SOCs.

Key words: nanometer CMOS, interconnect coupling crosstalk, parallel RLC analytical model, parameter extraction, function approximation