The field-effect transistor is inherently bipolar,having simultaneously electron and hole surface and volume channels and currents. The channels and currents are controlled by one or more externally applied transverse electric fields. It has been known as the unipolar field-effect transistor for 55-years since Shockley’s 1952 invention,because the electron-current theory inevitably neglected the hole current from over-specified internal and boundary conditions,such as the electrical neutrality and the constant hole-electrochemical-potential,resulting in erroneous solutions of the internal and terminal electrical characteristics from the electron channel current alone,which are in gross error when the neglected hole current becomes comparable to the electron current,both in subthreshold and strong inversion. This report presents the general theory,that includes both electron and hole channels and currents.The rectangular (x,y,z) parallelepiped transistors,uniform in the width direction (z-axis),with one or two MOS gates on thin and thick,and pure and impure base,are used to illustrate the two-dimensional effects and the correct internal and boundary conditions for the electric and the electron and hole electrochemical potentials. Complete analytical equations of the DC current-voltage characteristics of four common MOS transistor structures are derived without over-specification: the 1-gate on semi-infinite-thick impure-base (the traditional bulk transistor),the 1-gate on thin impure-silicon layer over oxide-insulated silicon bulk (SOI),the 1-gate on thin impure-silicon layer deposited on insulating glass (SOI TFT),and the 2-gates on thin pure-base (FinFETs).
Effects of in situ annealing on the structural and optical properties of Gallium nitride (GaN) layers grown on (0001) sapphire by hydride vapor phase epitaxy (HVPE) are studied.The properties of GaN epilayers are improved by in-situ annealing at growth temperature under ammonia (NH3) atmosphere.X-ray diffraction (XRD) analysis shows that the full width at half maximum (FWHM) of the rocking curves narrows as the annealing time increases.Raman scattering spectroscopy shows that E2(high) peak positions shift to the low frequency region.Compared to without annealing and epilayers annealed with bulk GaN,the E2(high) peak position of epilayers becomes closer to that of bulk GaN as the in situ annealing time increases.The biaxial compressive stress decreases after in situ annealing.Photoluminescence (PL) examination agrees well with XRD and Raman scattering analyses.These results suggest that the optical and structural properties of GaN epilayers can be improved by in situannealing.
Polyimide passivation and planarization process techniques for high speed InP/InGaAs single heterojunction bipolar transistors (SHBTS) are developed.A maximum extrapolated ft of 210GHz is achieved for the SHBT with 1.4μm×15μm emitter area at VCE=1.1V and IC=335mA.This device is suitable for high speed and low power applications,such as ultra high speed mixed signal circuits and optoelectronic communication ICs.
To investigate effective means of improving the efficiency of organic light-emitting devices (OLEDs) by making full use of triplet emission,a phosphorescent material Pt (II) Octaethylporphine (PtOEP) is doped into polymer host polyspirobifluorene (Spiro) to allow radiative recombination of triplet excitons.The current and brightness characteristics of the devices are tested and the electroluminescent spectra are described.Both fluorescence and phosphorescence are observed,and an obvious increase in external quantum efficiency is realized compared to undoped devices when different phosphorescent dopant concentrations are tried.Thus,the phosphorescent emission from triplet excited states might be an effective way to increase the efficiency of OLEDs when the concentration of the phosphorescent dopant is properly controlled.
Based on the 65nm CMOS process,a novel parallel RLC coupling interconnect analytical model is presented synthetically considering parasitical capacitive and parasitical inductive effects.Applying function approximation and model order-reduction to the model,we derive a closed-form and time-domain waveform for the far-end crosstalk of a victim line under ramp input transition.For various interconnect coupling sizes,the proposed RLC coupling analytical model enables the estimation of the crosstalk voltage within 2.50% error compared with Hspice simulation in a 65nm CMOS process.This model can be used in computer-aided-design of nanometer SOCs.
A novel capacitive pressure sensor is presented,whose sensing structure is a solid-state capacitor consisting of three square membranes with Al/SiO2/n-type silicon.It was fabricated using pn junction self-stop etching combined with adhesive bonding,and only three masks were used during the process.Sensors with side lengths of 1000,1200,and 1400μm were fabricated,showing sensitivity of 1.8,2.3,and 3.6fF/hPa over the range of 410~1010hPa,respectively.The sensitivity of the sensor with a side length of 1500μm is 4.6fF/hPa,the nonlinearity is 6.4%,and the max hysteresis is 3.6%.The results show that permittivity change plays an important part in the capacitance change.
This paper presents a low voltage,low power RF/analog front-end circuit for passive ultra high frequency (UHF) radio frequency identification (RFID) tags.Temperature compensation is achieved by a reference generator using sub-threshold techniques.The chip maintains a steady system clock in a temperature range from -40 to 100℃.Some novel building blocks are developed to save system power consumption,including a zero static current power-on reset circuit and a voltage regulator.The RF/analog front-end circuit is implemented with digital base-band and EEPROM to construct a whole tag chip in 0.18μm CMOS EEPROM technology without Schottcky diodes.Measured results show that the chip has a minimum supply voltage requirement of 0.75V.At this voltage,the total current consumption of the RF/analog front-end circuit is 4.6μA.
The influence of the electric field on the properties of the bound magnetopolaron in an infinite-depth GaAs semiconductor quantum well is investigated using the linear-combination operator and the unitary transformation method.The relationships between the polaron’s ground state energy and the Coulomb bound potential,electric field,magnetic field,and well-width are derived and discussed.Our numerical results show that the absolute value of the polaron’s ground state energy increases as the electric field and the Coulomb bound potential increase,and decreases as the well-width and the magnetic field strength increase.When the well-width is small,the quantum size effect is significant.
Based on an analysis of symmetry,the dispersion relations near the Δi valley in strained Si1-xGex(0≤x＜0.45)/(001),(111),(101)Si are derived using the KP method with perturbation theory.These relations demonstrate that Δi levels in strained Si1-xGex are different from the Δ1 level in relaxed Si1-xGex,while the longitudinal and transverse masses (m*l and m*t) are unchanged under strain.The energy shift between the Δi levels and the Δ1 level follows the linear deformation potential theory.Finally,a description of the conduction band (CB) edge in biaxially strained layers is given.
A gate-all-around cylindrical (GAAC) transistor for sub-10nm scaling is proposed.The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time.Among all other novel FinFET devices,the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability.According to our simulation,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET,including gate-all-around rectangular (GAAR) devices.With gate-all-around cylindrical architecture,the transistor is controlled by an essentially infinite number of gates surrounding the entire cylinder-shaped channel.The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect.The proposed fabrication procedures for devices having GAAC device architecture are also discussed.The method is characterized by its simplicity and full compatibility with conventional planar CMOS technology.
We investigate the effects of the surface states on the Schottky contacts in 4H-SiC MESFET.The Ti/Pt/Au gate metal contacts are deposited by electron beam evaporation and patterned by a lift-off process.Based on thermionic theory,a simple parameter extraction method is developed for determination of the surface states in metal/4H-SiC Schottky contacts.The interface state density and interface capacitance are calculated to be 4.386e13cm-2·eV-1 and 6.394e-6F/cm2,which are consistent with the device’s terminal characteristics.
The reverse snapback phenomena (RSP) on I-V characteristics of static induction thyristors (SITH) are physically researched.The I-Vcurves of the power SITH exhibit reverse snapback phenomena,and even turn to the conducting-state,when the anode voltage in the forward blocking-state is increased to a critical value.The RSP I-Vcharacteristics of the power SITH are analyzed in terms of operating mechanism,double carrier injection effect,space charge effect,electron-hole plasma in the channel,and the variation in carrier lifetime.The reverse snapback mechanism is theoretically proposed and the mathematical expressions to calculate the voltage and current values at the snapback point are presented.The computing results are compared with the experiment values.
The implementation of broadband monolithic baluns based on CMOS technology is investigated.The configuration and parameterized layout are analyzed.Then,a wide-band lumped element equivalent circuit model accounting for all necessary physical effects is proposed and model parameters are extracted,with high accuracy in a broadband frequency range,via combination of physical formula and fitting optimization.Two baluns were implemented with TSMC’s one-poly eight-metal (1P8M) 0.13μm mixed-signal (MS)/RF CMOS process.The S-parameters of these two baluns were measured using a vector network analyzer.The measured results agree well with the modeled parameters up to millimeter-wave frequencies.
Peroxodiphosphate anion (a powerful oxidant) can be formed in a special water-based cleaning agent through an electrochemical reaction on boron-doped diamond electrodes.This electrochemical reaction was applied during the oxidation,decomposition,and removal of organic contaminations on a silicon wafer surface,and it was used as the first step in the diamond electrochemical cleaning technique (DECT).The cleaning effects of DECT were compared with the RCA cleaning technique,including the silicon surface chemical composition that was observed with X-ray photoelectron spectroscopy and the morphology observed with atomic force microscopy.The measurement results show that the silicon surface cleaned by DECT has slightly less organic residue and lower micro-roughness,so the new technique is more effective than the RCA cleaning technique.
A new process for gate dielectric fabrication named in situ steam generation (ISSG) is reported.Based on the Deal-Grove model,an oxidation mechanism is proposed to break the Si-Si bond by an active atomic O and form a Si-O-Si bond during the oxidation process.The breakdown characteristics are investigated through a MOS-capacitor for both ISSG and furnace wet oxidation.The gate dielectric material generated by ISSG oxidation has a superior electrical performance owing to sufficient oxidation of weak Si-Si bonds relative to furnace wet oxidation,indicating a promising application in sub-micron IC device manufacturing.
A monolithic 10GHz LC voltage-controlled oscillator (VCO) is implemented in standard 0.25μm CMOS technology.The VCO adopts an optimized symmetric circular inductor with center-tap,an accumulation-mode MOS (A-MOS) varactor in series with a passive metal-isolator-metal capacitor (MIM-CAP) and a tail current source with an LC filter to operate with high-frequency and low-noise resulting in -103.2dBc/Hz at 1MHz offset from carrier frequency of 10.2GHz and approximately 11.5% tuning range.With a 3.3V supply voltage,the core circuit consumes 9.9mW.The chip area is 0.67mm×0.58mm.
A new configuration for delay cells used in voltage controlled oscillators is presented.A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given.A new method to optimize loop parameters based on low-jitter in PLL is also introduced.A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process.The result shows that the RJ (random jitter) RMS of 1.25GHz data rate series output is 2.3ps (0.0015UI) and RJ (1 sigma) is 0.0035UI.A phase noise measurement shows -120dBc/Hz@100kHz at 1111100000 clock-pattern data out.
A 13bit,pipelined analog-to-digital converter (ADC) designed to achieve high linearity is described.The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error,a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity,and an anti-disturb design to reduce the noise from the digital supply.This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm2,including pads.Measured performance includes -0.18/0.15LSB of differential nonlinearity,-0.35/0.5LSB of integral nonlinearity,75.7dB of signal-to-noise plus distortion ratio (SNDR) and 90.5 dBc of spurious-free dynamic range (SFDR) for 2.4MHz input at 2.5MS/s.At full speed conversion (5MS/s) and for the same 2.4MHz input,the measured SNDR and SFDR are 73.7dB and 83.9 dBc,respectively.The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.
To improve the accuracy and speed in cycle-accurate power estimation,this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model.By analyzing the power distribution and internal node state,we find the deficiency of only using port information.Then,we define the gate level number computing method and the concept of slice,and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information.Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model,and maintain a 700+ speedup compared with the existing gate-level power analysis technique.
A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented.By substituting conventional multi-circle antenna with single-circle antenna,the package cost of the tag is greatly reduced.Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented.The circuit is implemented in an SMIC 0.18μm EEPROM process.Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%.For a sinusoidal wave with magnitude of 0.5V,the output DC voltage reaches 1V,which is high enough for RFID tags.The read distance is as far as 22cm.
This paper presents a novel impedance matching approach for passive UHF RFID transponder ICs,which are compatible with the ISO/IEC 18000-6B standard and operate in the 915MHz ISM band.The passive UHF RFID transponder with complex impedances is powered by received RF energy.The approach uses the parasitic inductance of the antenna to implement ASK modulation by adjusting the capacitive reactance of the matching network,which changes with the backscatter circuit.The impedance matching achieves maximum power transfer between the reader,antenna,and transponder.The transponder IC,whose operating distance is more than 4m with the impedance matching approach,is fabricated using a Chartered 0.35μm two-poly four-metal CMOS process that supports Schottky diodes and EEPROM.
We study the relationship between microstructure and luminescence efficiency for GaN heteroepitaxial films by cathodoluminescence (CL),transmission electron microscopy,and X-ray diffraction.Even though threading dislocations in GaN epitaxial layers have been demonstrated to be effective nonradiative recombination centers,the CL band edge peak intensity does not decrease as the dislocation density increases.The luminescence efficiency of GaN is found to be affected both by the grain size of the mosaic structural GaN formed by two-step growth and by the bend extent of dislocations formed during the coalescence of sub-grains.
Effect of hydrogenation on the luminescence properties of ZnO is investigated with low temperature photoluminescence (PL) spectrum.Hydrogen is incorporated into the ZnO crystals from a remote DC plasma.It is found that hydrogen incorporation influences the relative luminescence intensities of bound excitons,and,in particular,the intensity of I4 (3.363eV) is enhanced.Hydrogenated ZnO samples show a different temperature dependence on PL spectra from the virgin ZnO samples.PL spectra of the hydrogenated ZnO samples were measured at 4.2K from different depths below the surface.The intensity of I4 and the intensity ratio of I4 to I8 change with depth,indicating a direct connection between the incorporated hydrogen and the shallow donor.In general,hydrogenation enhances the band edge luminescence and passivates the green emission.
Square patterns with different sizes are prepared on c-sapphire by plasma-enhanced chemical vapor deposition of SiO2,conventional optical lithography,and wet chemical etching.The GaN film is selectively grown on this patterned c-sapphire by hydride vapor phase epitaxy.An optical microscope,atomic force microscope,scanning electron microscope,high resolution double crystal X-ray diffraction (DCXRD),and Raman shift spectrum are used to analyze the sample.The GaN layer with a thickness of about 20μm grown on an area of 100μm×100μm is crack-free while the GaN layers grown on areas of 300μm×300μm and 500μm×500μm have cracks.Thus,the full width at half maximum (FWHM) of DCXRD of (0002) reflection of GaN grown on the independent square window of c-sapphire decreases when the area of window decreases,indicating better quality GaN single crystal.The minimum FWHM is 530" .From the corner of the square window towards its edge and center,the in-plane compressive stress of GaN decreases due to the interaction between the epitaxial lateral overgrown GaN wings and the SiO2 mask underneath,and the bending of 90° of threading dislocations at the border of the window regions.
The longitudinal composition profiles of HgCdTe LPE films based on infrared transmission spectra are evaluated.The infrared transmission spectra are simulated theoretically using the composition profile model proposed by Wang Qingxue,taking the interference effect of the light during propagation in the composition gradient region of HgCdTe LPE films into consideration.A set of infrared transmission spectrum curves of the samples with the same growth number but different HgCdTe layer thicknesses are used to check the reliability of the calculation method.The results show that all the experimental curves can be fitted theoretically.Next,a method to determine the 4 simulation parameters (HgCdTe epilayer thickness,composition gradient region thickness,surface composition,and composition slope in the epilayer) used in theoretical calculation is discussed and the precisions of these parameters are determined.The results show that the theoretical simulation of the infrared transmission spectra is effective to evaluate the longitudinal composition profiles of the HgCdTe LPE films.
Transmission electron microscope (TEM) measurements performed on InGaN/GaN multiple-quantum-well (MQW) deposited Silicon substrates have been investigated.By taking high-resolution transmission electron microscopy (HRTEM) imagery,electron diffraction contrast imagery, and electron diffraction image in precincts between the Si substrate and the AlN buffer area,and also taking Two-beam electron diffract contrast imagery around the quantum well area,we have researched the characteristics of dislocation.In addition,we take the image of materials before and after saturated KOH solution’s cauterization by field emission scanning electric microscope(SEM).It is discovered that the AIN buffer layer is of porous structure,and that a great deal of incomplete dislocation parallel to the interface was found between the buffer layer and extension.The average density of dislocation reaches 1e8cm-2 in the high -temperature GaN layer,which is in accordance with the density of hexagonal etch pits by scanning electric microscope (SEM).Much dislocation below the quantum well was found to be so bent up to 90° that the dislocation density was reduced more through the quantum well.Moreover,edge dislocation accounts for the largest part among all the line dislocations,and mixed dislocation is second,but screw dislocation is hardly found in the observed area.Therefore,we conclude that the porous structure of low-temperature ALN buffer’s enables the extension layer to develop under the ELO model,which leads to a massive dislocation bend below the quantum well and then the density of the penetrating dislocation is reduced.
Site-controlled InAs quantum wires were fabricated with the cleaved edge overgrowth method.First,AlGaAs/GaAs superlattices were grown on GaAs substrate by molecular beam epitaxy.Then,the sample was taken out of the MBE system and cleaved along the ［110］ direction.After pretreatment,the (110) cleaved edges acted as a nanopattern in overgrowth.Experimental results demonstrate that the pretreatment on the cleaved edge affects the overgrowth and that selective etching is better than natural oxidation for site-controlled growth of quantum wires.High temperature degasification will induce pits on GaAs spacers,indicating that Ga atoms can easily escape from (110) cleaved edges.Furthermore,the surface diffusion length of Ga atoms on the (110) surface is long and the preferred diffusion direction of the atoms on (110) surface is toward ［001］.
N nc-Si/c-Si heterojunction solar cells were prepared with the hot-wire chemical vapor deposition technique.The dark I-V characteristics of the cells with different atomic hydrogen treatments on the c-Si surface were measured.At room temperature,the I-Vcurves were fitted by a two-diode model in which four different voltage regions were recognized:the shunt resistance (V＜0.15),nonideal diode (0.15＜V＜0.3V),ideal diode (0.3＜V＜0.5V),and series resistance (V＞0.5V) regions.The modeled results show that the ideality factor of the nonideal diode (n2) is decreased by a suitable atomic hydrogen treatment of 30s,indicating a lower recombination current and a better interface property.The dark I-V characteristics in the temperature range of 282~335K indicate that in the lower voltage range of 0.15~0.3V,the dark current mainly originates from the recombination current in the depletion region.In the 0.3~0.5V range,the tunneling process dominates in the transport mechanism,which can be described by an interfacial tunneling process through the interface states.
This paper reports two kinds of AlGaN/GaN HEMTs with the field plate gate.In contrast with a conventional HEMT structure,their DC characteristics are improved and the broken voltage is over 100V.The reverse leakage current of the Schottky gate is reduced from 0.037 to 0.0057mA with a 100V voltage between gate and drain using a field plate.Its broken voltage is increased from 78 to over 100V.The HEMTs with the gate field plate structure and the source field plate structure are compared and their high frequency characteristics are also discussed.
Based on an analytical threshold voltage model of fully depleted silicon-on-insulator (SOI) MOSFETs with asymmetric HALO structures,the impact of the two-dimension effects in a buried-oxide layer on threshold voltage is discussed.Compared to the 1D model,two-dimensional effects in the buried-oxide layer of the deep submicron MOSFET device create the short-channel effect more quickly.The predictions of the new model are in good agreement with those of the two-dimension numerical simulator MEDICI.
We transfer GaN based LED epitaxial materials grown on a Si substrate to a new Si substrate and fabricate flip blue LED chips.Photoelectric properties of these chips with different n-electrode etching depths are researched.An accelerated aging experiment on a testing board is studied under a high driven current of 500mA for the chips of 200μm×200μm before incised.The results show that the chips with 0.8 and 1.2μm etching depths have lower forward voltage and slower light decay than the chips with 0.5μm etching depth.Meanwhile,the ESD is relatively steadier with aging time.Additionally,the ESD of chips with 0.8μm etching depth is larger than the chips with 1.2μm.
Back-illuminated Al0.42Ga0.58N/Al0.40Ga0.60N heterojunction p-i-n solar-blind UV photodetectors grown on sapphire by metal organic chemical vapor deposition are fabricated.An ideality factor of n=3 and a series resistance of RS=93Ω are obtained from the forward current-voltage curve of the device.The external quantum efficiency and detectivity at a peak wavelength of 275nm at zero-bias voltage are 9% and 4.98e11cm·Hz1/2·W-1,respectively.Mere 15.7% of the spectral transmittance of the Al0.42Ga0.58N window layer at 275nm results in the low external quantum efficiency and detectivity.
Metal-semiconductor-metal (MSM) photodetector linear arrays of 40 pixels based on 4H-SiC,in which nickel Schottky contacts are used,are designed,fabricated,and characterized.Current-voltage and spectral responsivity measurements are carried out at room temperature.The linear arrays show uniform performances,including responsibility,breakdown voltage,and low leakage current.The breakdown voltage of the unit is beyond 100V.The detector shows a peak responsivity of about 0.09A/W,a dark current smaller than 5pA at 20V,and a displayed peak response wavelength at 290nm.The ratio of responsivity at 290nm to that of at 400nm is more than 5000,implying that the photodetector has an improved visible blind performance.
To eliminate the influence of the individual diversity of carbon nanotubes (CNTs) and poor contact between the CNTs and the substrate on the luminescence uniformity of the CNT field emission (FE) display cathode film,a reactive current limiting layer is introduced.The zinc oxide is screen printed on the substrate as a reactive current limiting layer and subsequently covered with the CNTs using the CVD method.The FE current stability and luminescence uniformity are tested and the influence of the reactive current limiting layer on the FE curve is studied.SEM images show that the ZnO layer not only eliminates the CNT tip shielding effect but also improves the contact between the CNTs and the substrate.FE curves and luminescence photos show that the threshold voltage increases as the thickness of the ZnO layer increases and as the FE current decreases.The current stability and luminescence uniformity are improved remarkably due to the ZnO layer.
Novel formulas to analyze the gain characteristics of Er3+/Yb3+ co-doped waveguide amplifiers (EYCDWA) are derived from the rate equations and the light propagation equations under the uniform dopant and steady-state conditions,neglecting the amplified spontaneous emission and introducing initial energy transfer efficiency.Using these formulas,the effects of the pumping power,signal power,dopant concentration,and waveguide length on the gain characteristics of the EYCDWA are analyzed.A comparison is performed between the EYCDWA and the singly erbium-doped optical waveguide amplifier and some useful results are obtained.
A novel configuration of an electromagnetically actuated MEMS optical scanning mirror with a large mirror area of 6mm×4mm is designed,fabricated,and characterized.This optical scanning mirror based on a silicon plate,in which a set of micro-coils for actuation are adhered to the back side of the mirror using the electroplating technique,is immersed in the magnetic field produced by the magnetic circuit,including a permanent magnet.The mirror rotates around one pair of torsion bars when the driving current signal is applied on the driving coils.This device,fabricated using silicon bulk processing and the electroplating technique,shows excellent performance.The slope of optical steering deflection of this device is 0.03°/mA,the optical deflection angle is 1e2. under a resonant frequency of 381Hz at a lower power consumption of ＜1mW,and theQfactor in air is 221.Additionally,the MEMS scanning mirror as a precise optics element presents good surface roughness of mirror and high reflectivity,so it can be applied in scanning systems such as high speed micro-spectrometers and optical tunable filters in optical communication.
Based on a low swing,low crossing point current switch driver and central symmetry Q2 random walk pMOS current source layout routing methods,a 1.8V 10bit 120MS/s CMOS current-steering digital-to-analog converter IP core is implemented in a TSMC 0.18μm CMOS process.With a supply of 1.8V,the integral and differential nonlinearity are measured to be less than 0.45LSB and 0.25LSB,respectively.When the output signal frequency is 24.225MHz at 120MHz sampling rate,the SFDR is measured to be 64.9dB.The die area is about 0.43mm×0.52mm.
An adaptive slope compensation circuit used in current mode DC-DC converters is presented.After analyzing the theory of slope compensation,a dynamic slope compensation is proposed,which uses a translinear loop circuit for the operation of compensation current signal without the additional output voltage pin,saving package and die size on the chip.This slope compensation circuit can minimize the negative impact to load capacity and the transient response of the system.The circuit is designed with UMC BCD technology.When the input is 2V and the output is 8V,the load capacity of the boost DC-DC converter is 300mA and the load regulation is 6.7mV/A.
Aiming at the problem of testing parametric fault in analog integrated circuits,an approach based on power spectrum correlation analysis for diagnosing parametric faults is presented.After wavelet filter-banks’ filtering,the coherence function of the sub-band response sequence is computed.Subsequently,correlation analysis is imposed upon the power spectrum described by the coherence function sequence.As a result,not only can extracting the digital signature of the parametric fault be completed,but also the location of the parametric fault can be found.By virtue of international benchmark circuits,state variable filter,and leapfrog filter,the effectiveness of this approach with respect to locating parametric faults is validated by comparison with that in Ref.［8］.This provides a novel way to realize high fault coverage and automation of diagnosing parametric faults in analog integrated circuits.
