Abstract: A 13bit,pipelined analog-to-digital converter (ADC) designed to achieve high linearity is described.The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error,a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity,and an anti-disturb design to reduce the noise from the digital supply.This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm2,including pads.Measured performance includes -0.18/0.15LSB of differential nonlinearity,-0.35/0.5LSB of integral nonlinearity,75.7dB of signal-to-noise plus distortion ratio (SNDR) and 90.5 dBc of spurious-free dynamic range (SFDR) for 2.4MHz input at 2.5MS/s.At full speed conversion (5MS/s) and for the same 2.4MHz input,the measured SNDR and SFDR are 73.7dB and 83.9 dBc,respectively.The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.

Key words: analog-to-digital converter, high linearity, capacitor error-averaging, gain-boosting,  bootstrapping switch, anti-disturb