J. Semicond. > 2008, Volume 29 > Issue 3 > 447-457

PAPERS

Simulation of Gate-All-Around Cylindrical Transistors for Sub-10 Nanometer Scaling

Xiao Deyuan, Xie Joseph, Chi Minhwa, Wang Xi and Yu Yuehui

+ Author Affiliations

PDF

Abstract: A gate-all-around cylindrical (GAAC) transistor for sub-10nm scaling is proposed.The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time.Among all other novel FinFET devices,the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability.According to our simulation,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET,including gate-all-around rectangular (GAAR) devices.With gate-all-around cylindrical architecture,the transistor is controlled by an essentially infinite number of gates surrounding the entire cylinder-shaped channel.The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect.The proposed fabrication procedures for devices having GAAC device architecture are also discussed.The method is characterized by its simplicity and full compatibility with conventional planar CMOS technology.

Key words: gate-all-around cylindrical transistordevice physicsTCAD simulationfabrication procedure

  • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 3676 Times PDF downloads: 1182 Times Cited by: 0 Times

    History

    Received: 18 August 2015 Revised: 06 November 2007 Online: Published: 01 March 2008

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Xiao Deyuan, Xie Joseph, Chi Minhwa, Wang Xi, Yu Yuehui. Simulation of Gate-All-Around Cylindrical Transistors for Sub-10 Nanometer Scaling[J]. Journal of Semiconductors, 2008, 29(3): 447-457. ****Xiao D Y, Xie J, Chi M, Wang X, Yu Y H. Simulation of Gate-All-Around Cylindrical Transistors for Sub-10 Nanometer Scaling[J]. J. Semicond., 2008, 29(3): 447.
      Citation:
      Xiao Deyuan, Xie Joseph, Chi Minhwa, Wang Xi, Yu Yuehui. Simulation of Gate-All-Around Cylindrical Transistors for Sub-10 Nanometer Scaling[J]. Journal of Semiconductors, 2008, 29(3): 447-457. ****
      Xiao D Y, Xie J, Chi M, Wang X, Yu Y H. Simulation of Gate-All-Around Cylindrical Transistors for Sub-10 Nanometer Scaling[J]. J. Semicond., 2008, 29(3): 447.

      Simulation of Gate-All-Around Cylindrical Transistors for Sub-10 Nanometer Scaling

      • Received Date: 2015-08-18
      • Accepted Date: 2007-09-17
      • Revised Date: 2007-11-06
      • Published Date: 2008-02-28

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return