| Citation: |
Chen Fangxiong, Lin Min, Chen Bei, Jia Hailong, Shi Yin, Dai Forster. Design of an Active-RC Low-Pass Filter with Accurate Tuning Architecture[J]. Journal of Semiconductors, 2008, 29(11): 2238-2244.
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Chen F X, Lin M, Chen B, Jia H L, Shi Y, Dai F. Design of an Active-RC Low-Pass Filter with Accurate Tuning Architecture[J]. J. Semicond., 2008, 29(11): 2238.
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Design of an Active-RC Low-Pass Filter with Accurate Tuning Architecture
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Abstract
An active-RC low-pass filter of 5MHz cutoff frequency with a tuning architecture is proposed.It is implemented in 0.18μm standard CMOS technology.The accuracy of the tuning system is improved to be within (-1.24%,+2.16%) in measurement.The chip area of the tuning system is only a quarter of that of the main-filter.After tuning is completed,the tuning system will be turned off automatically to save power and to avoid interference.The in-band 3rd order harmonic input intercept point (IIP3) is larger than 16.1dBm,with 50Ω as the source impedance.The input referred noise is about 36μVrms.The measured group delay variation of the filter between 3 and 5MHz is only 24ns,and the filter power consumption is 3.6mW.This filter with the tuning system is realized easily and can be used in many wireless low-IF receiver applications,such as global position systems (GPS),global system for mobile communications (GSM) and code division multiple access (CDMA) chips.-
Keywords:
- CMOS circuit design,
- auto tuning,
- active RC filter,
- wireless system
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References
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