Chin. J. Semicond. > 1996, Volume 17 > Issue 11 > 839-845
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一种减小关键路径延迟的回路布线法

乔长阁，洪先龙

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    Received: 18 August 2015 Revised: Online: Published: 01 November 1996

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      Article Navigation >  Journal of Semiconductors  > 1996  >  17(11): 839-845
      乔长阁，洪先龙. 一种减小关键路径延迟的回路布线法[J]. 半导体学报(英文版), 1996, 17(11): 839-845.
      Citation:
      乔长阁，洪先龙. 一种减小关键路径延迟的回路布线法[J]. 半导体学报(英文版), 1996, 17(11): 839-845.
      shu

      • Received Date: 2015-08-18

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