Citation: |
Cao Ying, Ren Tenglong, Hong Zhiliang. A 16bit 96kHz Chopper-Stabilized Sigma-Delta ADC[J]. Journal of Semiconductors, 2007, 28(8): 1204-1210.
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Cao Y, Ren T L, Hong Z L. A 16bit 96kHz Chopper-Stabilized Sigma-Delta ADC[J]. Chin. J. Semicond., 2007, 28(8): 1204.
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A 16bit 96kHz Chopper-Stabilized Sigma-Delta ADC
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Abstract
A 16bit sigma-delta audio analog-to-digital converter is developed.It consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the modulator.Chopper stabilization is applied to the first integrator to eliminate the 1/fnoise.A low-power,area-efficient decimator is used,which includes a poly-phase comb-filter and a wave-digital-filter.The converter achieves a 92dB dynamic range over the 96kHz audio band.This single chip occupies 2.68mm2 in a 0.18μm six-metal CMOS process and dissipates only 15.5mW power. -
References
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