Abstract: This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication.It is implemented in CSMC 0.5μm CMOS technology.Under a supply voltage of 3.3V,it has a power consumption of 198mW.The core of the circuit is composed of 6 cascaded amplifiers that are in a conventional structure of differential pairs,an output buffer,and a DC offset cancellation feedback loop.The small signal gain can be adjusted from 74 to 44dB by an off-chip resistor.The chip was packaged before being tested.The experimental results indicate that the circuit has an input dynamic range of 54dB and provides a single-ended output swing of 950mV.Its output eye diagram remains satisfactory when the pseudo-random bit sequence (PRBS) input speed reaches 400Mbps.

Key words: optical communication, limiting amplifier, CMOS technology, SDH