J. Semicond. > 2008, Volume 29 > Issue 10 > 1873-1878

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A PVT Tolerant Sub-mA PLL for High Speed Links

Yang Yi, Yang Liqiong, Zhang Feng, Gao Zhuo, Huang Lingyi and Hu Weiwu

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Abstract: A sub-mA phase-locked loop fabricated in a 65nm standard digital CMOS process is presented.The impact of process variation is largely removed by a novel open-loop calibration that is performed only during start-up but is opened during normal operation.This method reduces calibration time significantly compared with its closed-loop counterpart.The dual-loop PLL architecture is adopted to achieve a process-independent damping factor and pole-zero separation.A new phase frequency detector embedded with a level shifter is introduced.Careful power partitioning is explored to minimize the noise coupling.The proposed PLL achieves 3.1ps RMS jitter running at 1.6GHz while consuming only 0.94mA.

Key words: PLLPVT variationjitter

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    Received: 18 August 2015 Revised: 11 June 2008 Online: Published: 01 October 2008

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      Yang Yi, Yang Liqiong, Zhang Feng, Gao Zhuo, Huang Lingyi, Hu Weiwu. A PVT Tolerant Sub-mA PLL for High Speed Links[J]. Journal of Semiconductors, 2008, 29(10): 1873-1878. ****Yang Y, Yang L Q, Zhang F, Gao Z, Huang L Y, Hu W W. A PVT Tolerant Sub-mA PLL for High Speed Links[J]. J. Semicond., 2008, 29(10): 1873.
      Citation:
      Yang Yi, Yang Liqiong, Zhang Feng, Gao Zhuo, Huang Lingyi, Hu Weiwu. A PVT Tolerant Sub-mA PLL for High Speed Links[J]. Journal of Semiconductors, 2008, 29(10): 1873-1878. ****
      Yang Y, Yang L Q, Zhang F, Gao Z, Huang L Y, Hu W W. A PVT Tolerant Sub-mA PLL for High Speed Links[J]. J. Semicond., 2008, 29(10): 1873.

      A PVT Tolerant Sub-mA PLL for High Speed Links

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      国家高技术研究发展计划

      • Received Date: 2015-08-18
      • Accepted Date: 2008-05-10
      • Revised Date: 2008-06-11
      • Published Date: 2008-11-11

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