Abstract:

A 150 Msamples/s, 6 bit CMOS folding and current mode interpolating analog to digital is designed in a 1.2 μm digital CMOS technology. A low power, high speed regenerated current comparator is proposed. By adopting Domino logic circuit, a very simple and flexible decoder is realitied with high speed and low power. The latency between input signal and output code is less than 2 clock cycles. The ADC only uses a single clock and its complement which simplifies the whole circuit. The converter power dissipation is simulated as 185 mW from a 5 V supply.

Key words: ADC, CMOS, folding, current mode, interpolating, Domino