Chin. J. Semicond. > 2007, Volume 28 > Issue 4 > 537-541

PAPERS

2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

Liu Yongwang, Wang Zhigong and Li Wei

+ Author Affiliations

PDF

Abstract: A 2.5Gb/s clock and data recovery (CDR) circuit is designed and realized in TSMC’s standard 0.18μm CMOS process.The clock recovery is based on a PLL.For phase noise optimization,a dynamic phase and frequency detector (PFD) is used in the PLL.The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is -111dBc/Hz at 10kHz offset.The rms jitter of the recovered 2.5Gb/s data is 3.3ps.The power consumption is 120mW.

Key words: clock recoverydata recoveryphase locked loopdynamic phase and frequency detector

  • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 2968 Times PDF downloads: 2388 Times Cited by: 0 Times

    History

    Received: 18 August 2015 Revised: 28 November 2006 Online: Published: 01 April 2007

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Liu Yongwang, Wang Zhigong, Li Wei. 2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit[J]. Journal of Semiconductors, 2007, 28(4): 537-541. ****Liu Y W, Wang Z G, Li W. 2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit[J]. Chin. J. Semicond., 2007, 28(4): 537.
      Citation:
      Liu Yongwang, Wang Zhigong, Li Wei. 2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit[J]. Journal of Semiconductors, 2007, 28(4): 537-541. ****
      Liu Y W, Wang Z G, Li W. 2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit[J]. Chin. J. Semicond., 2007, 28(4): 537.

      2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

      • Received Date: 2015-08-18
      • Accepted Date: 2006-09-22
      • Revised Date: 2006-11-28
      • Published Date: 2007-04-09

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return