A 75 GHz regenerative dynamic frequency divider with active transformer using InGaAs/InP HBT technology

    Corresponding author: Zhi Jin, jinzhi@ime.ac.cn
  • Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

Key words: InPhetero-junction bipolar transistorsdynamic frequency divider

Abstract: This letter presents a high speed 2:1 regenerative dynamic frequency divider with an active transformer fabricated in 0.7 μm InP DHBT technology with fT of 165 GHz and fmax of 230 GHz. The circuit includes a two-stage active transformer, input buffer, divider core and output buffer. The core part of the frequency divider is composed of a double-balanced active mixer (widely known as the Gilbert cell) and a regenerative feedback loop. The active transformer with two stages can contribute to positive gain and greatly improve phase difference. Instead of the passive transformer, the active one occupies a much smaller chip area. The area of the chip is only 469×414 μm2 and it entirely consumes a total DC power of only 94.6 mW from a single -4.8 V DC supply. The measured results present that the divider achieves an operating frequency bandwidth from 75 to 80 GHz, and performs a -23 dBm maximum output power at 37.5 GHz with a 0 dBm input signal of 75 GHz.


1.   Introduction
  • Recently, the millimeter and sub-millimeter frequency bandwidth covering 75 to 300 GHz are associated with many applications such as communication, radar, medical and automotive imaging systems[1, 2]. The rapidly increasing demand has stimulated research on high performance microwave circuits, which are often required in these systems for dividing the received signal down to a lower operating frequency, thus the frequency dividers are an essential and critical circuit. To overcome the bandwidth limitation of a static divider, various reports of the dynamic frequency divider are sprouting up, especially a regenerative dynamic divider with operating up to 305-330$+$GHz in 0.25 $\mu $m InP HBT technology[3, 4].

    The dynamic frequency divider remains the results of topology structure and layout design to achieve the best compromise among speed, bandwidth, chip size and power[5-8]. For an HBT with a certain current gain cutoff frequency ($f_{\rm T})$, the maximum operating frequency is generally achievable in the range of about half of $f_{\rm T}{}$[9]. As regards the operating bandwidth, it usually will vary from $f_{\rm T} /$4 to $f_{\rm T} /$2 of an available range. The large areas of chip are occupied with a pair of GSG pads for the convenience of on-wafer testing, and are occupied by passive balun for the high quality balanced signals, respectively. Therefore, the topology and layout of our choice would be preferred to pursue smaller size consumption and combine high maximum frequency with wide operating bandwidth.

    In this paper, we report a regenerative frequency divider operating from 75 to 80 GHz, which is limited by the available RF input signal generator. The dynamic divider was fabricated in our own 0.7 $\mu $m InGaAs/InP double heterojunction bipolar transistor process with $f_{\rm T} $ of 165 GHz and $f_{\rm max} $ of 230 GHz. That HBT process includes the 0.7 $\mu $m width emitter, thin-film TaN resistors, MIM capacitors and 3-level interconnect wiring. The chip microphotograph is illustrated in Fig. 1, whose area is only $469\times414$ $\mu $m$^{\mathrm{2}}$. The entire chip consists of an active transformer, input buffer, divider core and output buffer with a 50 $\Omega$ load, which only consumes 94.6 mW with a single $-4.8$ V supply voltage. To pursue a higher frequency operation, all HBTs bias point of the main signal path, excluding mirror current source, would be as far as possible satisfying those optimized biasing conditions $V_{\rm ce} = 1.7 $ V and $I_{\rm c} = 3.5$ mA.

2.   Circuit design
  • The principle of regenerative frequency divider may be well explained with the generalized schematic of Fig. 2. First, the input RF signal is applied to the active transformer; the differential signal will be generated and amplified. Secondly, the differential signal (RF$+$and RF) will pass the input buffer and enter into one input port of the mixer, and then the filtered output signal is fed back to the second input port of the active mixer. A Gilbert cell is widely known as a typical active mixer, which is the best choice for the differential network. No separate filter is supplied because of the inherent low-pass properties of a double balanced mixer[3]. With the main advantages of good multiplier and linearity, the output signal of the mixer is a typical value ($f_{\rm out} \pm f_{\rm in})$, assuming that the input frequency of the mixer is $f_{\rm in}$ and the output frequency is $f_{\rm out}$. Due to the low-pass properties, only the $f_{\rm out}-f_{\rm in}$ signal can pass and be fed back to the input port ($f_{\rm in})$, thus the desired $f_{\rm in\thinspace }$/2 would be regenerated at the IF output port. In addition, a symmetrical double balanced circuit can cancel both the harmonic ($f_{\rm in}$, 2$f_{\rm in}$, $\cdot\cdot\cdot$) and odd harmonic (3$f_{\rm in\thinspace }/$2, 5$f_{\rm in\thinspace }/$2, $\cdot\cdot\cdot$) at the IF output port. Surely, IF output signals ($f_{\rm in}/$2) are also prevented from penetrating back to the RF input port. Meanwhile, the filtered IF signal ($f_{\rm in}/$2) would be amplified through the output buffer.

    Although the Gilbert cell can also tolerate single-ended signals, the cost of this choice is slightly degraded linearity. For instance, the RF$+$input port can be directly taken as a single-ended signal with the RF-input AC grounded. As a result, the conversion gain and the maximum operating frequency would reduce to a relative extent, that degenerations are obviously undesirable in this design.

  • 2.1.   Active transformer and input buffer

  • With the discussion above, the double balanced structure is preferred, and it would need a transformer. An ideal differential transformer should generate a pair of differential output signals of balanced amplitudes and phases (0 dB gain difference and 180 degree phase difference) from a single input. The passive Marchand balun usually occupies a large area and finally would increase the overall chip cost. Further, the passive balun could not contribute any gain. The degradation of the output differential signal is very serious, and insertion loss and bandwidth would become worse with increasing the operating frequency, thus it is very difficult to achieve an optimal compromise between size consumption and signal gain for a passive transformer.

    However, an active transformer can provide high-quality balanced signals with extra conversion gain and wider bandwidth[10]. Another advantage is that it consumes only a very small chip area than a passive transformer. In this study, a two-stage active transformer was designed and adopted, which will convert the RF single-ended signal to a pair of differential signals (RF$+$and RF).

    Fig. 3 presents the two-stage active transformer topology, including some biasing components. The first stage of this transformer comprises two emitter followers (Q1 and Q2) and a differential pair (Q3 and Q4). The emitter followers will shift down the bias level and provide enough signal to drive the differential pair, which would be completely switched by the collector load of Q3 and Q4. A RF input signal is applied to the base of follower Q1 after DC blocking, and follower Q2 is opened. The signal phase shifts 180 degree from port A to port C, while the same signal reaches port B without any phase converting. Due to no load of the base current, the emitter signal of the Q4 device has the same phase with the collector signal, thus this first stage of the active transformer provides a 180 degree phase shift between C port and D port. On account of the limitation of single-ended signal input, the Q4 device cannot provide any signal gain at the D port, but the signal of the C port can be amplified.

    Thus, the first stage is difficult to generate high-quality balanced signals with the operating frequency increasing as shown in Fig. 4. The S21.1stage and S31.1stage are the $S$-parameters of the first stage; S21.2stage and S31.2stage are the $S$-parameters of the second stage.

    The second stage is very important, and the performance of the transformer could be improved a lot with an amplification effect of the differential pair (Q7 and Q8) as shown in Fig. 4. Two emitter followers (Q5 and Q6) shift down a level and drive the differential pair (Q7 and Q8). When combined with the first stage, the second stage can contribute positive gain and greatly improve the phase difference. Simulation results show that the two stages can give 11 to -5 dB gain with operating from 10 to 75 GHz, and the mismatch is only 1.5 dB in amplitude difference, even up to 110 GHz. The biasing current and output load were optimized to obtain promising converting efficiency.

    The input buffer circuit would require shifting down about 2 voltages to supply the next stage. Two stage emitter followers are enough to drive the lower level differential pair of the divider core. This active transformer including passive components and nonlinear HBTs model was simulated by the momentum electro-magnetic (EM) simulator in the Agilent Advanced Design System (ADS).

  • 2.2.   Divider core

  • The core of the dynamic frequency divider is composed of a double-balanced active mixer (widely known as the Gilbert cell) and a regenerative feedback loop[11]. Fig. 5 shows its simplified schematic: two signals inside the divider core are differential. The input signals at frequency $f_{\rm in} $ are applied to a lower-level differential pair (T1 and T2), which is the driver stage for its upper-level (T3, T4, T5 and T6). The input signal is applied to the lower-level of the Gilbert cell, because this reduces the input capacitance of the circuit. This is beneficial for achieving high input sensitivity[12].

    The differential output current of the driver stage is commutated, and then the active mixer output will be fed back to its upper-level through emitter followers (T7 and T8). If the feedback loop can sustain proper amplitude and phase condition, the desired $f_{\rm in}/$2 frequency signal will generate at the IF port. In addition, to ensure more high-speed operation, the layout of the divider core minimized the signal path length of the feedback loop in order to reduce the transmission delay.

  • 2.3.   Output buffer

  • The output buffer consists of two followers (X1 and X2) and a differential pair (X3 and X4) as shown in Fig. 6. The emitter followers work with lower current to reduce the output load of the divider core and also serve as a level shifter to drive the subsequent pair. The differential pair is designed to drive 50 $\Omega$ resistors to pursue a maximum output power[13]. As a result, the output buffer would reduce spikes of waveforms and amplify balanced signals with enough power to drive other circuits.

3.   Measurements and results
  • The dynamic divider performance at 75 GHz was carried out using an Agilent E4447A spectrum analyzer using a dedicated on-wafer test system in Fig. 7. A multiplier by 6 was connected to signal source E8257D to provide the W-band input signal. The waveguide and coaxial line loss were calibrated by a power sensor, which had induced a loss of about 5 dB between input and output.

    With -4.8 V supply voltage, the entire divider including a two-stage active transformer, input and output buffer consumes 94.6 mW. Stable operation of the divider is shown in Fig. 8 at 37.5 GHz with $-$23 dBm output power, which is not corrected with cable and probe loss. A weak harmonic ($-38$ dBm) of $f_{\rm in}/$3 input frequency at 25 GHz is captured in the output spectrum. That $f_{\rm in}/$3 harmonic is mainly caused by the $R_{\rm {load}}$ of the divider core. The maximum divider operating frequency would increase more than 20% with a stronger shifting of load signal, according to simulation[3]. Surely, this shift also yields a weak harmonic. The divider is not functional above 80 GHz, as the maximum operating frequency is simulated only up to 82 GHz. On account of the limited bandwidth of our signal generator (75 to 110 GHz), an input signal that is lower than 75 GHz would not be generated.

    The measurement of output power ($P_{\rm out:meas})$ with input frequency was swept from 75 to 80 GHz with the output power from $-23$ dBm to $-39.68$ dBm as shown in Fig. 9, where the value of input power ($P_{\rm in:meas})$ is all the same 0 dBm. The actual input signal power ($P_{\rm in:deem})$ with a calibrated loss would approximate to -5 dBm. The divider was simulated to operate properly from 38 to 82 GHz with a constant input power of 0 dBm, and the simulated output power ($P_{\rm out:sim})$ is from $-10.5$ dBm down to $-19.98$ dBm (lower than 75 GHz is not shown in Fig. 9). The simulated input frequency range is from 38 to 82 GHz, and Fig. 10 shows the simulated results in ADS. Fig. 10(a) shows the output frequency and output power when input frequency is 38 GHz. Fig. 10(b) shows the output frequency and output power when input frequency is 82 GHz.

    It seems that measured output power is obviously lower 15 to 20 dB than that simulated from 75 to 80 GHz. Partially, this is because the actual input power provided to the frequency divider was $ -5$ dBm, while the simulated input power was 0 dBm.

    When maintaining an input power of $-5$ dBm, the output power gradually reduced from $-23$ to $-39.68$ dBm with increasing the input frequency. This worse linearity is explained in greater detail as follows.

    The reason may be that the insertion loss is less than $-5$ dB when the active transformer is operating above 75 GHz, as shown in Fig. 4. When the input signal is less than $-5$ dBm, its amplitude is too weak to drive the divider core. As a result, there is no longer conversion gain of the Gilbert active mixer as an analog multiplication. To achieve maximum power transfer, we need to match the impedance of the divider core to the input buffer. However, this divider takes no account of the effect of impedance match. The harmonic simulated result presents that there is no small signal gain above 68 GHz, when the differential pair (T1 and T2) has the same bias and input signal.

    The above discussion arrives at a conclusion that the worse linearity was mainly caused by low insertion loss and poor conversion gain with the higher operating frequency. Furthermore, all passive components and wirings in the layout would bring in an external attenuation and induce a loss of output power. Particularly, due to the complexity of the feedback loop in the layout design, the length of feedback wirings (Line1 and Line2 in Fig. 4) is more than 75 $\mu $m, which was like a series inductance in the W-band. Assessing the high attenuation values per unit length, one should bear in mind that the transmission loss could be neglected when interconnection lines are shorter than a critical wavelength ($\lambda $/30) in W-band. Owing to the internal parasitic inductance of L1 and L2, the simulated result exhibits a negative slope over the whole W-band, with the performance decreasing by 3%-17% from 38 up to 82 GHz. This simulated investigation also could identify the worse linearity, which is caused by the transmission loss in the feedback loop.

    Another alternative, the coplanar waveguide process could provide a good ground reference for reducing the transmission loss. This would cancel out the differences in effective loss compared with a parasitic inductance, at least partly. Rather, this choice also would result in an extended circuit size. Nevertheless, the wirings design is difficult to achieve the best compromise among the longer line with parasitic inductances and increasing size consumption with the coplanar waveguide process.

    Table 1 shows the comparison of performances of the InP HBT frequency divider in this work with other frequency dividers.

4.   Conclusion
  • We have presented a regenerative dynamic frequency divider with an active transformer using InP HBT technology. The divider achieved an operating frequency bandwidth from 75 to 80 GHz and performs a $-23$ dBm maximum output power at 37.5 GHz with a 0 dBm input power at 75 GHz. The lack of an available RF generator source prevented the divider from measuring below 75 GHz of the input frequency. The two-stage active transformer could produce high-quality balanced signals to drive the divider core, which employed a typical Gilbert cell to perform frequency division. The total power consumption of the chip is only 94.6 mW with $-4.8$ V supply voltage.

Figure (10)  Table (1) Reference (16) Relative (20)

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