The design of miniaturized broadband power divider utilizing GaAs-based IPD process and equivalent circuit model

    Corresponding author: Ying Lu,
  • Nanjing Electronic Device Institute, Nanjing 210016 China

Key words: thin film integrated passive device (TF-IPD)parameters extractionde-embeddinglumped element

Abstract: The GaAs-based TF-IPD fabrication process and equivalent lumped element circuit are utilized to reduce the circuit size for double-section Wilkinson power divider. Ultimately the dimension of the proposed S-band power divider is reduced to 1.03×0.98 mm2. Its measured results show an operating fractional bandwidth of 54%, and return losses and isolation of greater than 20 dB. In addition the excess insertion loss is less than 1.1 dB. Moreover the good features contain amplitude and phase equilibrium with the values of better than 0.03 dB and 1.5° separately. This miniaturized power divider could be widely used in RF/microwave circuit systems.


1.   Introduction
  • In recent years, packaging technology such as system in package (SIP)[1-3], and system on package (SOP)[4] as the approaches of micro-system implementation for communication hardware have developed rapidly. Power divider (PD) owing to its practicality is widely used in RF/microwave circuits for wireless communication systems, such as front-end transceiver modules, feed networks of the array antenna and so on. However, because of the employment of multiple $\lambda $/4 wavelength lines in a conventional layout design, the size of the device is too large to be used in micro-system. Integrated passive device (IPD) technology which emerges as the times require, could be adopted to eliminate it. By means of integrating passive components on a semiconducting substrate or in a multilayer substrate, the dimensions of the traditional discrete components are reduced greatly.

    Many fabrication processes have been developed to implement IPD. In Ref. [5], the wideband PD is proposed with distributing multi-section among 13-layer LTCC material vertically, and integrating NiCr resistors. Finally, a compact ultra-wideband power divider with the dimensions of 4 × 4 × 1.33 mm$^{\mathrm{3}}$ is obtained. Other designs are accomplished based on thin film technology of a compound semiconductor. Practicable substrate materials could be silicon, GaAs and glass etc. In Ref. [6], the C-band PD with matching feature is implemented by adopting the 0.35 $\mu$m SiGe BiCMOS fabrication process, while Refs. [7-9] report the proposed devices achieved using Glass-based and GaAs-based fabrication process respectively.

    Compared to the thick film fabrication process, the thin film process has more advantages in developing IPD technology, such as accuracy, repeatability, reliability, smaller device size, and lower cost. Moreover, active devices can also be integrated.

    IPD based on GaAs substrate has been reported less than other semiconducting material. However, due to the use of semi-insulating GaAs high-resistance single crystal substrate, it provides many good performances: low loss, small parasitic resistance, good interconnection, compact size, etc. Ref. [10] reports an S-band PD with the size of 0.8 × 0.61 mm$^{\mathrm{2}}$ and the implementation by the GaAs-based fabrication process. However, it has some disadvantages, such as the operating fractional bandwidth is less than 7% and all return losses are greater than 15.2 dB.

    In this work, the proposed S-band PD is accomplished on a substrate of 3-inch GaAs wafer. RF performances are optimized by using the equivalent circuit model. Lastly, the device is provided with excellent performances and compact structure.

2.   Circuit design

    2.1.   Theory of Wilkinson power divider

  • In this paper the method of equivalent lumped element circuit replacing $\lambda$/4 wavelength transmission line in multi-section Wilkinson PD is employed to realize the proposed PD with properties of wide operating bandwidth and miniaturization.

    The lumped element values in Fig. 1 can be obtained by Eqs. (1) and (2). Normalized values of impedances in Fig. 2(a) are given as: $Z_{\rm {02}}=1.6670$, $Z_{\rm {01}}=1.1998$, $R_{\rm {2}}=1.8643$, $R_{\rm {1}}=5.3163$. Herein with substituting values of $Z_{\rm {02}}$, $Z_{\rm {01}}$ in Eqs. (1) and (2), and defining the center frequency: $f=2.75$ GHz, the four distinct parameters of $L$ and $C$ in Fig. 2(b) are solved as: $L_{\rm {1}}=3.47$ nH, $C_{\rm {1}}=$ 0.97 pF, $L_{\rm {2}}=$ 4.8 nH, $C_{\rm {2}}=0.69$ pF, $R_{\rm {1}}=265.8$ $\Omega $, $R_{\rm {2}}=93.2$ $\Omega $.

    where ${\omega =2}\pi f$, and $n=1$, 2.

  • 2.2.   Component modeling and parameter extracting

  • Performance and integration of each component ($L$, $C$, $R$) play important roles in properties of passive devices. In this paper, the foundation of the components design is based on equivalent circuit models. Here, the element values of the models are calculated by extracting parameters from simulated or measured $S$-parameters.

    The equivalent circuit model of spiral inductors ($L_{\rm {1}}$, $L_{\rm {2}})$ is based on 1-$\pi $ model[11] as shown in Fig. 3(a). Where $R_{\rm {Lsub1}}$, $R_{\rm {Lsub2}}$ are defined as substrate leakage resistances, $C_{\rm {Lsub1}}$, $C_{\rm {Lsub2}}$ as substrate parasitic capacitances, $C_{\rm {Ls}}$ as feedthrough capacitance which is the superposition of two kinds of parasitic capacitances: one lies on adjacent metal wire edges, another lies between two metal lines in the cross-sectional area. Besides, $L_{\rm {s}}$ represents equivalent series inductance, and $R_{\rm {Ls}}$ denotes equivalent series resistance including ohmic losses and skin effect.

    The equivalent circuit model of the metal-insulator-metal (MIM) capacitor ($C_{\rm {1}}$, $C_{\rm {2}})$ is shown in Fig. 3(b). $C_{\rm {s}}$ is the effective capacitance. $L_{\rm {Cs\thinspace }}$and $R_{\rm {Cs}}$ represent parasitic inductance and dielectric loss resistance respectively. In addition, $R_{\rm {Csub1}}$, $R_{\rm {Csub2}}$ are substrate leakage resistances, and $C_{\rm {Csub1}}$, $C_{\rm {Csub2}}$ are parasitic capacitances of the substrate.

    The equivalent circuit model of the thin film resistor (TFR) ($R_{\rm {1}}$, $R_{\rm {2}})$ is not only related to the structure and material, but also to its manufacturing process, as shown in Fig. 3(c). $L_{\rm {Rs}}$ represents parasitic inductance, and $R_{\rm {s}}$ is effective resistance. In addition, $R_{\rm {Rsub1}}$, $R_{\rm {Rsub2}}$ and $C_{\rm {Rsub1}}$, $C_{\rm {Rsub2\thinspace }}$are substrate leakage resistances and substrate parasitic capacitances respectively. Moreover, $R_{\rm {Rt1}}$, $R_{\rm {Rt2}}$ and $C_{\rm {Rt2}}$, $C_{\rm {Rt1}}$ are parasitic resistances and capacitances caused by ohmic contact between source and drain, here they are omitted due to the small values.

    The element values of each equivalent circuit model in Fig. 3 could be calculated in the following steps. Firstly, software simulation or on-chip measurement is employed to obtain $S$-parameters. Secondly, $S$-parameters are converted to $Z$-and $Y$-parameters. Lastly, the values of elements are separated and extracted according to Eqs. (3)-(10)[11].

    where $y$ is the $ Y$-parameters matrix. Moreover quality factor $ Q$ and resonant frequency $ f_0$ are neededfor the calculation of equations shown below:

    where L11 is port inductance.

3.   Simulation and discussion

    3.1.   Components simulation and optimization

  • Since the values of $L_{\rm {1}}$, $L_{\rm {2}}$, $C_{\rm {1}}$, $C_{\rm {2}}$, $R_{\rm {1}}$, and $R_{\rm {2}}$ have been calculated, the layout of each component can be obtained. Next all of them are ranged together according to the schematic shown in Fig. 2(b), so the initial layout of PD is attained. Generally speaking, the performances of this layout are always not so ideal, therefore optimization is needed. The implemented steps are described as follows: (1) Calculate the values of elements in the equivalent circuit model by using an EM simulator. (2) Establish and simulate the equivalent circuit of PD which contains parasitic parameters of each component in ADS. (3) Tune main parameter ($L_{\rm {s}}$, $C_{\rm {s}}$, $R_{\rm {s}}$ in Fig. 3) of each component until the results are satisfactory. (4) According to the modified values, the layout of PD is amended, and simulated. (5) Return to step (1), until the simulated results meet requirements.

    By the steps above, the element values of equivalent circuit model for each component are shown in Tables 1-3.

    Considering capacitor $C_{\rm {1}}$ and $C_{\rm {2\thinspace }}$in the PD schematic are always grounded at one end, Table 2 shows the substrate leakage resistance and capacitance at one port only. Besides, according to Tables 1-3, the parameters tabulated herein are all extracted below resonant frequency $f_{\rm {0}}$ and effective over a range of the operating-band.

  • 3.2.   Spiral inductor experimental results

  • In order to verify the consistency between the simulation model and the fabrication process, two kinds of optimized spiral inductors are sampled and measured individually. For abating measurement error, the parasitic parameters of DUT ports are stripped by using the de-embedding technique based on open and short calibration method [12]. The layouts of inductors $L_{\rm {2\thinspace }}$and $L_{\rm {1\thinspace }}$are shown in Fig. 4.

    The data in Table 4 show that: (1) The simulated results of equivalent series inductance $L_{\rm {s}}$ and self resonant frequency $f_{\rm {0}}$ agree with the ones solved by de-embedding technique. Hence the results from EM simulator (ADS) are effective for predicting the inductance $L_{\rm {s}}$ and resonant frequency $f_{\rm {0\thinspace }}$of the spiral inductor. (2) There are differences in the maximum values of quality factor $Q$ between the results from measurement and simulation. They denote that the model is not so exact in foretelling the values of $Q$, because of simplifying some parameters in simulation, while it will not affect the layout design distinctly. Anyway the results confirm that the simulation model reflects the fabrication process effectively, and the accuracy meets the requirements of design.

  • 3.3.   Device simulation and measurement

  • After optimization, the layout of the designed PD is accomplished as shown in Fig. 5(a). Here, it is simulated by the full-wave simulator ADS and HFSS.

    The parameters of the proposed device are shown in Table 5.

    The circuit area is only 1.01 mm$^{\mathrm{2\thinspace }}$ as shown in Fig. 5(b). It is remarkably reduced when comparing to traditional ones. Fig. 6 displays the distribution of the surface current and the electric field in the substrate at the frequency of 2 GHz and two phases of 0° and 90°. Surface current and electric field fluctuate synchronously as time goes on. The chip die on-wafer measurement is done by an Agilent network analyzer of N5224A with a probe station of Cascade Microtech. The comparison between the results of measured and EM simulated are shown in Fig. 7.

    The measured results show that the transmission losses of each signal path are below 4.1 dB and three return losses are greater than 20 dB. In addition, isolation is greater than 20 dB. The performances are excellent in the operating frequency between 2 and 3.5 GHz, which implies the operating fractional bandwidth corresponds to 54.5%. When the isolation and return losses satisfy the condition of better than 15 dB, it equals to 74.5%. The results of EM simulation, equivalent circuit model and measurement are basically consistent. However, due to the errors introduced by measurement and parasitic effects, the measured results deviate from the simulated and modeled ones a little.

    The two signal paths of the designed PD are symmetrical. The evaluation of amplitude and phase equilibrium level can be observed in Fig. 8. From the graph, the amplitude differences are $-0.2$ to 0.03 dB (1-7 GHz) and $-0.03$ to 0.03 dB (1-4 GHz). Yet, the phase differences are less than 1.5° (1-7 GHz).

    In Table 6, the results of similar studies published in recent years are compared with the ones in this paper. By observing, the proposed IPD PD has some advantages in terms of circuit size and electrical performances. In addition, the method of the design is simple, the process of the fabrication is uncomplicated, and the consistency of the mass produced is fine.

4.   Conclusion
  • The $S$-band PD with the features of wideband and compact size is realized in this paper. The GaAs IPD process is applied in its fabrication. Moreover, an equivalent circuit model is introduced in its design. Comparing with the other works in the literature, its advantages are obvious. The proposed PD is suitable for mass production, and RF circuit system application.

Figure (8)  Table (6) Reference (16) Relative (20)

Journal of Semiconductors © 2017 All Rights Reserved