Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

    Corresponding author: Haisong Li,
  • Xi'an Microelectronics Technology Institute, Xi'an 710054, China

Key words: single event effectsingle event transientradiation-hardenedguard ring, standard cell librarypulse width

Abstract: With the critical charge reduced to generate a single event effect (SEE) and high working frequency for a nanometer integrated circuit, the single event effect (SET) becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n+ guard ring and p+ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient (SET) pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET's pulse-width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV·cm2/mg, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LETeff from 12.5 MeV·cm2/mg to 79.5 MeV·cm2/mg and the pulse-width presents saturation tendency when the effective linear energy transfer (LETeff) value is larger than 40 MeV·cm2/mg. The test results also show that the hardened commercial standard cell's pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.


1.   Introduction
  • In the Earth's orbits, there are four primary sources of radiation: plasma, trapped particles, solar particles and comic rays. These radiation sources include a large sum of electrons, protons, and high-energy charged particles, which induce a single event effect in the semiconductor IC of space-shuttles and satellites. In order to get higher performance, the frequency of radiation-hardened VLSI is getting higher. As the clock frequency exceeds 100 MHz, SET could dominate the soft error response of the logic VLSI operating in space. Because the error rate of a logic VLSI is closely related with pulse-width, it is meaningful to study radiation-hardened ways of SET effects and to analyze the distributed pattern of a single event transient pulse-width. The experiment by Balaji Narasimham et al. showed that high density well contacts and guard band mitigate the width of SET pulses[2]. Gadlage et al. measured the SET pulse width in a 65nm bulk CMOS technology at temperatures ranging from 25 to 100 [3]. Makino et al. proposed an effective method to measure the SET pulse width of an inverter chain, which was fabricated in 0.2 $\mu $m PD SOI technology[4]. Ahlbin and Du studied the relationship between the layout topology and SET in the CMOS integrated circuit [5, 6]. The performance of SET was also analyzed in the FPGA circuit, scan flip-flop, redundant delay filter (RDF), 90 nm bulk CMOS process, 65 nm bulk CMOS process, SOI FinFETS, phase-locked loop, and so on[7-17].

    Time redundancy techniques [18, 19], as shown in Fig. 1, have been developed to eliminate SET pulses of which the values are smaller than a predetermined threshold value. For the excellent trade-off between clock frequency and radiation-hardened performance, it is necessary to analyze the distributing pattern of SET pulse width to set the threshold value in a specific process.

    In this work, based on the radiation-hardened logic cell in 65 nm bulk CMOS technology, the weakest driving capacity of an inverter, which generates the biggest pulse width at the same situation for a single-event happening, is used to constitute the inverter chain. By using a pulse capture circuit like the one described in Ref. [4], the distributing pattern of the radiation-hardened inverter cell's SET pulse width was measured in the cases of effective LET equal to 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV$\cdot$cm$^{\mathrm{2}}$/mg, respectively.

2.   Radiation-hardened inverter
  • The under-test inverter was radiation-hardened by the elaborate layout design, as shown in Fig. 2, adopting an idea like the one described in Ref. [2]. The inverter layout in Ref. [2] was hardened by a guard band without contacts and high-density well contact. In this paper, the pMOS transistor is enclosed by the n$^+$ guard ring, which contacts with VDD, and the nMOS transistor is enclosed by the p$^+$ guard ring, which contacts with GND. To get the worst case or the maximum pulse-width of SET, the under-test inverter was a cell which has the weakest drive capacity in the standard cell library. Gate widths of the nMOS and pMOS in the inverter are 360 and 460 nm. The nMOS and pMOS transistors' gate lengths equal to 60 nm.

3.   Test circuit
  • Test circuit design is based on the test circuit structure for the pulse width of SET shown in Ref. [4]. It consists of a test pulse generator, an inverter chain under test, a multiplexer, two pulse expanders, two pulse captures, two parallel-to-serial converters and a comparator, as shown in Fig. 3. As shown in Ref. [4], the relationship between $N_{\rm 1}$ and $T_{\rm w}$ is expressed as

    where $T_{\rm W} $ is the width of the pulse coming from the test pulse generator or inverter chain under test, and $N_{\rm 1}$ is the number of '1' in the outputs of the self-triggering flip-flop chain in the pulse capture block, and $\Delta T$ is the delay time of every two inverters in the pulse capture circuit, and $T_{\rm b} $ is the width broadening at the pulse expander.

    The block of the test pulse generator is used to produce the testing pulse, which can be utilized to calibrate the increment of the pulses through the pulse expander and to debug the test circuit in the non-radiation environment. The test pulse generator includes an adjustable oscillator. The output frequency of the oscillator, as shown in Fig. 4, can be changed to get various widths of pulse. The block of periodic signal to pulse signal converts the periodic signal to the pulse. The test point is used to measure the frequency of the oscillator, which can be utilized to calculate the value of $T_{\rm W} $, which stems from the block of the test pulse generator. This method calibrates the width of the test pulse on-line eliminating the PVT's (process, voltage and temperature) influence.

    There are 8 inverter chains in the test circuit, as shown in Fig. 5. Each chain includes 200 stages. The 8 inverter chains are combined by or-gates. The last output is connected to a multiplexer of 2-to-1. Because the inverters under test have the weakest drive capacity in all radiation-hardened standard cells, the experimental results of SET pulse-width represent the worst case, which can be utilized to set the time interval for time redundancy techniques. Here, a propagation induced pulse broadening (PIPB) effect, as shown in Refs. [20-23], was not considered, since the effect exists in a radiation environment and we just want to get the practical data with the PIPB effect.

    SET pulse width test circuit is a dual-lane measurement circuit and the comparator shown in Fig. 3 is an xor-gate. If the SET pulse originates from the inverter chain under test, the output signals of two lanes are the same and the value of signal 'monitor' in Fig. 3 is '0'; if the SET pulse originates from the pulse expander, pulse capture, or parallel-to-serial converter, the output signals of two lanes are different and the value of signal 'monitor' is '1'. Of course, we suppose that the SET pulse does not generate at the same time and the same place in the two lanes; in other words, the probability of the situation is too low for this to happen. So, we can exclude the SET pulse coming from the dual-lane measurement circuit from the test results and get more accurate experimental data. The chip was fabricated in a 65-nm CMOS process. Because the or-gates's area is much smaller than the area of inverter chains, the SET pulse generated by or-gates is very low compared to one generated by inverter chains. In addition, the or-gates in inverter chains have a high driving capacity, so it is hard to generate the SET pulse. Therefore, or-gates in an inverter chain do not influence the SET pulse-width test results.

4.   Experimental and results
  • Heavy ion irradiation tests were performed in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The test circuits were irradiated in a vacuum chamber with a broad beam of Cl (164 MeV), Ti (150 MeV), Cu (200 MeV), Br (218 MeV), I (240 MeV) or Au (280 MeV) at 0 degrees. The six kinds of ions provide effective LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV$\cdot$cm$^{\mathrm{2}}$/mg, respectively. The injection distances of the six kinds of ions are 47.4, 31, 30.2, 31.5, 27 and 26.2 $\mu$m, respectively. Each heavy ion was irradiated with a fluence of 10$^{\mathrm{7}}$ ions/cm$^{\mathrm{2}}$.

    Each heavy ion irradiates four chips to accumulate more information. To get the worst case, the power voltage of the chip was set by 1.08 V instead of 1.2 V. In this situation, the SET pulse generates more easily and the pulse-width of the SET is greater. We got the value of $\Delta T$ and $T_{\rm b} $ about equal to 33 and 503 ps respectively through the test pulse generator circuit.

    Figs. 6(a)-6(f) show histograms of the SET pulse-widths we observed. Pulse counts are plotted as a function of measured pulse-width $T_{\rm {W}}$. All pulse-widths are shorter than 400 ps in the range of LET$_{\rm {eff}}$ from 12.5 to 79.5 MeV$\cdot$cm$^{\mathrm{2}}$/mg. This implies that most of the pulses generated in the space environment would be shorter than 400 ps for this radiation-hardened standard library because this inverter has the weakest driving capacity in the library. Therefore, if the time redundancy technique is adopted, the time interval value between adjacent clocks could be set 400 ps to eliminate most of the SET pulse generating from the combinational logic. There are more SET pulses of 66 ps than the others in Figs. 6(a)-6(f), which is perhaps due to the sensitive volume decrease in nano-meter CMOS technology for SET and EHP absorbed faster by the guard ring. In Figs. 6(d)-6(f), because more EHPs are generated by ions with bigger LET$_{\rm {eff}}$, SET pulses in the range of 99 to 264 ps increase obviously.

    The unhardened commercial standard cell's pulse-width, which is analyzed in Ref. [1], focus on 40 to 440 ps for the VP inverter chain using Krypton with LET of 40.5 MeV$\cdot$cm$^{\mathrm{2}}$/mg. Fig. 6(a)-6(f) show that the hardened commercial standard cell's pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of Ref. [1]. Experimental results of Ref. [24] show that the SET pulse width for an unhardened inverter cell fabricating in 65 nm bulk CMOS, distribute between about 70 and 400 ps, which increase about 50% compared to the hardened inverter's SET pulse width in this paper. This phenomenon, which is mainly due to the EHP generated by heavy ions, can be absorbed faster in the hardened standard cell, which adopts an n$^{\mathrm{+}}$ guard ring and a p$^{\mathrm{+}}$ guard ring to enclose the PMOS transistor and NMOS transistor respectively, than in an unhardened standard cell.

    Fig. 6(g) shows the maximum SET pulse-width of (a)-(f) as a function of effective LET. It suggests that the maximum SET pulse-width increases with the bigger value of LET$_{\rm {eff}}$. The fastest change rate of SET pulse-width happens in the range of LET$_{\rm {eff}}$ from 20 to 40 MeV$\cdot$cm$^{\mathrm{2}}$/mg. It also exhibits the saturation tendency of the SET pulse-width in the effective LET range from 40 to 80 MeV$\cdot$cm$^{\mathrm{2}}$/mg, which agrees with the results of Ref. [3]. Fig. 6(h) shows the total counts of (a)-(f) as a function of effective LET. It suggests that there are more and more SET pulses as the LET$_{\rm {eff}}$ becomes bigger and bigger.

5.   Conclusion
  • The SET pulse-width of the weakest driving inverter, radiation-hardened by the n$^{\mathrm{+}}$ guard ring and the p$^{\mathrm{+}}$ guard ring in the layout, was measured by the improved pulse capture circuits. The results indicated that most of the SET pulse-widths are shorter than 400 ps in the range of LET$_{\rm {eff}}$ from 12.5 to 79.5 MeV$\cdot$cm$^{\mathrm{2}}$/mg. The pulse width of SET presents the saturation tendency when the LET$_{\rm {eff}}$ value is larger than 40 MeV$\cdot$cm$^{\mathrm{2}}$/mg and the SET pulses become more frequent when the LET$_{\rm {eff}}$ becomes bigger and bigger.

Figure (6)  Reference (24) Relative (20)

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