Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects

Santosh K. Gupta; Srimanta Baishya

doi:10.1088/1674-4926/34/7/074001

Abstract: A physically based analytical model for surface potential and threshold voltage including the fringing gate capacitances in cylindrical surround gate (CSG) MOSFETs has been developed. Based on this a subthreshold drain current model has also been derived. This model first computes the charge induced in the drain/source region due to the fringing capacitances and considers an effective charge distribution in the cylindrically extended source/drain region for the development of a simple and compact model. The fringing gate capacitances taken into account are outer fringe capacitance, inner fringe capacitance, overlap capacitance, and sidewall capacitance. The model has been verified with the data extracted from 3D TCAD simulations of CSG MOSFETs and was found to be working satisfactorily.

Key words: physics based modeling, source/drain extension (SDE), cylindrical surrounding gate (CSG) MOSFETs, fringing field, surface potential, threshold voltage

References:

[1]	Shrivastava R, Fitzpatrick K. A simple model for the overlap capacitance of a VLSI MOS device[J]. IEEE Trans Electron Devices, 1982, 29(12): 1870. doi: 10.1109/T-ED.1982.21044
[2]	Greeneich E W. An analytical model for the gate capacitance of small-geometry MOS structures[J]. IEEE Trans Electron Devices, 1983, 30(12): 1838. doi: 10.1109/T-ED.1983.21456
[3]	Suzuki K. Parasitic capacitance of submicrometer MOSFET's[J]. IEEE Trans Electron Devices, 1999, 46(9): 1895. doi: 10.1109/16.784191
[4]	Mohapatra N R, Desai M P, Narendra S G. Modeling of parasitic capacitances in deep submicrometer conventional and high-k dielectric MOS transistors[J]. IEEE Trans Electron Devices, 2003, 50(4): 959. doi: 10.1109/TED.2003.811387
[5]	Kumar M J, Gupta S K, Venkataraman V. Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs[J]. IEEE Trans Electron Devices, 2006, 53(4): 706. doi: 10.1109/TED.2006.870424
[6]	Bansal A, Paul B C, Roy K. Modeling and optimization of fringe capacitance of nanoscale DGMOS devices[J]. IEEE Trans Electron Devices, 2005, 52(2): 256. doi: 10.1109/TED.2004.842713
[7]	Guo J C, Yeh C T. A new three-dimensional capacitor model for accurate simulation of parasitic capacitances in nanoscale MOSFETs[J]. IEEE Trans Electron Devices, 2009, 56(8): 1598. doi: 10.1109/TED.2009.2022679
[8]	Liu X, Jin X, Lee J H. A full analytical model of fringing-field-induced parasitic capacitance for nano-scaled MOSFETs[J]. Semicond Sci Technol, 2010, 25(12): 015008.
[9]	Sun J P, Wang W, Toyabe T. Modeling of gate current and capacitance in nanoscale-MOS structures[J]. IEEE Trans Electron Devices, 2006, 53(12): 2950. doi: 10.1109/TED.2006.885637
[10]	Ernst T, Ritzenthaler R, Faynot O. A model of fringing fields in short-channel planar and triple-gate SOI MOSFETs[J]. IEEE Trans Electron Devices, 2007, 54(6): 1366. doi: 10.1109/TED.2007.895241
[11]	Kumar M J, Venkataraman V, Gupta S K. On the parasitic gate capacitance of small-geometry MOSFETs[J]. IEEE Trans Electron Devices, 2005, 52(7): 1676. doi: 10.1109/TED.2005.850630
[12]	Guo J C, Yeh C T. A new three-dimensional capacitor model for accurate simulation of parasitic capacitances in nanoscale MOSFETs[J]. IEEE Trans Electron Devices, 2009, 56(8): 1598. doi: 10.1109/TED.2009.2022679
[13]	Moldovan O, Iñiguez B, Jiménez D. Analytical charge and capacitance models of undoped cylindrical surrounding-gate MOSFETs[J]. IEEE Trans Electron Devices, 2007, 54(1): 162. doi: 10.1109/TED.2006.887213
[14]	He J, Bian W, Tao Y. Analytic carrier-based charge and capacitance model for long-channel undoped surrounding-gate MOSFETs[J]. IEEE Trans Electron Devices, 2007, 54(6): 1478. doi: 10.1109/TED.2007.896595
[15]	Jiménez D, Iñíguez B, Suñél J. Continuous analytic Ⅰ-Ⅴ model for surrounding-gate MOSFETs[J]. IEEE Electron Device Lett, 2004, 25(8): 571. doi: 10.1109/LED.2004.831902
[16]	Sarkar A, De S, Dey A. A new analytical subthreshold model of SRG MOSFET with analogue performance investigation[J]. International Journal of Electronics, 2012, 99(2): 267. doi: 10.1080/00207217.2011.623278
[17]	Xu Q, Zou J, Luo J. Predictive modeling of capacitance and resistance in gate all around cylindrical nanowire MOSFETs for parasitic design optimization[J]. 10th IEEE International Conference on Solid State and Integrated Circuit Technology (ICSICT), Shanghai, 2010: 1958.
[18]	Sarkar A, De S, Dey A. Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model[J]. J Comput Electron, 2012, 11(2): 182. doi: 10.1007/s10825-012-0396-9
[19]	Zou J, Xu Q, Luo J. Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs[J]. IEEE Trans Electron Devices, 2011, 58(10): 3379. doi: 10.1109/TED.2011.2162521
[20]	Ge L, Fossum J G. Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs[J]. IEEE Trans Electron Devices, 2002, 49(2): 287. doi: 10.1109/16.981219
[21]	Chiang T K. Concise analytical threshold voltage model for cylindrical fully depleted surrounding-gate metal-oxide-semiconductor field effect transistors[J]. Jpn J Appl Phys, 2005, 44(5): 2948.
[22]	Kaur H, Kabra S, Haldar S. An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYSMGAS) surrounding gate MOSFET[J]. Solid-State Electron, 2008, 52(2): 305. doi: 10.1016/j.sse.2007.09.006
[23]	Auth C P, Plummer J D. Scaling theory for cylindrical fully-depleted surrounding gate MOSFET's[J]. IEEE Electron Device Lett, 1997, 18(2): 74. doi: 10.1109/55.553049
[24]	Kranti A, Haldar S, Gupta R S. Analytical model for threshold voltage and Ⅰ-Ⅴ characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET[J]. Microelectron Eng, 2001, 56: 241. doi: 10.1016/S0167-9317(00)00419-6
[25]	Faycal D, Mohamed Amir A, Djemai A. Surface-potential-based model to study the subthreshold swing behavior including hot-carrier effect for nanoscale GASGAA MOSFETs[J]. International conference on Design & Technology of Integrated Systems in Nanoscale Era, 2010: 1.
[26]	Young K K. Analysis of conduction in fully depleted SOI MOSFETs[J]. IEEE Trans Electron Devices, 1989, 36: 504. doi: 10.1109/16.19960
[27]	Gupta S K, Baishya S. Modeling and simulation of triple metal cylindrical surround gate MOSFETs for reduced short channel effects[J]. International Journal of Soft Computing and Engineering (IJSCE), 2012, 2(2): 214.
[28]	Gupta S K, Baishya S. Modeling of built-in potential variations of cylindrical surrounding gate (CSG) MOSFETs[J]. International Journal of VLSI Design and Communication Systems (VLSIC), 2012, 3(5): 67. doi: 10.5121/vlsic
[29]	Byerly W E. Elements of the integral calculus with a key to the solution of differential equations, and a short table of integrals. 2nd ed. Boston USA:Ginn and Company, 1892
[30]	Jahnke E, Emde F. Tables of functions with formulae and curves[J]. Dover Publications, 1943.
[31]	Nehari Z. Conformal mapping[J]. McGraw-Hill, 1952.
[32]	Kober H. Dictionary of conformal representations[J]. Dover Publications, 1957.
[33]	Dwight H B. Tables of integrals and other mathematical data. 3rd ed. New York, USA:The Macmillan Company, 1957
[34]	Churchill R V, Brown J W, Verhey R F. Complex variables and applications. 3rd ed[J]. McGraw Hill, 1976.
[35]	Smythe W R. Static and dynamic electricity. 3rd ed[J]. Taylor & Francis, 1989.

[1]	Shrivastava R, Fitzpatrick K. A simple model for the overlap capacitance of a VLSI MOS device[J]. IEEE Trans Electron Devices, 1982, 29(12): 1870. doi: 10.1109/T-ED.1982.21044
[2]	Greeneich E W. An analytical model for the gate capacitance of small-geometry MOS structures[J]. IEEE Trans Electron Devices, 1983, 30(12): 1838. doi: 10.1109/T-ED.1983.21456
[3]	Suzuki K. Parasitic capacitance of submicrometer MOSFET's[J]. IEEE Trans Electron Devices, 1999, 46(9): 1895. doi: 10.1109/16.784191
[4]	Mohapatra N R, Desai M P, Narendra S G. Modeling of parasitic capacitances in deep submicrometer conventional and high-k dielectric MOS transistors[J]. IEEE Trans Electron Devices, 2003, 50(4): 959. doi: 10.1109/TED.2003.811387
[5]	Kumar M J, Gupta S K, Venkataraman V. Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs[J]. IEEE Trans Electron Devices, 2006, 53(4): 706. doi: 10.1109/TED.2006.870424
[6]	Bansal A, Paul B C, Roy K. Modeling and optimization of fringe capacitance of nanoscale DGMOS devices[J]. IEEE Trans Electron Devices, 2005, 52(2): 256. doi: 10.1109/TED.2004.842713
[7]	Guo J C, Yeh C T. A new three-dimensional capacitor model for accurate simulation of parasitic capacitances in nanoscale MOSFETs[J]. IEEE Trans Electron Devices, 2009, 56(8): 1598. doi: 10.1109/TED.2009.2022679
[8]	Liu X, Jin X, Lee J H. A full analytical model of fringing-field-induced parasitic capacitance for nano-scaled MOSFETs[J]. Semicond Sci Technol, 2010, 25(12): 015008.
[9]	Sun J P, Wang W, Toyabe T. Modeling of gate current and capacitance in nanoscale-MOS structures[J]. IEEE Trans Electron Devices, 2006, 53(12): 2950. doi: 10.1109/TED.2006.885637
[10]	Ernst T, Ritzenthaler R, Faynot O. A model of fringing fields in short-channel planar and triple-gate SOI MOSFETs[J]. IEEE Trans Electron Devices, 2007, 54(6): 1366. doi: 10.1109/TED.2007.895241
[11]	Kumar M J, Venkataraman V, Gupta S K. On the parasitic gate capacitance of small-geometry MOSFETs[J]. IEEE Trans Electron Devices, 2005, 52(7): 1676. doi: 10.1109/TED.2005.850630
[12]	Guo J C, Yeh C T. A new three-dimensional capacitor model for accurate simulation of parasitic capacitances in nanoscale MOSFETs[J]. IEEE Trans Electron Devices, 2009, 56(8): 1598. doi: 10.1109/TED.2009.2022679
[13]	Moldovan O, Iñiguez B, Jiménez D. Analytical charge and capacitance models of undoped cylindrical surrounding-gate MOSFETs[J]. IEEE Trans Electron Devices, 2007, 54(1): 162. doi: 10.1109/TED.2006.887213
[14]	He J, Bian W, Tao Y. Analytic carrier-based charge and capacitance model for long-channel undoped surrounding-gate MOSFETs[J]. IEEE Trans Electron Devices, 2007, 54(6): 1478. doi: 10.1109/TED.2007.896595
[15]	Jiménez D, Iñíguez B, Suñél J. Continuous analytic Ⅰ-Ⅴ model for surrounding-gate MOSFETs[J]. IEEE Electron Device Lett, 2004, 25(8): 571. doi: 10.1109/LED.2004.831902
[16]	Sarkar A, De S, Dey A. A new analytical subthreshold model of SRG MOSFET with analogue performance investigation[J]. International Journal of Electronics, 2012, 99(2): 267. doi: 10.1080/00207217.2011.623278
[17]	Xu Q, Zou J, Luo J. Predictive modeling of capacitance and resistance in gate all around cylindrical nanowire MOSFETs for parasitic design optimization[J]. 10th IEEE International Conference on Solid State and Integrated Circuit Technology (ICSICT), Shanghai, 2010: 1958.
[18]	Sarkar A, De S, Dey A. Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model[J]. J Comput Electron, 2012, 11(2): 182. doi: 10.1007/s10825-012-0396-9
[19]	Zou J, Xu Q, Luo J. Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs[J]. IEEE Trans Electron Devices, 2011, 58(10): 3379. doi: 10.1109/TED.2011.2162521
[20]	Ge L, Fossum J G. Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs[J]. IEEE Trans Electron Devices, 2002, 49(2): 287. doi: 10.1109/16.981219
[21]	Chiang T K. Concise analytical threshold voltage model for cylindrical fully depleted surrounding-gate metal-oxide-semiconductor field effect transistors[J]. Jpn J Appl Phys, 2005, 44(5): 2948.
[22]	Kaur H, Kabra S, Haldar S. An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYSMGAS) surrounding gate MOSFET[J]. Solid-State Electron, 2008, 52(2): 305. doi: 10.1016/j.sse.2007.09.006
[23]	Auth C P, Plummer J D. Scaling theory for cylindrical fully-depleted surrounding gate MOSFET's[J]. IEEE Electron Device Lett, 1997, 18(2): 74. doi: 10.1109/55.553049
[24]	Kranti A, Haldar S, Gupta R S. Analytical model for threshold voltage and Ⅰ-Ⅴ characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET[J]. Microelectron Eng, 2001, 56: 241. doi: 10.1016/S0167-9317(00)00419-6
[25]	Faycal D, Mohamed Amir A, Djemai A. Surface-potential-based model to study the subthreshold swing behavior including hot-carrier effect for nanoscale GASGAA MOSFETs[J]. International conference on Design & Technology of Integrated Systems in Nanoscale Era, 2010: 1.
[26]	Young K K. Analysis of conduction in fully depleted SOI MOSFETs[J]. IEEE Trans Electron Devices, 1989, 36: 504. doi: 10.1109/16.19960
[27]	Gupta S K, Baishya S. Modeling and simulation of triple metal cylindrical surround gate MOSFETs for reduced short channel effects[J]. International Journal of Soft Computing and Engineering (IJSCE), 2012, 2(2): 214.
[28]	Gupta S K, Baishya S. Modeling of built-in potential variations of cylindrical surrounding gate (CSG) MOSFETs[J]. International Journal of VLSI Design and Communication Systems (VLSIC), 2012, 3(5): 67. doi: 10.5121/vlsic
[29]	Byerly W E. Elements of the integral calculus with a key to the solution of differential equations, and a short table of integrals. 2nd ed. Boston USA:Ginn and Company, 1892
[30]	Jahnke E, Emde F. Tables of functions with formulae and curves[J]. Dover Publications, 1943.
[31]	Nehari Z. Conformal mapping[J]. McGraw-Hill, 1952.
[32]	Kober H. Dictionary of conformal representations[J]. Dover Publications, 1957.
[33]	Dwight H B. Tables of integrals and other mathematical data. 3rd ed. New York, USA:The Macmillan Company, 1957
[34]	Churchill R V, Brown J W, Verhey R F. Complex variables and applications. 3rd ed[J]. McGraw Hill, 1976.
[35]	Smythe W R. Static and dynamic electricity. 3rd ed[J]. Taylor & Francis, 1989.

[1]	Ji Feng, Xu Jingping, Lai P T, Chen Weibing, Li Yanping. 2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs. J. Semicond., 2006, 27(10): 1725.
[2]	Li Ruizhen, Han Zhengsheng. An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs. J. Semicond., 2005, 26(12): 2303.
[3]	He Hongyu, Zheng Xueren. Analytical drain current model for amorphous IGZO thin-film transistors in above-threshold regime. J. Semicond., 2011, 32(7): 074004. doi: 10.1088/1674-4926/32/7/074004
[4]	Li Xiyue, Deng Wanling, Huang Junkai. A physical surface-potential-based drain current model for polysilicon thin-film transistors. J. Semicond., 2012, 33(3): 034005. doi: 10.1088/1674-4926/33/3/034005
[5]	Kong Ming, Guo Jianmin, Zhang Ke, Li Wenhong. A Novel CMOS Voltage Reference Based on Threshold Voltage Difference Between p-Type and n-Type MOSFETs. J. Semicond., 2007, 28(10): 1546.
[6]	Xu Bojuan, Du Gang, Xia Zhiliang, Zeng Lang, Han Ruqi, Liu Xiaoyan. Threshold Voltage Model of a Double-Gate MOSFET with Schottky Source and Drain. J. Semicond., 2007, 28(8): 1179.
[7]	Zhang Guohe, Shao Zhibiao, Zhou Kai. Threshold Voltage Model for a Fully Depleted SOI-MOSFETwith a Non-Uniform Profile. J. Semicond., 2007, 28(6): 842.
[8]	Tang Junxiong, Tang Minghua, Yang Feng, Zhang Junjie, Zhou Yichun, Zheng Xuejun. A Temperature-Dependent Model for Threshold Voltage and Potential Distribution of Fully Depleted SOI MOSFETs. J. Semicond., 2008, 29(1): 45.
[9]	Xiaoyu Ma, Wanling Deng, Junkai Huang. Explicit solution of channel potential and drain current model in symmetric double-gate polysilicon TFTs. J. Semicond., 2014, 35(3): 032002. doi: 10.1088/1674-4926/35/3/032002
[10]	Lu Jingxue, Huang Fengyi, Wang Zhigong, Wu Wengang. Refinement of an Analytical Approximation of the Surface Potential in MOSFETs. J. Semicond., 2006, 27(7): 1155.
[11]	Jie Wang, Lingling Sun, Jun Liu, Mingzhu Zhou. A surface-potential-based model for AlGaN/AlN/GaN HEMT. J. Semicond., 2013, 34(9): 094002. doi: 10.1088/1674-4926/34/9/094002
[12]	Jian Qin, Ruohe Yao. Modeling of current-voltage characteristics for dual-gate amorphous silicon thin-film transistors considering deep Gaussian density-of-state distribution. J. Semicond., 2015, 36(12): 124005. doi: 10.1088/1674-4926/36/12/124005
[13]	Xu Jian, Ding Lei, Han Zhengsheng, Zhong Chuanjie. Impact of Two-Dimension Effects on Threshold Voltage of Fully Depleted SOI MOSFETs with Asymmetric Halos. J. Semicond., 2008, 29(3): 559.
[14]	Chaowen Liu, Jingping Xu, Lu Liu, Hanhan Lu, Yuan Huang. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric. J. Semicond., 2016, 37(2): 024004. doi: 10.1088/1674-4926/37/2/024004
[15]	T. S. Arun Samuel, N. B. Balamurugan. Analytical modeling and simulation of germanium single gate silicon on insulator TFET. J. Semicond., 2014, 35(3): 034002. doi: 10.1088/1674-4926/35/3/034002
[16]	Huifang Xu, Yuehua Dai, Ning Li, Jianbin Xu. A 2-D semi-analytical model of double-gate tunnel field-effect transistor. J. Semicond., 2015, 36(5): 054002. doi: 10.1088/1674-4926/36/5/054002
[17]	Shoubhik Gupta, Bahniman Ghosh, Shiromani Balmukund Rahi. Compact analytical model of double gate junction-less field effect transistor comprising quantum-mechanical effect. J. Semicond., 2015, 36(2): 024001. doi: 10.1088/1674-4926/36/2/024001
[18]	Xu Jingbo, Zhang Haiying, Yin Junjian, Liu Liang, Li Xiao, Ye Tianchun, Li Ming. Monolithic Integration of 0.8μm Gate-Length GaAs-Based InGaP/AlGaAs/InGaAs Enhancement- and Depletion-Mode PHEMTs. J. Semicond., 2007, 28(9): 1424.
[19]	T. Chaudhary, G. Khanna. Analysis and impact of process variability on performance of junctionless double gate VeSFET. J. Semicond., 2017, 38(10): 104003. doi: 10.1088/1674-4926/38/10/104003
[20]	Xu Wenjie, Sun Lingling, Liu Jun, Li Wenjun, Zhang Haipeng, Wu Yanming, He Jia. A Continuous and Analytical Surface Potential Model for SOI LDMOS. J. Semicond., 2007, 28(11): 1712.

Search

GET CITATION

S K Gupta, S Baishya. Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects[J]. J. Semicond., 2013, 34(7): 074001. doi: 10.1088/1674-4926/34/7/074001.

Export: BibTex EndNote