J. Semicond. > Volume 35 > Issue 3 > Article Number: 032002

Explicit solution of channel potential and drain current model in symmetric double-gate polysilicon TFTs

Xiaoyu Ma , Wanling Deng and Junkai Huang

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Abstract: A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thin-film transistors has been derived based on an effective charge density approach of Poisson's equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminates the regional approach. Model predictions are compared to numerical simulations with close agreement, having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.

Key words: double-gatedrain currentsurface potentialpolysilicon thin-film transistor

Abstract: A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thin-film transistors has been derived based on an effective charge density approach of Poisson's equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminates the regional approach. Model predictions are compared to numerical simulations with close agreement, having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.

Key words: double-gatedrain currentsurface potentialpolysilicon thin-film transistor



References:

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Chen R, Zheng X, Deng W. A physical-based analytical solution tot the surface potential of polysilicon thin film transistors using the Lambert W function[J]. Solid-State Electron, 2007, 51(6): 975. doi: 10.1016/j.sse.2007.03.004

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Sehgal A, Mangla T, Chopra S. Physics based threshold voltage extraction and simulation for poly-crystalline thin film transistors using a double-gate structure[J]. Semicond Sci Technol, 2006, 21(3): 370. doi: 10.1088/0268-1242/21/3/028

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Wang L, Ren Y, Han D. Asynchronous double-gate polycrystalline silicon thin-film transistors for AM-OLED pixel circuits[J]. IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2012. doi: 10.1109/ICSICT.2012.6467841

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Huang J, Deng W, Zheng X. A compact model for undoped symmetric double-gate polysilicon thin-film transistors[J]. IEEE Trans Electron Devices, 2010, 57(10): 2607. doi: 10.1109/TED.2010.2060725

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Deng W, Zheng X, Chen R. A new poly-Si TFTs DC model for device characterization and circuit simulation[J]. Chinese Journal of Semiconductors, 2007, 28(12): 1916.

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Ortiz-Conde A, García-Sánchez F J, Muci J. A review of core compact models for undoped double-gate SOI MOSFETs[J]. IEEE Trans Electron Devices, 2007, 54(1): 131. doi: 10.1109/TED.2006.887046

[13]

Sallese J M, Chevillon N, Lallement C. Charge-based modeling of junctionless double-gate field-effect transistors[J]. IEEE Trans Electron Devices, 2011, 58(8): 2628. doi: 10.1109/TED.2011.2156413

[14]

Ortiz-Conde A, García-Sánchez F J, Malobabic S. Analytic solution of the channel potential in undoped symmetric dual-gate MOSFETs[J]. IEEE Trans Electron Devices, 2005, 52(7): 1669. doi: 10.1109/TED.2005.850629

[15]

Ortiz-Conde A, García-Sánchez F J, Muci J. Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs[J]. Solid State Electron, 2005, 49(4): 640. doi: 10.1016/j.sse.2005.01.017

[16]

He J, Liu F, Zhou X. A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region[J]. Chin Phys B, 2011, 20(1): 016102. doi: 10.1088/1674-1056/20/1/016102

[17]

He J, Zhang L, Zhang J. A complete surface potential-based core model for undoped symmetric double-gate MOSFETs[J]. Journal of Semiconductors, 2008, 29(11): 2092.

[18]

Jacunski M D, Shurn M S, Owusu A A. A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects[J]. IEEE Trans Electron Devices, 1999, 46(6): 1146. doi: 10.1109/16.766877

[19]

Park J H, Kim Y, Kim S. Surface-potential-based analytic DC I——V model with effective electron density for a-IGZO TFTs considering the parasitic resistance[J]. IEEE Electron Device Lett, 2011, 32(11): 1540. doi: 10.1109/LED.2011.2163810

[20]

Wang M, Wong M. An effective channel mobility-based analytical on-current model for polycrystalline silicon thin-film transistors[J]. IEEE Trans Electron Devices, 2007, 54(4): 869. doi: 10.1109/TED.2007.891248

[1]

Moschou D C, Theodorou C G, Hastas N A. Short channel effects on LTPS TFT degradation[J]. Journal of Display Technology, 2013, PP(99): 1.

[2]

Tsai C C, Lee Y J, Wang J L. High-performance top and bottom double-gate low temperature poly-silicon thin film transistors fabricated by excimer laser crystallization[J]. Solid State Electron, 2008, 52(3): 365. doi: 10.1016/j.sse.2007.10.029

[3]

Zhang S, Han R, Sin J K O. A novel self-aligned double-gate TFT technology[J]. IEEE Electron Device Lett, 2001, 22(11): 530. doi: 10.1109/55.962653

[4]

Tsai C C, Wei K F, Lee Y J. High-performance short-channel double-gate lowtemperature polysilicon thin-film transistors using excimer laser crystallization[J]. IEEE Electron Device Lett, 2007, 28(11): 1010. doi: 10.1109/LED.2007.908473

[5]

Lin H C, Lin Z M, Chen W C. Read characteristics of independent double-gate poly-Si nanowire SONOS devices[J]. IEEE Trans. Electron Devices, 2011, 58(11): 3771. doi: 10.1109/TED.2011.2164251

[6]

Tsuji H, Kuzuoka H, Kishida Y. Surface-potential-based drain current model for polycrystalline silicon thin-film transistors[J]. Jpa J Appl Phys, 2008, 47(10): 7798. doi: 10.1143/JJAP.47.7798

[7]

Chen R, Zheng X, Deng W. A physical-based analytical solution tot the surface potential of polysilicon thin film transistors using the Lambert W function[J]. Solid-State Electron, 2007, 51(6): 975. doi: 10.1016/j.sse.2007.03.004

[8]

Sehgal A, Mangla T, Chopra S. Physics based threshold voltage extraction and simulation for poly-crystalline thin film transistors using a double-gate structure[J]. Semicond Sci Technol, 2006, 21(3): 370. doi: 10.1088/0268-1242/21/3/028

[9]

Wang L, Ren Y, Han D. Asynchronous double-gate polycrystalline silicon thin-film transistors for AM-OLED pixel circuits[J]. IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2012. doi: 10.1109/ICSICT.2012.6467841

[10]

Huang J, Deng W, Zheng X. A compact model for undoped symmetric double-gate polysilicon thin-film transistors[J]. IEEE Trans Electron Devices, 2010, 57(10): 2607. doi: 10.1109/TED.2010.2060725

[11]

Deng W, Zheng X, Chen R. A new poly-Si TFTs DC model for device characterization and circuit simulation[J]. Chinese Journal of Semiconductors, 2007, 28(12): 1916.

[12]

Ortiz-Conde A, García-Sánchez F J, Muci J. A review of core compact models for undoped double-gate SOI MOSFETs[J]. IEEE Trans Electron Devices, 2007, 54(1): 131. doi: 10.1109/TED.2006.887046

[13]

Sallese J M, Chevillon N, Lallement C. Charge-based modeling of junctionless double-gate field-effect transistors[J]. IEEE Trans Electron Devices, 2011, 58(8): 2628. doi: 10.1109/TED.2011.2156413

[14]

Ortiz-Conde A, García-Sánchez F J, Malobabic S. Analytic solution of the channel potential in undoped symmetric dual-gate MOSFETs[J]. IEEE Trans Electron Devices, 2005, 52(7): 1669. doi: 10.1109/TED.2005.850629

[15]

Ortiz-Conde A, García-Sánchez F J, Muci J. Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs[J]. Solid State Electron, 2005, 49(4): 640. doi: 10.1016/j.sse.2005.01.017

[16]

He J, Liu F, Zhou X. A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region[J]. Chin Phys B, 2011, 20(1): 016102. doi: 10.1088/1674-1056/20/1/016102

[17]

He J, Zhang L, Zhang J. A complete surface potential-based core model for undoped symmetric double-gate MOSFETs[J]. Journal of Semiconductors, 2008, 29(11): 2092.

[18]

Jacunski M D, Shurn M S, Owusu A A. A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects[J]. IEEE Trans Electron Devices, 1999, 46(6): 1146. doi: 10.1109/16.766877

[19]

Park J H, Kim Y, Kim S. Surface-potential-based analytic DC I——V model with effective electron density for a-IGZO TFTs considering the parasitic resistance[J]. IEEE Electron Device Lett, 2011, 32(11): 1540. doi: 10.1109/LED.2011.2163810

[20]

Wang M, Wong M. An effective channel mobility-based analytical on-current model for polycrystalline silicon thin-film transistors[J]. IEEE Trans Electron Devices, 2007, 54(4): 869. doi: 10.1109/TED.2007.891248

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X Y Ma, W L Deng, J K Huang. Explicit solution of channel potential and drain current model in symmetric double-gate polysilicon TFTs[J]. J. Semicond., 2014, 35(3): 032002. doi: 10.1088/1674-4926/35/3/032002.

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Manuscript received: 22 August 2013 Manuscript revised: 01 November 2013 Online: Published: 01 March 2014

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