J. Semicond. > Volume 37 > Issue 1 > Article Number: 015004

A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS

Dong Li , Qiao Meng , and Fei Li

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Abstract: This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μ m 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter (DAC). In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.5 dB and spurious-free dynamic range (SFDR) of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2.

Key words: SAR ADCswitching schemeSAR control logicDACcomparator

Abstract: This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μ m 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter (DAC). In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.5 dB and spurious-free dynamic range (SFDR) of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2.

Key words: SAR ADCswitching schemeSAR control logicDACcomparator



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[1]

Confalonieri P, Zamprogno M, Girardi F. A 2.7 mW 1 MSps 10 b analog-to-digital converter with built-in reference buffer and 1 LSB accuracy programmable input ranges.[J]. Solid-State Circuits Conference (ESSCIRC), 2004.

[2]

Culurciello E, Andreou A G. An 8-bit 800-μW 1.23-MSs successive approximation ADC in SOI CMOS.[J]. IEEE Trans Circuits Syst:Express Briefs,, 2006, 53(9): 858.

[3]

Zhu Y, Chio U F, Wei H G. A power-efficient capacitor structure for high-speed charge recycling SAR ADCs[J]. IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008: 642.

[4]

Agnes A, Bonizzoni E, Malcovati P. A 9.4-ENOB 1 V 3.8 μW 100 kS/s SAR ADC with time-domain comparator.[J]. IEEE International Solid-State Circuits Conference (ISSCC), 2008, 245.

[5]

Ginsburg B P, Chandrakasan A P. 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC[J]. IEEE J Solid-State Circuits, 2007, 42(4): 739.

[6]

Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731.

[7]

Zhu Y, Chan C H, Chio U F. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE J Solid-State Circuits, 2010, 45(6): 1111.

[8]

Huang G Y, Chang S J, Liu C C. 10-bit 30-MS/s SAR ADC using a switchback switching method[J]. IEEE Trans VLSI Syst, 2013, 21(3): 584.

[9]

Hong H K, Kim W, Park S J. A 7 b 1 GS/s 7.2 mW non binary 2 b/cycle SAR ADC with register-to-DAC direct control.[J]. IEEE Custom Integrated Circuits Conference (CICC),, 2012.

[10]

Yang J, Naing T L, Brodersen R W. A 1 GS/s 6 bit 6.7 mW successive approximation ADC using asynchronous processing.[J]. IEEE J Solid-State Circuits,, 2010, 45(8): 1469.

[11]

Zhu Zhangming, Xiao Yu, Song Xiaoli. Vcm-based monotonic capacitor switching scheme for SAR ADC[J]. IET Electron Lett, 2013, 49(5): 327.

[12]

Zhu Zhangming, Qiu Zheng, Liu Maliang. A 6-to-10-bit 0.5 V-to-0.9 V reconfigurable 2 MS/s power scalable SAR ADC in 0.18 μm CMOS[J]. IEEE Trans Circuits Syst I:Regular Papers, 2015, 62(3): 689.

[13]

Xu R, Liu B, Yuan J. Digitally calibrated 768-kS/s 10-b minimum-size SAR ADC array with dithering[J]. IEEE J Solid-State Circuits, 2012, 47(9): 2129.

[14]

Qiao Ning, Zhang Guoquan, Yang Bo. A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18μm SOI CMOS technology.[J]. Journal of Semiconductors,, 2012, 33(9): 095005.

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D Li, Q Meng, F Li. A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS[J]. J. Semicond., 2016, 37(1): 015004. doi: 10.1088/1674-4926/37/1/015004.

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Manuscript received: 09 October 2015 Manuscript revised: Online: Published: 01 January 2016

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