J. Semicond. > Volume 39 > Issue 10 > Article Number: 105003

A high-efficiency charge pump in BCD process for implantable medical devices

Jie Zhang , Hong Zhang , and Ruizhi Zhang

+ Author Affilications + Find other works by these authors

PDF

Turn off MathJax

Abstract: This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS (BCD) technology for implantable medical devices. Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm2.

Key words: voltage doublercharge pumphigh-efficiencyimplantable medical device

Abstract: This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS (BCD) technology for implantable medical devices. Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm2.

Key words: voltage doublercharge pumphigh-efficiencyimplantable medical device



References:

[1]

Nagaraj S, Rassam F G. Improved noncoherent UWB receiver for implantable biomedical devices. IEEE Trans Biomed Eng, 2016, 63(10): 2220

[2]

Zhou J, Kim A, Ziaie B. An ultrasonically controlled power management system for implantable biomedical devices. IEEE Biomed Circuits Syst Conf, 2015: 1

[3]

Lee S Y, Hong J H, Hsieh C H, et al. A Low-power 13.56 MHz RF front-end circuit for implantable biomedical devices. IEEE Trans Biomed Circuits Syst, 2013, 7(3): 256

[4]

Wong L S Y, Hossain S, Ta A, et al. A very low-power CMOS mixed-signal IC for implantable pacemaker applications. IEEE J Solid-State Circuits, 2004, 39(12): 2446

[5]

Zhang J, Zhang H, Zhang R, et al. A mixed-signal ASIC for triple-chamber cardiac pacemakers with heart resistance measurement. IEEE Asian Solid-State Circuits Conference, 2015: 1

[6]

Yip M, Jin R, Nakajima H H, et al. A fully-implantable cochlear implant SoC with piezoelectric middle-ear sensor and arbitrary waveform neural stimulation. IEEE J Solid-State Circuits, 2015, 50(1): 214

[7]

Azin M, Guggenmos D J, Barbay S, et al. A battery-powered activity-dependent intracortical microstimulation IC for brain-machine-brain Interface. IEEE J Solid-State Circuits, 2011, 46(4): 731

[8]

Novo A, Gerosa A, Neviani A, et al. Programmable voltage multiplier for pacemaker output pulse generation. Electron Lett, 1999, 35(7): 560

[9]

Novo A, Gerosa A, Neviani A, et al. A CMOS 0.8 μm programmable charge pump for the output stage of an implantable pacemaker. IEEE International Caracas Conference on Devices, Circuits and Systems, 2000: 34/1

[10]

Gak J, Miguez M, Arnaud A. A programmable charge pump voltage converter for implantable medical devices in a HV technology. IEEE Latin American Symposium on Circuits and Systems, 2013: 1

[11]

Esmailiyan A, Shaker A, Ghotbi I, et al. A charge-pump based multi-mode stimuli generator for cardiac pacemaking. IEEE International New Circuits and Systems Conference, 2016: 1

[12]

Tanzawa T, Tanaka T. A dynamic analysis of the Dickson charge pump circuit. IEEE J Solid-State Circuits, 1997, 32(8): 1231

[13]

Baek J M, Chun J H, Kwon K W. A power-efficient voltage upconverter for embedded EEPROM application. IEEE Trans Circuits Syst II, 2010, 57(6): 435

[14]

Peng H, Tang N, Yang Y, et al. CMOS startup charge pump with body bias and backward control for energy harvesting step-up converters. IEEE Trans Circuits Syst I, 2014, 61(6): 1618

[15]

Tanzawa T. An optimum design for integrated switched-capacitor Dickson charge pump multipliers with area power balance. IEEE Trans Power Electron, 2014, 29(2): 534

[16]

Nakagome Y, Tanaka H, Takeuchi K, et al. An experimental 1.5-V 64-Mb DRAM. IEEE J Solid-State Circuits, 1991, 26(4): 465

[17]

Pelliconi R, Iezzi D, Baroni A, et al. Power efficient charge pump in deep submicron standard CMOS technology. IEEE J Solid-State Circuits, 2003, 38(6): 1068

[18]

Ying T, Ki W, Chan M. Area-efficient CMOS charge pumps for LCD drivers. IEEE J Solid-State Circuits, 2003, 8(10): 1721

[19]

Favrat P, Deval P, Declercq M J. A high-efficiency CMOS voltage doubler. IEEE J Solid-State Circuits, 1998, 33(3): 410

[20]

Shen L, Hofmann K. Fully integratable 4-phase charge pump architecture for high voltage applications. International Conference Mixed Design of Integrated Circuits and Systems, 2012: 265

[21]

Kim J, Mok P K T, Kim C. A 0.15 V input energy harvesting charge pump with dynamic body biasing and adaptive dead-time for efficiency improvement. IEEE J Solid-State Circuits, 2015, 50(2): 414

[1]

Nagaraj S, Rassam F G. Improved noncoherent UWB receiver for implantable biomedical devices. IEEE Trans Biomed Eng, 2016, 63(10): 2220

[2]

Zhou J, Kim A, Ziaie B. An ultrasonically controlled power management system for implantable biomedical devices. IEEE Biomed Circuits Syst Conf, 2015: 1

[3]

Lee S Y, Hong J H, Hsieh C H, et al. A Low-power 13.56 MHz RF front-end circuit for implantable biomedical devices. IEEE Trans Biomed Circuits Syst, 2013, 7(3): 256

[4]

Wong L S Y, Hossain S, Ta A, et al. A very low-power CMOS mixed-signal IC for implantable pacemaker applications. IEEE J Solid-State Circuits, 2004, 39(12): 2446

[5]

Zhang J, Zhang H, Zhang R, et al. A mixed-signal ASIC for triple-chamber cardiac pacemakers with heart resistance measurement. IEEE Asian Solid-State Circuits Conference, 2015: 1

[6]

Yip M, Jin R, Nakajima H H, et al. A fully-implantable cochlear implant SoC with piezoelectric middle-ear sensor and arbitrary waveform neural stimulation. IEEE J Solid-State Circuits, 2015, 50(1): 214

[7]

Azin M, Guggenmos D J, Barbay S, et al. A battery-powered activity-dependent intracortical microstimulation IC for brain-machine-brain Interface. IEEE J Solid-State Circuits, 2011, 46(4): 731

[8]

Novo A, Gerosa A, Neviani A, et al. Programmable voltage multiplier for pacemaker output pulse generation. Electron Lett, 1999, 35(7): 560

[9]

Novo A, Gerosa A, Neviani A, et al. A CMOS 0.8 μm programmable charge pump for the output stage of an implantable pacemaker. IEEE International Caracas Conference on Devices, Circuits and Systems, 2000: 34/1

[10]

Gak J, Miguez M, Arnaud A. A programmable charge pump voltage converter for implantable medical devices in a HV technology. IEEE Latin American Symposium on Circuits and Systems, 2013: 1

[11]

Esmailiyan A, Shaker A, Ghotbi I, et al. A charge-pump based multi-mode stimuli generator for cardiac pacemaking. IEEE International New Circuits and Systems Conference, 2016: 1

[12]

Tanzawa T, Tanaka T. A dynamic analysis of the Dickson charge pump circuit. IEEE J Solid-State Circuits, 1997, 32(8): 1231

[13]

Baek J M, Chun J H, Kwon K W. A power-efficient voltage upconverter for embedded EEPROM application. IEEE Trans Circuits Syst II, 2010, 57(6): 435

[14]

Peng H, Tang N, Yang Y, et al. CMOS startup charge pump with body bias and backward control for energy harvesting step-up converters. IEEE Trans Circuits Syst I, 2014, 61(6): 1618

[15]

Tanzawa T. An optimum design for integrated switched-capacitor Dickson charge pump multipliers with area power balance. IEEE Trans Power Electron, 2014, 29(2): 534

[16]

Nakagome Y, Tanaka H, Takeuchi K, et al. An experimental 1.5-V 64-Mb DRAM. IEEE J Solid-State Circuits, 1991, 26(4): 465

[17]

Pelliconi R, Iezzi D, Baroni A, et al. Power efficient charge pump in deep submicron standard CMOS technology. IEEE J Solid-State Circuits, 2003, 38(6): 1068

[18]

Ying T, Ki W, Chan M. Area-efficient CMOS charge pumps for LCD drivers. IEEE J Solid-State Circuits, 2003, 8(10): 1721

[19]

Favrat P, Deval P, Declercq M J. A high-efficiency CMOS voltage doubler. IEEE J Solid-State Circuits, 1998, 33(3): 410

[20]

Shen L, Hofmann K. Fully integratable 4-phase charge pump architecture for high voltage applications. International Conference Mixed Design of Integrated Circuits and Systems, 2012: 265

[21]

Kim J, Mok P K T, Kim C. A 0.15 V input energy harvesting charge pump with dynamic body biasing and adaptive dead-time for efficiency improvement. IEEE J Solid-State Circuits, 2015, 50(2): 414

[1]

Jiang Bowei, Wang Xiao, Min Hao. A Novel All-pMOS AC to DC Charge Pump with High Efficiency. J. Semicond., 2008, 29(4): 660.

[2]

Zhao Menglian, Wu Xiaobo, Han Shiming, Deng Li, Yan Dongqin, Yan Xiaolang. Research and Design of an On-Chip High Efficiency Dual-Output Charge Pump. J. Semicond., 2008, 29(7): 1305.

[3]

Zheng Ran, Wei Tingcun, Wang Jia, Gao Deyuan. An area-saving and high power efficiency charge pump built in a TFT-LCD driver IC. J. Semicond., 2009, 30(9): 095015. doi: 10.1088/1674-4926/30/9/095015

[4]

Li Zhiqun, Zheng Shuangshuang, Hou Ningbing. Design of a high performance CMOS charge pump for phase-locked loop synthesizers. J. Semicond., 2011, 32(7): 075007. doi: 10.1088/1674-4926/32/7/075007

[5]

Pang Zegui, Zhuang Yiqi, Li Xiaoming, Li Jun. A Low-Voltage, High Efficiency Power Generation Structure for UHF RFID. J. Semicond., 2008, 29(2): 293.

[6]

Moumita Mukherjee, Pravash R. Tripathy, S. P. Pati. Potential of asymmetrical Si/Ge and Ge/Si based hetero-junction transit time devices over homo-junction counterparts for generation of high power. J. Semicond., 2011, 32(11): 113001. doi: 10.1088/1674-4926/32/11/113001

[7]

Wang Songlin, Zhou Bo, Ye Qiang, Wang Hui, Guo Wangrui. A novel charge pump drive circuit for power MOSFETs. J. Semicond., 2010, 31(4): 045009. doi: 10.1088/1674-4926/31/4/045009

[8]

Li Xianrui, Lai Xinquan, Li Yushan, Ye Qiang. Research and design of a novel current mode charge pump. J. Semicond., 2009, 30(10): 105012. doi: 10.1088/1674-4926/30/10/105012

[9]

Xue Hong, Li Zhiqun, Wang Zhigong, Li Wei, Zhang Li. A Charge Pump Design for Low-Spur PLL. J. Semicond., 2007, 28(12): 1988.

[10]

Ye Qiang, Lai Xinquan, Xu Luping, Wang Hui, Zeng Huali, Chen Fuji. A multi-mode low ripple charge pump with active regulation. J. Semicond., 2009, 30(12): 125006. doi: 10.1088/1674-4926/30/12/125006

[11]

Cong Liu, Xinquan Lai, Hanxiao Du, Yuan Chi. A double-stage start-up structure to limit the inrush current used in current mode charge pump. J. Semicond., 2016, 37(6): 065006. doi: 10.1088/1674-4926/37/6/065006

[12]

Feng Yong, Peng Zhenfei, Yang Shanshan, Hong Zhiliang, Liu Yang. A dual mode charge pump with adaptive output used in a class G audio power amplifier. J. Semicond., 2011, 32(4): 045002. doi: 10.1088/1674-4926/32/4/045002

[13]

Fu Cong, Song Zhitang, Chen Houpeng, Cai Daolin, Wang Qian, Hong Xiao, Ding Sheng, Li Xi. A novel low ripple charge pump with a 2X/1.5X booster for PCM. J. Semicond., 2012, 33(9): 095001. doi: 10.1088/1674-4926/33/9/095001

[14]

Shengbo Zhang, Guangjun Yang, Jian Hu, Jun Xiao. A novel sourceline voltage compensation circuit for embedded NOR flash memory. J. Semicond., 2014, 35(7): 075007. doi: 10.1088/1674-4926/35/7/075007

[15]

Peng Qin, Jinbo Li, Jian Kang, Xiaoyong Li, Jianjun Zhou. Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm. J. Semicond., 2014, 35(9): 095007. doi: 10.1088/1674-4926/35/9/095007

[16]

A. Karthikeyan, P.S. Mallick. High-speed and low-power repeater for VLSI interconnects. J. Semicond., 2017, 38(10): 105006. doi: 10.1088/1674-4926/38/10/105006

[17]

Tao Yang, Yu Jiang, Shengyou Liu, Guiliang Guo, Yuepeng Yan. A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator. J. Semicond., 2015, 36(6): 065005. doi: 10.1088/1674-4926/36/6/065005

[18]

Zhao Zhenyu, Zhang Minxuan, Chen Shuming, Chen Jihua, Li Junfeng. A radiation-hardened-by-design technique for improving single-event transient tolerance of charge pumps in PLLs. J. Semicond., 2009, 30(12): 125009. doi: 10.1088/1674-4926/30/12/125009

[19]

Hua Chen, Renjie Gong, Xu Cheng, Yulin Zhang, Zhong Gao, Guiliang Guo, Yuepeng Yan. A 220-1100 MHz low phase-noise frequency synthesizer with wide-band VCO and selectable I/Q divider. J. Semicond., 2014, 35(12): 125006. doi: 10.1088/1674-4926/35/12/125006

[20]

Yin Haifeng, Wang Feng, Liu Jun, Mao Zhigang. A Low Jitter PLL in a 90nm CMOS Digital Process. J. Semicond., 2008, 29(8): 1511.

Search

Advanced Search >>

GET CITATION

J Zhang, H Zhang, R Z Zhang, A high-efficiency charge pump in BCD process for implantable medical devices[J]. J. Semicond., 2018, 39(10): 105003. doi: 10.1088/1674-4926/39/10/105003.

Export: BibTex EndNote

Article Metrics

Article views: 1056 Times PDF downloads: 46 Times Cited by: 0 Times

History

Manuscript received: 02 March 2018 Manuscript revised: 03 April 2018 Online: Uncorrected proof: 06 September 2018 Published: 09 October 2018

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误