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A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications

Quan Pan and Xiongshi Luo

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 Corresponding author: Quan Pan, panq@sustech.edu.cn

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Abstract: This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process. Multiple bandwidth enhancement techniques, including input bonding wire, input series on-chip inductive peaking and negative capacitance compensation, are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device, achieving an overall bandwidth enhancement ratio of 8.5. The electrical measurement shows TIA achieves 58 dBΩ up to 12.7 GHz with a 180-fF off-chip photodetector. The optical measurement demonstrates a clear open eye of 20 Gb/s. The TIA dissipates 4 mW from a 1.2-V supply voltage.

Key words: bandwidth enhancementCMOS optical receivercascodeinductive peakingnegative capacitancetransimpedance amplifier (TIA)



[1]
Li C, Palermo S. A low-power 26-GHz transformer-based regulated cascode SiGe BiCMOS transimpedance amplifier. IEEE J Solid State Circuits, 2013, 48, 1264 doi: 10.1109/JSSC.2013.2245059
[2]
Han J, Choi B, Seo M, et al. A 20-Gb/s transformer-based current-mode optical receiver in 0.13-μm CMOS. IEEE Trans Circuits Syst II, 2010, 57, 348 doi: 10.1109/TCSII.2010.2047309
[3]
Park S M, Yoo H J. 1.25-Gb/s regulated cascode CMOS transimpedance amplifier for gigabit Ethernet applications. IEEE J Solid State Circuits, 2004, 39, 112 doi: 10.1109/JSSC.2003.820884
[4]
Taghavi M H, Belostotski L, Haslett J W. A CMOS low-power cross-coupled immittance-converter transimpedance amplifier. IEEE Microw Wirel Compon Lett, 2015, 25, 403 doi: 10.1109/LMWC.2015.2421253
[5]
Schrodinger K, Stimma J, Mauthe M. A fully integrated CMOS receiver front-end for optic Gigabit Ethernet. IEEE J Solid State Circuits, 2002, 37, 874 doi: 10.1109/JSSC.2002.1015685
[6]
Kim J, Buckwalter J F. Bandwidth enhancement with low group-delay variation for a 40-Gb/s transimpedance amplifier. IEEE Trans Circuits Syst I, 2010, 57, 1964 doi: 10.1109/TCSI.2010.2041502
[7]
Pan Q, Wang Y P, Yue C P. A 42-dBΩ 25Gb/s CMOS transimpedance amplifier with multiple-peaking scheme for optical communications. IEEE Trans Circuits Syst II, 2020, 67, 72 doi: 10.1109/TCSII.2019.2901601
[8]
Atef M, Chen H, Zimmermann H. 10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology. 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013, 72
[9]
Li D, Liu M, Gao S W, et al. Low-noise broadband CMOS TIA based on multi-stage stagger-tuned amplifier for high-speed high-sensitivity optical communication. IEEE Trans Circuits Syst I, 2019, 66, 3676 doi: 10.1109/TCSI.2019.2916150
[10]
Kim S G, Hong C, Eo Y S, et al. A 40-GHz mirrored-cascode differential transimpedance amplifier in 65-nm CMOS. IEEE J Solid State Circuits, 2019, 54, 1468 doi: 10.1109/JSSC.2018.2886323
[11]
Razavi B. Design of integrated circuits for optical communication. John Wiley & Sons, Inc., 2002
[12]
Razavi B. A study of phase noise in CMOS oscillators. IEEE J Solid State Circuits, 1996, 31, 331 doi: 10.1109/4.494195
[13]
Taghavi M H, Belostotski L, Haslett J W, et al. 10-Gb/s 0.13-μm CMOS inductorless modified-RGC transimpedance amplifier. IEEE Trans Circuits Syst I, 2015, 62, 1971 doi: 10.1109/TCSI.2015.2440732
[14]
Ray S, Hella M M. A 53 dBΩ 7-GHz inductorless transimpedance amplifier and a 1-THz GBP limiting amplifier in 0.13-μm CMOS. IEEE Trans Circuits Syst I, 2018, 65, 2365 doi: 10.1109/TCSI.2017.2788799
[15]
Costanzo R, Bowers S M. A current reuse regulated cascode CMOS transimpedance amplifier with 11-GHz bandwidth. IEEE Microw Wirel Compon Lett, 2018, 28, 816 doi: 10.1109/LMWC.2018.2854594
[16]
Park K, Oh W S. A 40-Gb/s 310-fJ/b inverter-based CMOS optical receiver front-end. IEEE Photonics Technol Lett, 2015, 27, 1931 doi: 10.1109/LPT.2015.2447283
Fig. 1.  Schematic of the proposed TIA.

Fig. 2.  (Color online) Single-stage shunt resistive feedback TIA in (a) original inverter-based configuration, (b) proposed inverter-based cascode configuration, and (c) the comparison of voltage gain between inverter-based amplifier and inverter-based cascode amplifier.

Fig. 3.  Small-signal model of the proposed TIA.

Fig. 4.  (Color online) (a) BWER of Hs,in(s) in $\pm {25\%}\ Z_{\mathrm{i}\mathrm{n}}$. (b) Frequency response of the input series peaking network in target LBW, and (c) BWER of ZTIA(s) varies with LS.

Fig. 5.  (a) Schematic of negative impedance converter. (b) Half-circuit analysis of cross-couple topology.

Fig. 6.  (Color online) Post-layout simulation of progressive TIA bandwidth enhancement.

Fig. 7.  (Color online) Post-layout simulation of (a) TIA output noise and (b) IRN current.

Fig. 8.  (Color online) (a) Chip micrograph and (b) measurement setup.

Fig. 9.  (Color online) Measured transimpedance gain.

Fig. 10.  (Color online) Measured PRBS-15 optical eye diagram at 20 Gb/s.

Table 1.   Comparison of inverter-based and inverter-based cascode amplifier.

Parameter $ {C}_{\mathrm{i}\mathrm{n}} $$ {v}_{\mathrm{n},\mathrm{i}\mathrm{n},\mathrm{A}}^{2} $
Inv. Amp.$ {C}_{\mathrm{g}\mathrm{s},\mathrm{p}}+{C}_{\mathrm{g}\mathrm{s},\mathrm{n}}+(1+{A}_{\mathrm{v}})({C}_{\mathrm{g}\mathrm{d},\mathrm{n}}+{C}_{\mathrm{g}\mathrm{d},\mathrm{p}}) $$ \dfrac{4KT\gamma }{{(g}_{\mathrm{m}\mathrm{p}}+{g}_{\mathrm{m}\mathrm{n}})} $
Inv.cas Amp.$ {C}_{\mathrm{g}\mathrm{s},\mathrm{p}1}+{C}_{\mathrm{g}\mathrm{s},\mathrm{n}1}+\left(1+\dfrac{{g}_{\mathrm{m}\mathrm{p}1}}{{g}_{\mathrm{m}\mathrm{p}2}}\right){C}_{\mathrm{g}\mathrm{d},\mathrm{p}1}+\left(1+\dfrac{{g}_{\mathrm{m}\mathrm{n}1}}{{g}_{\mathrm{m}\mathrm{n}2}}\right){C}_{\mathrm{g}\mathrm{d},\mathrm{n}1} $$ \dfrac{4KT\gamma }{{(g}_{\mathrm{m}\mathrm{p}1}+{g}_{\mathrm{m}\mathrm{n}1})}+\dfrac{4KT\gamma {g}_{\mathrm{m}\mathrm{n}2}}{{{(g}_{\mathrm{m}\mathrm{p}1}+{g}_{\mathrm{m}\mathrm{n}1})}^{2}{\left(1+\dfrac{{g}_{\mathrm{m}\mathrm{n}1}}{s{C}_{\mathrm{d}\mathrm{s},\mathrm{n}1}}\right)}^{2}}+\dfrac{4KT\gamma {g}_{\mathrm{m}\mathrm{p}2}}{{{(g}_{\mathrm{m}\mathrm{p}1}+{g}_{\mathrm{m}\mathrm{n}1})}^{2}{\left(1+\dfrac{{g}_{\mathrm{m}\mathrm{p}1}}{s{C}_{\mathrm{d}\mathrm{s},\mathrm{p}1}}\right)}^{2}} $
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Table 2.   TIA performance comparison and summary.

SpecificationRef. [7]Ref. [8]Ref. [13]Ref. [14]Ref. [15]Ref. [16]This work
CMOS (nm)6540130130656565
TopologyInverter-basedInverter-based cascodeImmittance-converter RGCCGRGCInverter-basedInverter-based cascode
BW (GHz)246.89+771129.612.7
DR (Gb/s)2510+10^10NA4020
CPD (fF)2504502501000200100180
Gain (dBΩ)4255.3+50.153+625058
Supply (V)1.21.21.51.231.21.2
Power (mW)3*3.01*(+)7.5*12*10*12.4*4*
Active size (mm2)0.080.090.0160.080.08NA0.033
FoM252NA7526127775454
^ Electrical measurement. + Simulation result. * TIA power only (dummy and output buffer power excluded). FoM = Gain(Ω)·BW(GHz)·CPD(pF)/
Pwr(mW).
DownLoad: CSV
[1]
Li C, Palermo S. A low-power 26-GHz transformer-based regulated cascode SiGe BiCMOS transimpedance amplifier. IEEE J Solid State Circuits, 2013, 48, 1264 doi: 10.1109/JSSC.2013.2245059
[2]
Han J, Choi B, Seo M, et al. A 20-Gb/s transformer-based current-mode optical receiver in 0.13-μm CMOS. IEEE Trans Circuits Syst II, 2010, 57, 348 doi: 10.1109/TCSII.2010.2047309
[3]
Park S M, Yoo H J. 1.25-Gb/s regulated cascode CMOS transimpedance amplifier for gigabit Ethernet applications. IEEE J Solid State Circuits, 2004, 39, 112 doi: 10.1109/JSSC.2003.820884
[4]
Taghavi M H, Belostotski L, Haslett J W. A CMOS low-power cross-coupled immittance-converter transimpedance amplifier. IEEE Microw Wirel Compon Lett, 2015, 25, 403 doi: 10.1109/LMWC.2015.2421253
[5]
Schrodinger K, Stimma J, Mauthe M. A fully integrated CMOS receiver front-end for optic Gigabit Ethernet. IEEE J Solid State Circuits, 2002, 37, 874 doi: 10.1109/JSSC.2002.1015685
[6]
Kim J, Buckwalter J F. Bandwidth enhancement with low group-delay variation for a 40-Gb/s transimpedance amplifier. IEEE Trans Circuits Syst I, 2010, 57, 1964 doi: 10.1109/TCSI.2010.2041502
[7]
Pan Q, Wang Y P, Yue C P. A 42-dBΩ 25Gb/s CMOS transimpedance amplifier with multiple-peaking scheme for optical communications. IEEE Trans Circuits Syst II, 2020, 67, 72 doi: 10.1109/TCSII.2019.2901601
[8]
Atef M, Chen H, Zimmermann H. 10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology. 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013, 72
[9]
Li D, Liu M, Gao S W, et al. Low-noise broadband CMOS TIA based on multi-stage stagger-tuned amplifier for high-speed high-sensitivity optical communication. IEEE Trans Circuits Syst I, 2019, 66, 3676 doi: 10.1109/TCSI.2019.2916150
[10]
Kim S G, Hong C, Eo Y S, et al. A 40-GHz mirrored-cascode differential transimpedance amplifier in 65-nm CMOS. IEEE J Solid State Circuits, 2019, 54, 1468 doi: 10.1109/JSSC.2018.2886323
[11]
Razavi B. Design of integrated circuits for optical communication. John Wiley & Sons, Inc., 2002
[12]
Razavi B. A study of phase noise in CMOS oscillators. IEEE J Solid State Circuits, 1996, 31, 331 doi: 10.1109/4.494195
[13]
Taghavi M H, Belostotski L, Haslett J W, et al. 10-Gb/s 0.13-μm CMOS inductorless modified-RGC transimpedance amplifier. IEEE Trans Circuits Syst I, 2015, 62, 1971 doi: 10.1109/TCSI.2015.2440732
[14]
Ray S, Hella M M. A 53 dBΩ 7-GHz inductorless transimpedance amplifier and a 1-THz GBP limiting amplifier in 0.13-μm CMOS. IEEE Trans Circuits Syst I, 2018, 65, 2365 doi: 10.1109/TCSI.2017.2788799
[15]
Costanzo R, Bowers S M. A current reuse regulated cascode CMOS transimpedance amplifier with 11-GHz bandwidth. IEEE Microw Wirel Compon Lett, 2018, 28, 816 doi: 10.1109/LMWC.2018.2854594
[16]
Park K, Oh W S. A 40-Gb/s 310-fJ/b inverter-based CMOS optical receiver front-end. IEEE Photonics Technol Lett, 2015, 27, 1931 doi: 10.1109/LPT.2015.2447283
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    Received: 08 May 2021 Revised: 03 September 2021 Online: Accepted Manuscript: 04 November 2021Uncorrected proof: 05 November 2021Published: 04 January 2022

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      Quan Pan, Xiongshi Luo. A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications[J]. Journal of Semiconductors, 2022, 43(1): 012401. doi: 10.1088/1674-4926/43/1/012401 Q Pan, X S Luo, A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications[J]. J. Semicond., 2022, 43(1): 012401. doi: 10.1088/1674-4926/43/1/012401.Export: BibTex EndNote
      Citation:
      Quan Pan, Xiongshi Luo. A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications[J]. Journal of Semiconductors, 2022, 43(1): 012401. doi: 10.1088/1674-4926/43/1/012401

      Q Pan, X S Luo, A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications[J]. J. Semicond., 2022, 43(1): 012401. doi: 10.1088/1674-4926/43/1/012401.
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      A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications

      doi: 10.1088/1674-4926/43/1/012401
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      • Quan Pan:(S’08–M’14) received his BS degree in Electrical Engineering (EE) at the University of Science and Technology of China (USTC) in 2005, and his PhD degree in Electronics and Computer Engineering (ECE) at the Hong Kong University of Science and Technology (HKUST) in 2014. He is an Assistant Professor at School of Microelectronics, Southern University of Science and Technology since 2018. His research interests include high-speed optical transceiver, wireless and wireline circuit design
      • Xiongshi Luo:received the BS degress in microelectronics science and engineering from the Southern University of Science and Technology, Shenzhen, China, in 2019. He is currently persuing the MS degree in the same university. His research interests include high-speed serial links and optical interconnects
      • Corresponding author: panq@sustech.edu.cn
      • Received Date: 2021-05-08
      • Revised Date: 2021-09-03
      • Published Date: 2022-01-10

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