Abstract: A 4-kbit low-cost one-time programmable (OTP) memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor (1.5T) OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch (HVSW) circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification (RFID) tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600×600 μm2. The 4-kbit OTP macro only consumes 200×260 μm2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.
For embedded non-volatile memory (NVM) applications, a number of technologies are available. Embedded floating gate based electrically erasable programmable ROM (EEPROM), flash memory that can be rewritten many times, is available, although it often requires extra masks and process steps to fabricate. In result, it adds to the manufacturing costs, has low reliability and is harder to scale to the smaller geometry advanced process node[1-3]. Foundry fuses and e-fuses are also available. The program of the e-fuses memory heavily depends on current density, layout size and interconnects structure[4, 5], which typically requires larger footprints compared to other embedded NVM. They are not reliable enough when manufactured, making them impractical for larger data requirements, such as code storage, and unable to meet the field-programmable requirements. Anti-fuses (AF) one-time programmable (OTP) memory shows a useful low-cost solution for embedded applications, such as analog trimming, key encryption, RFID and chip ID, power management IC and redundancy repair of SRAM/DRAM[6] because of the ease of programming on-chip during manufacture or in-system, without any additional masks or processing steps and high reliability[7, 8].
The AF based on the gate oxide uses the breakdown of the gate oxide as a storage node and the program strongly depends on the thickness of the gate oxide. After oxide breakdown, the AF presents a permanently conducting state from the gate to the source/drain and behaves as a resistor. The resistance depends on the program current and time. For different programmed cells in the same chip, the equivalent resistances have a wide distribution range. The three transistor (3T) cell and two transistor (2T) cell based on the gate oxide were reported in Ref. [9, 10]. They are fully compatible with a standard CMOS process, but both have a large cell size because they use a separate PMOS cap as the AF device. In addition, they are 4-terminal and 3-terminal respectively, which makes their operation complex.
In this paper, a 2-terminal 1.5 transistor (1.5T) OTP cell based on gate oxide AF is proposed and implemented in a 0.18- $\mu $m standard CMOS process. The area of the cell is 2.13 $\mu $m $^{2}$, which is a 49.3% size reduction in comparison to the 3T cell[1]. The programmed cell works as a diode and shows a negative feedback from the bit line voltage to the read current, which makes the distribution range of the read current narrower. A novel high voltage switch (HVSW) circuit is also proposed to make sure the OTP macro implemented in a standard CMOS process works reliably when programming with high voltage. The 4-kbit OTP macro consisting of a 4-kbit array, row/column decoder, control logic, sense amplifier (SA), charge pump (CP) and HVSW is designed and embedded in RFID chips. The full chip is fabricated in a 0.18 $\mu$m process. The measurement shows a 100% program yield by adjusting the program time and obvious advantages in the core area and the power consumption compared to the reported 3T cell and 2T cell OTP cores.
2.
1.5 transistor OTP cell
The proposed 1.5T cell is composed of an access transistor coupled in series with an AF device, as shown in Fig. 1. The access transistor addresses the cell to be programmed and read or not; the AF device is for storage. Compared to the 3T cell[9], the high voltage (HV) blocking NMOS is reduced, but the cascode HV switching circuitry is added in the periphery. By sharing the source of the AF device and the drain of the access transistor and shorting their gates, the size of the proposed cell is 2.13 $\mu $m $^{2}$ in the 0.18- $\mu $m standard CMOS process and much smaller than the one transistor and one capacitor (1T1C) OTP cell[11] structure. When programming, the word line (WL) is biased to high voltage ( $V_{\rm PP}$) and the bit line (BL) is biased to zero. The oxide thicknesses of the access NMOS and the AF device are around 6.8 nm and 2.9 nm, respectively. Based on the silicon testing results of single thick oxide NMOS, the gate oxide breakdown voltage is about 10.6 V and the junction reverse breakdown voltage is about 8.9 V. Figure 2 shows the breakdown $I$- $V$ characteristics of the cell. Sweeping $V_{\rm PP}$ from 0 to 7 V and clamping the current to 100 $\mu $A, the breakdown voltage of the AF is around 6.3 V. So the thick oxide access transistor can withstand the program stress and works well.
Figure
1.
(a) Schematic of 1.5T OTP cell. (b) Cross-sectional view of the cell.
For 8 $\times $ 8 arrays in the testing chip, bias selected WL to 7 V and selected BL to 0 V. Program all the cells bit by bit. Read all the programmed bits one by one by changing WL to $V_{\rm DD}$. Figure 3 shows the read current distribution of statistics of 1.28-kbit. The average read current is more than 140 $\mu $A and there is no soft breakdown bit.
Figure
3.
The read current distribution of breakdown cells.
Figure 4 shows the average read current of 64 cells before programming and after programming. BL is biased to 0 and sweep WL from 0 to 1.8 V. Before programming, the read current is below 2 pA. After programming, the cell works as a diode. When WL $=$ 1.8 V, the current is around 150 $\mu $A. The current difference before and after programming is large enough for sense amplifier sensing out 0 and 1.
Figure
4.
The read current before programming and after programming.
Figure 5 shows the programming conditions of a 2 $\times$ 2 array with cell 1 being selected. The high program voltage $V_{\rm PP}$ is around 7 V. The selected WL is $V_{\rm PP}$ and unselected WL is 0; the selected BL is 0 and the unselected BL is $V_{\rm PP}$. In order to avoid the programming disturbance of the same WL, the $V_{\rm PP}$ timing of the unselected BL should come earlier than the selected WL. For the unselected cell 4, HV is now directly applied to the drain-substrate reverse junction of the access transistor, which is not destructive because of the channel being off, and the gate induced drain leakage (GIDL) through the drain-to-substrate junction can also be ignored. In read mode, bias the selected WL to $V_{\rm DD}$ (1.8 V) and unselected WL to 0. The selected BL to the sense amplifier (SA) is turned on and the unselected BL is turned off. Figure 5 shows the sense path.
Figure
5.
The OTP 2 $\times $ 2 array with cell 1 being biased to program.
For the 2 $\times$ 2 array, program cell 1 and cell 4 respectively; cell 2 and cell 3 are not programmed. Figure 6 shows the read current when sweeping BL from 0 to 600 mV. The read current of cell 2 and cell 3 are smaller than 30 pA, so there is no disturbing issue of the array. The read current of cell 1 and cell 4 decreases as the voltage of BL increases. For the read path shown in Fig. 5, the BL voltage is proportional to the read current. If the read current is too large or too small, the cell structure can negatively couple back the current effectively, since the programmed cell works as a diode. As a result, the distribution range of the read current in the macro core is narrower, which is easier for the design of a SA.
Figure
6.
Sweep the BL from 0 to 600 mV and read the current with cell 1 and cell 4 programmed, cell 2 and cell 3 not programmed.
The 4-kbit OTP memory macro is organized efficiently for low area consumption. Some circuit techniques are used in the macro to make the standard I/O transistors in the CMOS process work reliably with high program voltage. The macro consists of a 4-kbit array, row/column decoders, controlling logic, high voltage switches (HVSW), sense amplifier (SA) and charge pump (CP). The block diagram of the memory core is shown in Fig. 7. The HVSW shifts the voltage of the WL and the BL to $V_{\rm PP}$ in program mode or $V_{\rm DD}$ in read mode. Since the program voltage $V_{\rm PP}$ is around 7 V, which is much larger than the 3.3 V I/O transistor operation voltage, a new HVSW structure is proposed in this paper to make sure it works reliably. The SA block compares the cell current and reference current and senses out digital 0 or 1. This block strongly affects OTP macro read power, access time and chip yield. The charge pump is designed to provide the high voltage for the memory macro being programmed in-system. The CP should be strong enough to afford the program current. In the macro, we clamp the program current to around 100 $\mu $A/bit. Based on the power optimization principle[12] for the CP, the number of stages of the CP is eight for 7.4 V default output voltage and each stage capacitance is about 15 pF for about 100 $\mu $A current loads.
3.1
4-kbit memory array
The array is constructed by eight 512-bits blocks and each block is 64 $\times $ 8 bits cell. Eight blocks share 64 word lines, eight bit lines and one sense amplifier. Each WL and BL is connected to HVSW to get high voltage ( $V_{\rm PP}$) when programming. The selecting transistors of the blocks can limit the leakage current of BL from unselected blocks.
The program operation can be set in external $V_{\rm PP}$ mode by the $V_{\rm PP}$ pad or internal mode by the charge pump; the charge pump can provide 6.8/7.4/8/8.6 V program voltage with different setups. In program mode, the selected WL is $V_{\rm PP}$ while the BL is 0 V; the unselected WL is 0 V while the BL is $V_{\rm PP}$. Two terminals of AF of selected cells are biased to $V_{\rm PP}$. One needs to adjust the size of passing transistors of the WL and BL and the selecting transistors to decrease the IR drop consumption. In order to reduce the stress of I/O transistors, the small switches are used to make sure the $V_{\rm PP}$ ramps up step by step from $V_{\rm DD}$ to $V_{\rm PP}$. Specific timings are also designed for reliable programming operation: the high voltage of the BL should come earlier than the WL for unselected cells and the block selecting signal should turn on earlier than the WL selecting signal to prevent incorrect programming.
In read mode, $V_{\rm DD}$ is applied to the WL. The read current flowing from the breakdown AF to the BL is detected by the SA, while a very small tunneling current ( < 100 pA) flows at the non-programmed cell. The read current of a programmed cell is in the range from a few $\mu $A to several tens of $\mu $A with the average value being around 20 $\mu $A. The SA compares the read current with a reference current that can be set to 2/4/8 $\mu $A. If the read current is larger than the reference current, the output data is "1", otherwise it is "0".
3.2
High voltage switches
The HVSW is used to control the high voltage ( $V_{\rm PP}$) for programming. Standard I/O transistors usually cannot handle such high voltages reliably because of transistor gate oxide stress, punch through, junction stress and hot carrier injecting to the substrate and gate. Conventional high voltage switches in EEPROM use high voltage transistors such as LDMOS that require additional process modification. In order to tackle the stress problem when applying high voltage to the transistors, four transistors (M3-M6) in Fig. 8 are stacked to withstand the high voltage. These stacked protection transistors should be larger than other transistors. The gates of M3-M6 are biased to $V_{\rm M}$, which is around $V_{\rm PP}$/2 to make sure the gate oxide stress of all transistors would not be larger than $V_{\rm M}$. When IP is high, note A will be $V_{\rm M}$ - $V_{\rm tn}$ and note F will be $V_{\rm M}$ $+$ $V_{\rm tp}$. Note C will be $V_{\rm PP}$ and note D will be 0. In result, the largest $V_{\rm ds}$ of all the transistors is clamped to $V_{\rm M}$ $+V_{\rm t}$. The channel length of these transistors should be larger than the default smallest size to avoid punch through. M9-M12 are the driving stage. M11 and M12 should use a large size to decrease the IR drop when passing programming current. Compared to the HVSW introduced in Ref. [13], this design eliminates the gate oxide stress and decreases the junction stress.
Figure
8.
The circuit of proposed high voltage switch.
Another advantage of this design is no DC current consumption. But there is short-circuit current during the switch moment. When switching the input signal, NMOS (M1-M2) release the latch and PMOS (M7-M8) pull up the node voltage. Usually, it uses a larger NMOS size to release the latch quickly and a smaller PMOS size to decrease the short-circuit current since a large PMOS size would consume more current to fight against the pull-down NMOS. However, too small a PMOS size will increase the charging time. So it is the tradeoff between the power and the delay. In this OTP macro, we take more care of the power. The measurements of the OTP macro show the HVSW can work reliably at an 8 V program voltage.
4.
Implementation and measurements
The 4-kbit OTP macro was embedded in a passive RFID tag, which consists of an analog front-end (AFE), a digital control block and a 4-kbit OTP macro. The microphotograph of the implemented full chip is shown in Fig. 9. The chip was fabricated with a 1-poly 6-metal 0.18- $\mu$m standard CMOS process. The total area is 600 $\times $ 600 $\mu $m $^{2}$ including testing and bonding pads. The area of the 4-kbit OTP macro is 408 $\times $ 260 $\mu $m $^{2}$ including a charge pump block and 200 $\times $ 260 $\mu $m $^{2}$ without the charge pump block.
Figure
9.
The microphotograph of fabricated full chip.
A general test bench of the RFID system with ISO 14443A protocols, which is composed of readers controlled by a personal computer (PC), antennas and tags, was built for testing the chip. The reader transmits the handshake command, read commands and program commands, and receives the reading out data sent out by the tag. The first step of the testing is the handshake and setting the program voltage and reference current. Then, transfer to read mode. If all the read out data of the blank block are zero, go to program mode, else read fail. In program mode, we bias a 7.4 V voltage pulse provided by CP to the selected cell. The pulse width is 100 $\mu $s. After programming the bit, read out the data to verify it. If the data is consistent to the programmed data, go to the next bit, else add another program pulse. For one program operation, the maximum number of pulses to the same bit is 64. If the bit is always verified wrongly after 64 pulses of programming, we can also program it again manually. In the testing flow, we manually programmed the hard bits under ten times. Figure 10 shows the statistic programming results of 50 dies (200-kbit). The result shows 100% program yield within a maximum ten programming times (64 ms).
Table 1 shows the key features of the OTP macro and the contrast to Refs. [1, 8]. This work has significant advantages in core size. The maximum byte programming current consumption (all eight bits being programmed to high) is about 1.2 mA with 7.4 V $V_{\rm PP}$. In the read mode, the bit read current can be clamped to about 20 $\mu $A at 3.38 MHz with 1.8 V $V_{\rm DD}$. Compared to Ref. [1], the power consumption has been improved greatly.
This paper introduces a 1.5T OTP cell which has a 49.3% size reduction compared to Ref. [1]. The measurement showed that the cell worked with a large programming window and without any disturbance. The CMOS compatible HVSW for programming is also proposed, which has no DC current consumption. The 4-kbit OTP macro is designed and embedded in RFID tags and presents 100% program yield within 100 $\mu$A bit program current and the maximum 6.4 ms program time. The bit read current can be clamped to about 20 $\mu$A at 3.38 MHz with 1.8 V $V_{\rm DD}$. The advantages of low cost and low power consumption compared to the previously reported ones show promising applications in the system on chip (SOC) and as redundancy repair blocks of SRAM/DRAM.
References
[1]
Cha H K, Yun I, Kim J, et al. A 32-KB standard CMOS antifuse one-time programmable ROM embedded in a 16-bit microcontroller. IEEE J Solid-State Circuits, 2006, 41:2115 doi: 10.1109/JSSC.2006.880603
[2]
Yang Xiaonan, Wang Yong, Zhang Manhong. A novel 2-T structure memory device using a Si nanodot for embedded application. Journal of Semiconductors, 2011, 32(12):124007 doi: 10.1088/1674-4926/32/12/124007
[3]
Jia Xiaoyun, Feng Peng, Zhang Shengguang. An ultra-low-power area efficient non-volatile memeory in 0.18μm single-poly CMOS process for passive RFID tags. Journal of Semiconductors, 2013, 34(8):085004 doi: 10.1088/1674-4926/34/8/085004
[4]
Kothandaraman C, Iyer S K, Iyer S S. Electrically programmable fuse (eFUSE) using electromigration in silicides. IEEE Electron Device Lett, 2002, 23:523 doi: 10.1109/LED.2002.802657
[5]
Alavi M, Bohr M, Hicks J, et al. A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process. Technical Digest, International Electron Devices Meeting, 1997:855 http://www.smtnet.com/library/files/upload/prom-element.pdf
[6]
Wee J K, Min K S, Park J T, et al. A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs. IEEE J Solid-State Circuits, 2002, 37:251 doi: 10.1109/4.982432
[7]
Candelier P, Villani N, Schoellkopf J P, et al. One time programmable drift antifuse cell reliability. Proceedings 38th Annual 2000 IEEE International Reliability Physics Symposium, 2000:169 http://ieeexplore.ieee.org/document/843909/
[8]
Ito H, Namekawa T. Pure CMOS one-time programmable memory using gate-ox anti-fuse. Proceedings of the IEEE Custom Integrated Circuits Conference, 2004:469 doi: 10.1007/s11771-011-0669-7
[9]
Kim J, Lee K. Three-transistor one-time programmable (OTP) ROM cell array using standard CMOS gate oxide antifuse. IEEE Electron Device Lett, 2003, 24:589 doi: 10.1109/LED.2003.815429
Peng J, Rosendale G, Fliesler M. A novel embedded OTP NVM using standard foundry CMOS logic technology. NVSMW, 2006:24 doi: 10.1007/978-3-319-48339-9_9/fulltext.html
[12]
Palumbo G, Pappalardo D, Gaibotti M. Charge-pump circuits:power-consumption optimization. IEEE Trans Circuits Syst I-Fundamental Theory and Applications, 2002, 49:1535 doi: 10.1109/TCSI.2002.804544
[13]
Baek J M, Chun J H, Kwon K W. A power-efficient voltage upconverter for embedded EEPROM application. IEEE Trans Circuits Syst Ⅱ-Express Briefs, 2010, 57:435 doi: 10.1109/TCSII.2010.2048351
Fig. 1.
(a) Schematic of 1.5T OTP cell. (b) Cross-sectional view of the cell.
Cha H K, Yun I, Kim J, et al. A 32-KB standard CMOS antifuse one-time programmable ROM embedded in a 16-bit microcontroller. IEEE J Solid-State Circuits, 2006, 41:2115 doi: 10.1109/JSSC.2006.880603
[2]
Yang Xiaonan, Wang Yong, Zhang Manhong. A novel 2-T structure memory device using a Si nanodot for embedded application. Journal of Semiconductors, 2011, 32(12):124007 doi: 10.1088/1674-4926/32/12/124007
[3]
Jia Xiaoyun, Feng Peng, Zhang Shengguang. An ultra-low-power area efficient non-volatile memeory in 0.18μm single-poly CMOS process for passive RFID tags. Journal of Semiconductors, 2013, 34(8):085004 doi: 10.1088/1674-4926/34/8/085004
[4]
Kothandaraman C, Iyer S K, Iyer S S. Electrically programmable fuse (eFUSE) using electromigration in silicides. IEEE Electron Device Lett, 2002, 23:523 doi: 10.1109/LED.2002.802657
[5]
Alavi M, Bohr M, Hicks J, et al. A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process. Technical Digest, International Electron Devices Meeting, 1997:855 http://www.smtnet.com/library/files/upload/prom-element.pdf
[6]
Wee J K, Min K S, Park J T, et al. A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs. IEEE J Solid-State Circuits, 2002, 37:251 doi: 10.1109/4.982432
[7]
Candelier P, Villani N, Schoellkopf J P, et al. One time programmable drift antifuse cell reliability. Proceedings 38th Annual 2000 IEEE International Reliability Physics Symposium, 2000:169 http://ieeexplore.ieee.org/document/843909/
[8]
Ito H, Namekawa T. Pure CMOS one-time programmable memory using gate-ox anti-fuse. Proceedings of the IEEE Custom Integrated Circuits Conference, 2004:469 doi: 10.1007/s11771-011-0669-7
[9]
Kim J, Lee K. Three-transistor one-time programmable (OTP) ROM cell array using standard CMOS gate oxide antifuse. IEEE Electron Device Lett, 2003, 24:589 doi: 10.1109/LED.2003.815429
Peng J, Rosendale G, Fliesler M. A novel embedded OTP NVM using standard foundry CMOS logic technology. NVSMW, 2006:24 doi: 10.1007/978-3-319-48339-9_9/fulltext.html
[12]
Palumbo G, Pappalardo D, Gaibotti M. Charge-pump circuits:power-consumption optimization. IEEE Trans Circuits Syst I-Fundamental Theory and Applications, 2002, 49:1535 doi: 10.1109/TCSI.2002.804544
[13]
Baek J M, Chun J H, Kwon K W. A power-efficient voltage upconverter for embedded EEPROM application. IEEE Trans Circuits Syst Ⅱ-Express Briefs, 2010, 57:435 doi: 10.1109/TCSII.2010.2048351
Chinese Journal of Semiconductors , 2005, 26(3): 436-442.
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Xian Li, Huicai Zhong, Cheng Jia, Xin Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. Journal of Semiconductors, 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007
X Li, H C Zhong, C Jia, X Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. J. Semicond., 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007.
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Received: 08 October 2013Revised: 10 November 2013Online:Published: 01 May 2014
Xian Li, Huicai Zhong, Cheng Jia, Xin Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. Journal of Semiconductors, 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007 ****X Li, H C Zhong, C Jia, X Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. J. Semicond., 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007.
Citation:
Xian Li, Huicai Zhong, Cheng Jia, Xin Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. Journal of Semiconductors, 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007
****
X Li, H C Zhong, C Jia, X Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. J. Semicond., 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007.
Xian Li, Huicai Zhong, Cheng Jia, Xin Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. Journal of Semiconductors, 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007 ****X Li, H C Zhong, C Jia, X Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. J. Semicond., 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007.
Citation:
Xian Li, Huicai Zhong, Cheng Jia, Xin Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. Journal of Semiconductors, 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007
****
X Li, H C Zhong, C Jia, X Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. J. Semicond., 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007.
A 4-kbit low-cost one-time programmable (OTP) memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor (1.5T) OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch (HVSW) circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification (RFID) tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600×600 μm2. The 4-kbit OTP macro only consumes 200×260 μm2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.
For embedded non-volatile memory (NVM) applications, a number of technologies are available. Embedded floating gate based electrically erasable programmable ROM (EEPROM), flash memory that can be rewritten many times, is available, although it often requires extra masks and process steps to fabricate. In result, it adds to the manufacturing costs, has low reliability and is harder to scale to the smaller geometry advanced process node[1-3]. Foundry fuses and e-fuses are also available. The program of the e-fuses memory heavily depends on current density, layout size and interconnects structure[4, 5], which typically requires larger footprints compared to other embedded NVM. They are not reliable enough when manufactured, making them impractical for larger data requirements, such as code storage, and unable to meet the field-programmable requirements. Anti-fuses (AF) one-time programmable (OTP) memory shows a useful low-cost solution for embedded applications, such as analog trimming, key encryption, RFID and chip ID, power management IC and redundancy repair of SRAM/DRAM[6] because of the ease of programming on-chip during manufacture or in-system, without any additional masks or processing steps and high reliability[7, 8].
The AF based on the gate oxide uses the breakdown of the gate oxide as a storage node and the program strongly depends on the thickness of the gate oxide. After oxide breakdown, the AF presents a permanently conducting state from the gate to the source/drain and behaves as a resistor. The resistance depends on the program current and time. For different programmed cells in the same chip, the equivalent resistances have a wide distribution range. The three transistor (3T) cell and two transistor (2T) cell based on the gate oxide were reported in Ref. [9, 10]. They are fully compatible with a standard CMOS process, but both have a large cell size because they use a separate PMOS cap as the AF device. In addition, they are 4-terminal and 3-terminal respectively, which makes their operation complex.
In this paper, a 2-terminal 1.5 transistor (1.5T) OTP cell based on gate oxide AF is proposed and implemented in a 0.18- $\mu $m standard CMOS process. The area of the cell is 2.13 $\mu $m $^{2}$, which is a 49.3% size reduction in comparison to the 3T cell[1]. The programmed cell works as a diode and shows a negative feedback from the bit line voltage to the read current, which makes the distribution range of the read current narrower. A novel high voltage switch (HVSW) circuit is also proposed to make sure the OTP macro implemented in a standard CMOS process works reliably when programming with high voltage. The 4-kbit OTP macro consisting of a 4-kbit array, row/column decoder, control logic, sense amplifier (SA), charge pump (CP) and HVSW is designed and embedded in RFID chips. The full chip is fabricated in a 0.18 $\mu$m process. The measurement shows a 100% program yield by adjusting the program time and obvious advantages in the core area and the power consumption compared to the reported 3T cell and 2T cell OTP cores.
2.
1.5 transistor OTP cell
The proposed 1.5T cell is composed of an access transistor coupled in series with an AF device, as shown in Fig. 1. The access transistor addresses the cell to be programmed and read or not; the AF device is for storage. Compared to the 3T cell[9], the high voltage (HV) blocking NMOS is reduced, but the cascode HV switching circuitry is added in the periphery. By sharing the source of the AF device and the drain of the access transistor and shorting their gates, the size of the proposed cell is 2.13 $\mu $m $^{2}$ in the 0.18- $\mu $m standard CMOS process and much smaller than the one transistor and one capacitor (1T1C) OTP cell[11] structure. When programming, the word line (WL) is biased to high voltage ( $V_{\rm PP}$) and the bit line (BL) is biased to zero. The oxide thicknesses of the access NMOS and the AF device are around 6.8 nm and 2.9 nm, respectively. Based on the silicon testing results of single thick oxide NMOS, the gate oxide breakdown voltage is about 10.6 V and the junction reverse breakdown voltage is about 8.9 V. Figure 2 shows the breakdown $I$- $V$ characteristics of the cell. Sweeping $V_{\rm PP}$ from 0 to 7 V and clamping the current to 100 $\mu $A, the breakdown voltage of the AF is around 6.3 V. So the thick oxide access transistor can withstand the program stress and works well.
Figure
1.
(a) Schematic of 1.5T OTP cell. (b) Cross-sectional view of the cell.
For 8 $\times $ 8 arrays in the testing chip, bias selected WL to 7 V and selected BL to 0 V. Program all the cells bit by bit. Read all the programmed bits one by one by changing WL to $V_{\rm DD}$. Figure 3 shows the read current distribution of statistics of 1.28-kbit. The average read current is more than 140 $\mu $A and there is no soft breakdown bit.
Figure
3.
The read current distribution of breakdown cells.
Figure 4 shows the average read current of 64 cells before programming and after programming. BL is biased to 0 and sweep WL from 0 to 1.8 V. Before programming, the read current is below 2 pA. After programming, the cell works as a diode. When WL $=$ 1.8 V, the current is around 150 $\mu $A. The current difference before and after programming is large enough for sense amplifier sensing out 0 and 1.
Figure
4.
The read current before programming and after programming.
Figure 5 shows the programming conditions of a 2 $\times$ 2 array with cell 1 being selected. The high program voltage $V_{\rm PP}$ is around 7 V. The selected WL is $V_{\rm PP}$ and unselected WL is 0; the selected BL is 0 and the unselected BL is $V_{\rm PP}$. In order to avoid the programming disturbance of the same WL, the $V_{\rm PP}$ timing of the unselected BL should come earlier than the selected WL. For the unselected cell 4, HV is now directly applied to the drain-substrate reverse junction of the access transistor, which is not destructive because of the channel being off, and the gate induced drain leakage (GIDL) through the drain-to-substrate junction can also be ignored. In read mode, bias the selected WL to $V_{\rm DD}$ (1.8 V) and unselected WL to 0. The selected BL to the sense amplifier (SA) is turned on and the unselected BL is turned off. Figure 5 shows the sense path.
Figure
5.
The OTP 2 $\times $ 2 array with cell 1 being biased to program.
For the 2 $\times$ 2 array, program cell 1 and cell 4 respectively; cell 2 and cell 3 are not programmed. Figure 6 shows the read current when sweeping BL from 0 to 600 mV. The read current of cell 2 and cell 3 are smaller than 30 pA, so there is no disturbing issue of the array. The read current of cell 1 and cell 4 decreases as the voltage of BL increases. For the read path shown in Fig. 5, the BL voltage is proportional to the read current. If the read current is too large or too small, the cell structure can negatively couple back the current effectively, since the programmed cell works as a diode. As a result, the distribution range of the read current in the macro core is narrower, which is easier for the design of a SA.
Figure
6.
Sweep the BL from 0 to 600 mV and read the current with cell 1 and cell 4 programmed, cell 2 and cell 3 not programmed.
The 4-kbit OTP memory macro is organized efficiently for low area consumption. Some circuit techniques are used in the macro to make the standard I/O transistors in the CMOS process work reliably with high program voltage. The macro consists of a 4-kbit array, row/column decoders, controlling logic, high voltage switches (HVSW), sense amplifier (SA) and charge pump (CP). The block diagram of the memory core is shown in Fig. 7. The HVSW shifts the voltage of the WL and the BL to $V_{\rm PP}$ in program mode or $V_{\rm DD}$ in read mode. Since the program voltage $V_{\rm PP}$ is around 7 V, which is much larger than the 3.3 V I/O transistor operation voltage, a new HVSW structure is proposed in this paper to make sure it works reliably. The SA block compares the cell current and reference current and senses out digital 0 or 1. This block strongly affects OTP macro read power, access time and chip yield. The charge pump is designed to provide the high voltage for the memory macro being programmed in-system. The CP should be strong enough to afford the program current. In the macro, we clamp the program current to around 100 $\mu $A/bit. Based on the power optimization principle[12] for the CP, the number of stages of the CP is eight for 7.4 V default output voltage and each stage capacitance is about 15 pF for about 100 $\mu $A current loads.
3.1
4-kbit memory array
The array is constructed by eight 512-bits blocks and each block is 64 $\times $ 8 bits cell. Eight blocks share 64 word lines, eight bit lines and one sense amplifier. Each WL and BL is connected to HVSW to get high voltage ( $V_{\rm PP}$) when programming. The selecting transistors of the blocks can limit the leakage current of BL from unselected blocks.
The program operation can be set in external $V_{\rm PP}$ mode by the $V_{\rm PP}$ pad or internal mode by the charge pump; the charge pump can provide 6.8/7.4/8/8.6 V program voltage with different setups. In program mode, the selected WL is $V_{\rm PP}$ while the BL is 0 V; the unselected WL is 0 V while the BL is $V_{\rm PP}$. Two terminals of AF of selected cells are biased to $V_{\rm PP}$. One needs to adjust the size of passing transistors of the WL and BL and the selecting transistors to decrease the IR drop consumption. In order to reduce the stress of I/O transistors, the small switches are used to make sure the $V_{\rm PP}$ ramps up step by step from $V_{\rm DD}$ to $V_{\rm PP}$. Specific timings are also designed for reliable programming operation: the high voltage of the BL should come earlier than the WL for unselected cells and the block selecting signal should turn on earlier than the WL selecting signal to prevent incorrect programming.
In read mode, $V_{\rm DD}$ is applied to the WL. The read current flowing from the breakdown AF to the BL is detected by the SA, while a very small tunneling current ( < 100 pA) flows at the non-programmed cell. The read current of a programmed cell is in the range from a few $\mu $A to several tens of $\mu $A with the average value being around 20 $\mu $A. The SA compares the read current with a reference current that can be set to 2/4/8 $\mu $A. If the read current is larger than the reference current, the output data is "1", otherwise it is "0".
3.2
High voltage switches
The HVSW is used to control the high voltage ( $V_{\rm PP}$) for programming. Standard I/O transistors usually cannot handle such high voltages reliably because of transistor gate oxide stress, punch through, junction stress and hot carrier injecting to the substrate and gate. Conventional high voltage switches in EEPROM use high voltage transistors such as LDMOS that require additional process modification. In order to tackle the stress problem when applying high voltage to the transistors, four transistors (M3-M6) in Fig. 8 are stacked to withstand the high voltage. These stacked protection transistors should be larger than other transistors. The gates of M3-M6 are biased to $V_{\rm M}$, which is around $V_{\rm PP}$/2 to make sure the gate oxide stress of all transistors would not be larger than $V_{\rm M}$. When IP is high, note A will be $V_{\rm M}$ - $V_{\rm tn}$ and note F will be $V_{\rm M}$ $+$ $V_{\rm tp}$. Note C will be $V_{\rm PP}$ and note D will be 0. In result, the largest $V_{\rm ds}$ of all the transistors is clamped to $V_{\rm M}$ $+V_{\rm t}$. The channel length of these transistors should be larger than the default smallest size to avoid punch through. M9-M12 are the driving stage. M11 and M12 should use a large size to decrease the IR drop when passing programming current. Compared to the HVSW introduced in Ref. [13], this design eliminates the gate oxide stress and decreases the junction stress.
Figure
8.
The circuit of proposed high voltage switch.
Another advantage of this design is no DC current consumption. But there is short-circuit current during the switch moment. When switching the input signal, NMOS (M1-M2) release the latch and PMOS (M7-M8) pull up the node voltage. Usually, it uses a larger NMOS size to release the latch quickly and a smaller PMOS size to decrease the short-circuit current since a large PMOS size would consume more current to fight against the pull-down NMOS. However, too small a PMOS size will increase the charging time. So it is the tradeoff between the power and the delay. In this OTP macro, we take more care of the power. The measurements of the OTP macro show the HVSW can work reliably at an 8 V program voltage.
4.
Implementation and measurements
The 4-kbit OTP macro was embedded in a passive RFID tag, which consists of an analog front-end (AFE), a digital control block and a 4-kbit OTP macro. The microphotograph of the implemented full chip is shown in Fig. 9. The chip was fabricated with a 1-poly 6-metal 0.18- $\mu$m standard CMOS process. The total area is 600 $\times $ 600 $\mu $m $^{2}$ including testing and bonding pads. The area of the 4-kbit OTP macro is 408 $\times $ 260 $\mu $m $^{2}$ including a charge pump block and 200 $\times $ 260 $\mu $m $^{2}$ without the charge pump block.
Figure
9.
The microphotograph of fabricated full chip.
A general test bench of the RFID system with ISO 14443A protocols, which is composed of readers controlled by a personal computer (PC), antennas and tags, was built for testing the chip. The reader transmits the handshake command, read commands and program commands, and receives the reading out data sent out by the tag. The first step of the testing is the handshake and setting the program voltage and reference current. Then, transfer to read mode. If all the read out data of the blank block are zero, go to program mode, else read fail. In program mode, we bias a 7.4 V voltage pulse provided by CP to the selected cell. The pulse width is 100 $\mu $s. After programming the bit, read out the data to verify it. If the data is consistent to the programmed data, go to the next bit, else add another program pulse. For one program operation, the maximum number of pulses to the same bit is 64. If the bit is always verified wrongly after 64 pulses of programming, we can also program it again manually. In the testing flow, we manually programmed the hard bits under ten times. Figure 10 shows the statistic programming results of 50 dies (200-kbit). The result shows 100% program yield within a maximum ten programming times (64 ms).
Table 1 shows the key features of the OTP macro and the contrast to Refs. [1, 8]. This work has significant advantages in core size. The maximum byte programming current consumption (all eight bits being programmed to high) is about 1.2 mA with 7.4 V $V_{\rm PP}$. In the read mode, the bit read current can be clamped to about 20 $\mu $A at 3.38 MHz with 1.8 V $V_{\rm DD}$. Compared to Ref. [1], the power consumption has been improved greatly.
This paper introduces a 1.5T OTP cell which has a 49.3% size reduction compared to Ref. [1]. The measurement showed that the cell worked with a large programming window and without any disturbance. The CMOS compatible HVSW for programming is also proposed, which has no DC current consumption. The 4-kbit OTP macro is designed and embedded in RFID tags and presents 100% program yield within 100 $\mu$A bit program current and the maximum 6.4 ms program time. The bit read current can be clamped to about 20 $\mu$A at 3.38 MHz with 1.8 V $V_{\rm DD}$. The advantages of low cost and low power consumption compared to the previously reported ones show promising applications in the system on chip (SOC) and as redundancy repair blocks of SRAM/DRAM.
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Xian Li, Huicai Zhong, Cheng Jia, Xin Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. Journal of Semiconductors, 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007 ****X Li, H C Zhong, C Jia, X Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. J. Semicond., 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007.
Xian Li, Huicai Zhong, Cheng Jia, Xin Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. Journal of Semiconductors, 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007
****
X Li, H C Zhong, C Jia, X Li. A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications[J]. J. Semicond., 2014, 35(5): 055007. doi: 10.1088/1674-4926/35/5/055007.
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