Fig. 1.
Proposed clock generator.
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| Citation: |
Lei Zhao, Yintang Yang, Zhangming Zhu, Lianxi Liu. A clock generator for a high-speed high-resolution pipelined A/D converter[J]. Journal of Semiconductors, 2013, 34(2): 025003. doi: 10.1088/1674-4926/34/2/025003
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L Zhao, Y T Yang, Z M Zhu, L X Liu. A clock generator for a high-speed high-resolution pipelined A/D converter[J]. J. Semicond., 2013, 34(2): 025003. doi: 10.1088/1674-4926/34/2/025003.
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A clock generator for a high-speed high-resolution pipelined A/D converter
DOI: 10.1088/1674-4926/34/2/025003
More Information
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Abstract
A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop (DLL), and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 μm 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.-
Keywords:
- duty cycle stabilizer,
- clock jitter,
- dynamic logic,
- non-overlap clock
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References
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