1. Introduction

At W-band, although HEMTs have established record power levels^{[1, 2]}, the double heterojunction bipolar transistor (DHBT) is still under development since its improved linearity characteristics over high electron mobility field effect transistors (HEMTs)^[3]. Compared to silicon-based transistor technology, an InP HBT usually has higher maximum oscillation frequency (${f_{{\text{max}}}}$), which pushes the transistor's application towards terahertz. The highest reported power level of a W-band HBT amplifier is 19 dBm @ 75 GHz^[4]. However, the HBT power amplifiers reported^[5-8] mostly have low gain, which is only about ten dB. So in practice a drive amplifier is often used before the power amplifier, yet it increases the area and cost.

In this paper, a two-stage cascode W-band DHBT MMIC power amplifier is presented with the topology shown in Fig. 1. The transistor is grown on a 3-inch InP wafer with an epitaxial profile designed for high frequency power application. The device exhibits ${f_{{\text{max}}}}$ of 253 GHz, $B{V_{{\text{ceo}}}}$ of 6 V, ${J_{{\text{max}}}}$ of 1.6 mA/$\mu m$^{2[9, 10]}. In order to achieve high gain in a small chip area, first, a two-stage cascode topology is employed; second, cell layouts with less parasitic effect are rigorously examined; third, a dual-frequency transformer^[11] is employed which acts as power splitter or power combiner. The output stage is matched at the impedance determined from load pull simulation to deliver the maximum RF power. Each cascode pair is biased at class A operation for high power gain and high linearity. All the passive components are simulated by a momentum electro-magnetic (EM) simulator, and then co-simulated with the nonlinear HBT models^{[8, 12]} in an ADS EDA environment^[13] to predicate the small-signal and large-signal performances.

2. Cell unit design

Two kinds of cell-units are designed: the two-cascode-pairunit and the four-cascode-pair unit. Design of the two cell-units is similar. The schematic and layout of the four-cascode pair unit are shown respectively in Figs. 2(a) and 2(b). The MIM capacitors at the base electrode of the second transistor in the cascode structure ensure RF short to ground. The MIM capacitors' parasites have a strong effect on the cell's gain and stability^[14]. By making their resonating frequencies near the working frequency, the parasites are diminished. The interconnecting lines between the two HBTs in the cascode structure have radiation loss and cross coupling to the base bias line below. By minimizing the length of the interconnecting lines and the width of the base bias line, the radiation loss and the cross coupling are reduced. The layouts are fine-tuned to ensure that the stability factor $K$ is slightly above 1 and the maximum stable gain (MSG) is as high as possible. The connections at the cell's input and output are fine-tuned to reduce the amplitude and phase differences among the four cascode pairs so as to obtain the highest possible output power.

Electro-thermal coupling has been studied through simulation and test verification^[15]. The most important self-heating effect in a single HBT is base voltage regression. By use of a current source, this effect can be avoided. For multiple-finger HBTs, current hogging may happen and must be prevented since it degrades the bandwidth and the output power. From elementary feedback theory, the cell unit is thermally stable if the thermal stability factor $\gamma$ is less than 1^{[14, 16]}

$\label{eq1} \gamma =\frac{{{\rm d}V_{\rm be}}/{\rm d}T} {{kT}/{qI_{\rm c}+R_{\rm e}}}V_{\rm ce} R_{\rm th} <1,$

(1)

where $d{V_{{\text{be}}}}{\text{/dT}}$ is the thermal-electric feedback coefficient, ${R_{\text{e}}}$ is the parasitic emitter resistance, and ${R_{\text{th}}}$ is the HBT's thermal resistance. From Eq. (1), by widening the space between the emitters, ${R_{\text{th}}}$ is reduced and in the meantime the collector current ${I_{\text{c}}}$ is limited so that $K$ satisfies Eq. (1) and current hogging does not occur. The cascode pair is biased at $I_{\rm B}=$ 150 $\mu$A, ${V_{\text{M}}}$ $=$ 2.5 V, ${V_{\text{C}}}$ $=$ 3.5 V, ${I_{\text{c}}}$ $=$ 11 mA. Co-simulation of the device models and the cell layout shows that for the two-cascode-pair cell unit, MSG, $K$ and the saturated output power are 15.6 dB, 2.7 and 12.6 dBm; for the four-cascode-pair cell unit, they are 16.8 dB, 1.1, and 14.7 dBm. The higher MSG of the four-cascode-pair cell unit results from the stability factor$K$ decrease due to excessive parasitic inductance of the MIM capacitor. This can be compensated by the loss of the subsequent power combiner.

3. Matching network design

The source and load impedance ${{\text{Z}}_{\text{0}}}$ is 50 $\Omega$. Conjugate impedance matching is employed for the two-cascode-pair cell unit to acquire high gain. The corresponding source impedance ${{\text{Z}}_{\text{S1}}}$ is 3.0 -j*4.0 $\Omega$, the load impedance ${{\text{Z}}_{\text{L1}}}$ is 3.5 $+$ j*20.1 $\Omega$. To obtain the maximum output power, the optimum load impedance ${{\text{Z}}_{\text{L2}}}$ for the four-cascode-pair cell unit is determined from load pull simulation, which is 4.7 $+$ j*3.6 $\Omega$. The input of this cell is conjugate matched and the corresponding source impedance ${{\text{Z}}_{\text{S2}}}$ is 2.2 $-$ j*10.9 $\Omega$.

Fully distributed transmission lines are selected for impedance matching because they are less sensitive to component spread and have fewer parasites than the lumped components. For the input and output matching networks, the two-section dual-frequency transformer^{[11, 17]} is adopted, which comprises the sections L₁, L₂, $L_{1}'$, $L_{2}'$, as shown in Fig. 3. In the input stage, a short serial high-impedance transmission line Z₄, L₄ and two same parallel low-impedance stubs Z₃, L₃ transform the cell's input impedance ${\text{Z}}_{_{{\text{S1}}}}^ *$ to a real one ${R_{{\text{L1}}}}$ at first. Then two sections with characteristic impedances of Z₁, Z₂ and physical lengths of L₁, L₂ are utilized to transform ${R_{{\text{L1}}}}$ to ${{\text{Z}}_{\text{0}}}$ at two distinct frequencies ${f_1}$, ${f_2}$. Z₁, L₁, Z₂, L₂ can be acquired with the help of a Smith chart. The initial values of L₁, L₂, Z₁, Z₂ are calculated as

$m=f_2/f_1,$

(2)

$\alpha=\tan^2\left(1+\frac{\pi}{1+m} \right),$

(3)

$L_1=L_2=\frac{\lambda_1}{2(1+m)}$

(4)

$\begin{split} Z_1={}& \Bigg\{\frac{Z_0}{2\alpha}\left(R_L-4Z_0\right) \\[2mm]& \left. +\sqrt{\left[\frac{2Z_0}{2\alpha}(R_{\rm L}-4Z_0)\right]^2+16Z_0^3R_{\rm L}}\right\}^{1/2}, \end{split}$

(5)

$Z_2=\frac{2Z_0R_{\rm L}}{Z_1},$

(6)

where $\lambda_1$ is the line propagation wavelength at ${f_1}$. Numerical method is used to further optimize these parameters for broadband and low transmission loss. The EM simulation results indicate insertion loss less than 1.2 dB and the 3 dB pass-band covering the whole W band when terminated with fixed impedance.

For the inter-stage matching network, in addition to impedance transform, the inter-stage network also provides DC feeding paths and DC blocks separating the drain and gate supplies. A ladder-like matching network employing edge-coupled lines is developed as shown in Fig. 4. In order to make the network synthesizable, a lump model for the edge-coupled lines is build. The size of the edge-coupled lines compromises between the high value of capacitance and low value of parasitic inductance. ${Z_{\text{L}}}$, ${Z_{\text{R}}}$ are selected so that the whole matching network can give wide pass-band and low loss. After optimization, the EM simulation results indicate the insertion loss below 2.5 dB and the 3-dB pass-band above 20 GHz when the terminal ports are of fixed impedances.

The developed ladder-like network can not only be used for impedance matching between stages of the same number of cell-units, but can also be used for matching between N and 2N cell-units by just moving the couple capacitors to the middle points of each pair in the 2N cell-units.

4. Bias network design and stability analysis

The circuit is kept in vertical mirror symmetry as possible as we can from both an electrical and a layout point of view. This helps to avoid odd-mode oscillations^[18]. So two same bias networks (shown in Fig. 5) are included on both sides which also facilitate assembling in T/R modules. MIM capacitors followed by parallel RC series are used to ensure grounding of in-band signals and absorption of out-of-band signals. Potential low-frequency oscillations are further suppressed by resistively loaded quarter-wave stubs at the right-angle bends in the output combining network.

Due to the vertical mirror symmetry, even-and odd-mode signals exist in the circuit shown in Fig. 6. For even mode, the points T₁, T₁₂ are terminated with impedance 2${{\text{Z}}_{\text{0}}}$ and the $K$-$\Delta$_S criteria still works which requires the proviso that the system is stable for one specific set of passive terminations^[19-21]. For odd mode, points ${{\text{T}}_{\text{1}}}$, ${{\text{T}}_{{\text{12}}}}$ are virtually grounded^[18]. From Freitag's method, ${R_{\text{i}}}$ and ${R_{\text{i}}}$ (shown in Fig. 3) are selected as 10 $\Omega$ and 5 $\Omega$ respectively to ensure the odd-mode stability and parametric oscillations^[22]. The simulated stability factor $K$ for the whole circuit is bigger than 1 across DC-110 GHz which enables the even-mode stability, as shown in Fig. 7. The minimum value of $K$ is 2.8 and it is located in the pass band, which means high power gain at these frequencies. This is just what we want.

Aside from possible even-and odd-mode oscillations, there can also be other kinds of loop oscillations due to the asymmetry in the top or bottom half circuit. So the open-loop power wave transfer characteristics with the break point at ${{\text{T}}_{\text{3}}}$, ${{\text{T}}_{\text{4}}}$, ${{\text{T}}_{\text{5}}}$, ${{\text{T}}_{\text{6}}}$ respectively are analyzed. The Nyquist curves are plotted as in Fig. 8. Also the Nyquist curves with the break points at ${{\text{T}}_{\text{8}}}$, ${{\text{T}}_{\text{9}}}$, ${{\text{T}}_{{\text{10}}}}$, ${{\text{T}}_{{\text{11}}}}$ are analyzed. All of these curves do not encircle the critical point 1 $+$ j*0 clockwise, which indicates that no oscillations should occur. The circuit is further simulated by a transient method and the voltage waves at the points ${{\text{T}}_{\text{2}}}$-${{\text{T}}_{{\text{11}}}}$ are inspected to guarantee that no oscillation occurs in the time domain.

5. Simulations and measurements

The whole passive layouts are divided into six passive sections and EM-simulated by using MOMENTUM software. Then the HBT transistor models are embedded and co-simulated with the $S$-parameters of the six passive sections in the schematic environment. The output power is predicted using the harmonic balance method.

Figure 9 shows a photograph of the fabricated MMIC. The chip size is 1.5 $\times$ 1.7 mm$^2$. On-wafer RF measurements are performed by using a frequency-expanded HP8510C W-band vector network analyzer. For the input stage, the collect current is 90 mA, the collector voltage ${V_{\text{C}}}$1 is 4 V; for the output stage, the collect current is 176 mA, the collector voltage ${V_{\text{C}}}$2 is 3.5 V. ${V_{\text{C}}}$2 is less than ${V_{\text{C}}}$1 to guarantee that the heat and temperature rise for the four-cascode-pair cell unit in the output stage should not be too high. The total power consumption is 980 mW. Figure 10 shows the measured W-band small-signal responses in comparison to the simulated results. It can be seen that the small signal gain is more than 20 dB over 75.5-84.5 GHz. The trends of the simulated and measured S₂₁ curves are the same, while the actual pass-band moves lower. This may result from the fitting error of the HBT models at W band, which needs further perfection. In the vicinity of 77 GHz, S₂₁ exceeds 0 dB. S₂₂ can be reduced below 0 dB when the collector bias current is lowered to 140 mA, as shown in Fig. 11. Although Fig. 10 demonstrates potential instability, oscillation does not actually occur, which is verified by the spectrum measurement shown in Fig. 12 (the low amplitude is due to the high conversion loss). Analysis shows that the parasitic inductances of the strip lines at the input and output of the cell and the ground finiteness may cause this phenomenon. The ground finiteness is required by wafer processing. Improvements on process are underway to resolve this problem.

The output power is measured with an Agilent E4417A power meter and W8486A power sensor, as shown in Fig. 13. The W-band source comes from Farran's multiplier, which delivers about 15 dBm power over the W-band. By adjusting the attenuation value of the variable attenuator, the MMIC is driven into saturation gradually. Losses of the waveguides, probes, and attenuator are compensated. Figure 14 shows the measured ${P_{{\text{out}}}}$-${P_{{\text{in}}}}$ curve at 79 GHz. Measurements show the MMIC has a linear gain of 24 dB and a saturated output power of 16.9 dBm (49.1 mW) with gain of 15.2 dB.

Figure 15 displays the curves of the statured output power and the corresponding input power curves vs. frequency. As can be seen, the saturated power is above 14 dBm over 75–88 GHz. At the high frequency end, the output power drops because the MMIC is not driven into saturation due to gain decline.

A comparison of several representative published millimeter-wave HBT power amplifier designs is presented in Table 1. It shows that this power amplifier has the greatest power gain. Its output power is also comparable to the reported amplifier manufactured in HBT technology.

6. Conclusion

A two-stage W-band cascode DHBT MMIC power amplifier is designed and fabricated. Cascode structures help to achieve high gain in a small chip area and to ensure wide-band stability. The cell units are carefully designed to ensure good amplitude/phase consistencies between different cascode pairs. Low-$Q$ matching networks contribute to wide pass-band and low insertion loss. Transistors at the output stage are matched for maximum power delivery. The chip size is 1.5 $\times$ 1.7 mm$^2$. Measurements show that the small signal gain is above 20 dB over 75.5-84.5 GHz, and the maximum output power is 16.9 dBm (49.1 mW) @ 79 GHz with gain of 15.2 dB. The signal gain precedes other reported HBT power amplifiers at this frequency band.